[all-commits] [llvm/llvm-project] f563cc: AMDGPU/GlobalISel: RegBankLegalize rules for load

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/new-rbs-rb-load-rules
  Home:   https://github.com/llvm/llvm-project
  Commit: f563ccef965406f4df3a4481142795de32e596f4
      https://github.com/llvm/llvm-project/commit/f563ccef965406f4df3a4481142795de32e596f4
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-12-05 (Thu, 05 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: RegBankLegalize rules for load

Add IDs for bit width that cover multiple LLTs: B32 B64 etc.
"Predicate" wrapper class for bool predicate functions used to
write pretty rules. Predicates can be combined using &&, || and !.
Lowering for splitting and widening loads.
Write rules for loads to not change existing mir tests from old
regbankselect.



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