[all-commits] [llvm/llvm-project] 2ec06c: [𝘀𝗽𝗿] initial version

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/tri-remove-reserved-registers-in-getregpressuresetlimit
  Home:   https://github.com/llvm/llvm-project
  Commit: 2ec06c7094cff66d31d05e07565cdfa937b03494
      https://github.com/llvm/llvm-project/commit/2ec06c7094cff66d31d05e07565cdfa937b03494
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-12-05 (Thu, 05 Dec 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/RegisterClassInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/RegisterClassInfo.cpp
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
    M llvm/test/CodeGen/NVPTX/misched_func_call.ll
    M llvm/test/CodeGen/PowerPC/aix-csr-alloc.mir
    M llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
    M llvm/test/CodeGen/PowerPC/compute-regpressure.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
    M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
    M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
    M llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
    M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
    M llvm/test/CodeGen/X86/sse-regcall.ll
    M llvm/test/CodeGen/X86/sse-regcall4.ll
    M llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll
    M llvm/test/TableGen/bare-minimum-psets.td
    M llvm/test/TableGen/inhibit-pset.td
    M llvm/unittests/CodeGen/MFCommon.inc
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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