[all-commits] [llvm/llvm-project] 6caf9f: [X86] combineStore - fold scalar float store(fabs/...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6caf9f82365a4b377c8ed22e737be14170f2ec9f
      https://github.com/llvm/llvm-project/commit/6caf9f82365a4b377c8ed22e737be14170f2ec9f
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-12-05 (Thu, 05 Dec 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/combine-fabs.ll
    M llvm/test/CodeGen/X86/combine-fneg.ll
    M llvm/test/CodeGen/X86/fsxor-alignment.ll

  Log Message:
  -----------
  [X86] combineStore - fold scalar float store(fabs/fneg(load())) -> store(and/xor(load(),c)) (#118680)

As noted on #117557 - its not worth performing scalar float fabs/fneg on the fpu if we're not doing any other fp ops.

This is currently limited to store + load pairs - I could try to extend this further if necessary, but we need to be careful that we don't end up in an infinite loop with the DAGCombiner foldBitcastedFPLogic combine.

Fixes #117557



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