[all-commits] [llvm/llvm-project] 15a9f4: AMDGPU/GlobalISel: AMDGPURegBankLegalize

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/new-rbs-rb-legalize
  Home:   https://github.com/llvm/llvm-project
  Commit: 15a9f499e20e6289e27ac0704a0a545abf91e3c0
      https://github.com/llvm/llvm-project/commit/15a9f499e20e6289e27ac0704a0a545abf91e3c0
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-12-04 (Wed, 04 Dec 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    A llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    A llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
    A llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    A llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir

  Log Message:
  -----------
  AMDGPU/GlobalISel: AMDGPURegBankLegalize

Lower G_ instructions that can't be inst-selected with register bank
assignment from AMDGPURegBankSelect based on uniformity analysis.
- Lower instruction to perform it on assigned register bank
- Put uniform value in vgpr because SALU instruction is not available
- Execute divergent instruction in SALU - "waterfall loop"

Given LLTs on all operands after legalizer, some register bank
assignments require lowering while other do not.
Note: cases where all register bank assignments would require lowering
are lowered in legalizer.

AMDGPURegBankLegalize goals:
- Define Rules: when and how to perform lowering
- Goal of defining Rules it to provide high level table-like brief
  overview of how to lower generic instructions based on available
  target features and uniformity info (uniform vs divergent).
- Fast search of Rules, depends on how complicated Rule.Predicate is
- For some opcodes there would be too many Rules that are essentially
  all the same just for different combinations of types and banks.
  Write custom function that handles all cases.
- Rules are made from enum IDs that correspond to each operand.
  Names of IDs are meant to give brief description what lowering does
  for each operand or the whole instruction.
- AMDGPURegBankLegalizeHelper implements lowering algorithms

Since this is the first patch that actually enables -new-reg-bank-select
here is the summary of regression tests that were added earlier:
- if instruction is uniform always select SALU instruction if available
- eliminate back to back vgpr to sgpr to vgpr copies of uniform values
- fast rules: small differences for standard and vector instruction
- enabling Rule based on target feature - salu_float
- how to specify lowering algorithm - vgpr S64 AND to S32
- on G_TRUNC in reg, it is up to user to deal with truncated bits
  G_TRUNC in reg is treated as no-op.
- dealing with truncated high bits - ABS S16 to S32
- sgpr S1 phi lowering
- new opcodes for vcc-to-scc and scc-to-vcc copies
- lowering for vgprS1-to-vcc copy (formally this is vgpr-to-vcc G_TRUNC)
- S1 zext and sext lowering to select
- uniform and divergent S1 AND(OR and XOR) lowering - inst-selected into
  SALU instruction
- divergent phi with uniform inputs
- divergent instruction with temporal divergent use, source instruction
  is defined as uniform(AMDGPURegBankSelect) - missing temporal
  divergence lowering
- uniform phi, because of undef incoming, is assigned to vgpr. Will be
  fixed in AMDGPURegBankSelect via another fix in machine uniformity
  analysis.



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