[all-commits] [llvm/llvm-project] 99b862: [DAGISel][ARM] Fix vector truncate combine for big...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 99b862efba9c2db5ec0aa32f62b5bc78df61d7a4
      https://github.com/llvm/llvm-project/commit/99b862efba9c2db5ec0aa32f62b5bc78df61d7a4
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2024-12-04 (Wed, 04 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/ARM/vector-trunc.ll

  Log Message:
  -----------
  [DAGISel][ARM] Fix vector truncate combine for big-endian (#118101)

This DAG combine was incorrect for big-endian targets, because it
assumes that when a bitcast changes the lane width, the
least-significant bits of the wider lanes are in the lower-numbered
lanes of the smaller type, which is only true for little-endian.



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