[all-commits] [llvm/llvm-project] 148fdc: [GlobalISel] Add G_ABDS and G_ABDU instructions (#...

[Thorsten Schütt via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 148fdc519cd25b36db9da61a6c6cabe86268dc58
      https://github.com/llvm/llvm-project/commit/148fdc519cd25b36db9da61a6c6cabe86268dc58
  Author: Thorsten Schütt <schuett at gmail.com>
  Date:   2024-12-04 (Wed, 04 Dec 2024)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
    A llvm/test/MachineVerifier/test_abd_su.mir
    M llvm/test/TableGen/GlobalISelEmitter.td

  Log Message:
  -----------
  [GlobalISel] Add G_ABDS and G_ABDU instructions (#118122)

The DAG has the same instructions: the signed and unsigned absolute
difference of it's input. For AArch64, they map to uabd and sabd for
Neon and SVE. The Neon and SVE instructions will require custom
patterns.

They are pseudo opcodes and are not imported by the IRTranslator. We
need combines to create them.

PowerPC, ARM, and AArch64 have native instructions.

/// i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1) 
///  or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1)

For GlobalISel, we are going to write the combines in MIR patterns.

see:
llvm/test/CodeGen/AArch64/abd-combine.ll

- [ ] combine into abd
- [ ] legalize and add td patterns



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