[all-commits] [llvm/llvm-project] 1e7171: [AArch64] Add tablegen patterns for concat(extract...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e7171f692d0fad37aad0674c6b7c904540a9a0c
      https://github.com/llvm/llvm-project/commit/1e7171f692d0fad37aad0674c6b7c904540a9a0c
  Author: David Green <david.green at arm.com>
  Date:   2024-12-03 (Tue, 03 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64] Add tablegen patterns for concat(extract-high, extract-high) (#118286)

A `concat(extract-high(x), extract-high(y))` is the top half of x
inserted into the bottom half of y. This patch adds a tablegen pattern
to make sure that we generate a single i64 lane insert.



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