[all-commits] [llvm/llvm-project] 56cb5c: [RISCV] Remove RISCVISD::VNSRL_VL and adjust deint...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56cb5cbfcdc09499d366046d6ea2ea6655fc11ef
      https://github.com/llvm/llvm-project/commit/56cb5cbfcdc09499d366046d6ea2ea6655fc11ef
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-12-02 (Mon, 02 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

  Log Message:
  -----------
  [RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match (#118391)

Instead of directly lowering to vnsrl_vl and having custom pattern
matching for that case, we can just lower to a (legal) shift and
truncate, and let generic pattern matching produce the vnsrl.

The major motivation for this is that I'm going to reuse this logic to
handle e.g. deinterleave4 w/ i8 result.

The test changes aren't particularly interesting. They're minor code
improvements - I think because we do slightly better with the
insert_subvector patterns, but that's mostly irrelevant.



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