[all-commits] [llvm/llvm-project] de6d0d: [RISCV][GISel] Add FCLASS to onlyUsesFP for regist...

[Luke Quinn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de6d0d2de0e2df72bd77f29d27addf13ebfbc997
      https://github.com/llvm/llvm-project/commit/de6d0d2de0e2df72bd77f29d27addf13ebfbc997
  Author: Luke Quinn <lquinn2015 at gmail.com>
  Date:   2024-12-02 (Mon, 02 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll

  Log Message:
  -----------
  [RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

Bug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS
has an input float register and output GPR this caused reg bank select
regression.



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