[all-commits] [llvm/llvm-project] c9fa31: [RISCV] Use LiveIntervals to determine if AVL domi...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9fa3195f0f012a5606ec3e403a1f111b3a4e0c7
      https://github.com/llvm/llvm-project/commit/c9fa3195f0f012a5606ec3e403a1f111b3a4e0c7
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-12-03 (Tue, 03 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll

  Log Message:
  -----------
  [RISCV] Use LiveIntervals to determine if AVL dominates when coalescing (#118285)

In order to coalesce a vsetvli with a register AVL into a previous
vsetvli, we need to make sure that the AVL register is reachable at the
previous vsetvli.

Back in pre-RA vsetvli insertion we just checked to see if the two
virtual registers were the same virtual register, and then this was
hacked around in the move to post-RA. We can instead use live intervals
to check that the reaching definition is the same at both instructions.

On its own this doesn't have much of an impact, but helps a lot in
#118283 and enables coalescing in about 60 of the test cases from that
PR.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications