[all-commits] [llvm/llvm-project] 43ee6f: [AlwaysInline] Avoid unnecessary BFI fetches (#117...
jeanPerier via All-commits
all-commits at lists.llvm.org
Mon Dec 2 02:03:04 PST 2024
Branch: refs/heads/users/jperier/opt_eval_in_mem
Home: https://github.com/llvm/llvm-project
Commit: 43ee6f7a01fca8cf08e1029c54acc23240b86fca
https://github.com/llvm/llvm-project/commit/43ee6f7a01fca8cf08e1029c54acc23240b86fca
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
Log Message:
-----------
[AlwaysInline] Avoid unnecessary BFI fetches (#117750)
AlwaysInliner doesn't use BFI itself, it only updates it. If BFI is not
already computed, it will spend time to first compute it, and then
update it. This is not necessary: If BFI is not available in the first
place, there is no need to update it.
This is mainly relevant in debug builds for IR that has a lot of
alwaysinline functions.
Commit: 8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
https://github.com/llvm/llvm-project/commit/8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
Log Message:
-----------
[OpenACC] enable 'deviceptr' for combined constructs.
This is another clause whose implementation is identical for combined
constructs as with compute constructs, so this adds tests and enables
it.
Commit: 198fb5ed4ac7d096da03ea4a0a27832d18b1350f
https://github.com/llvm/llvm-project/commit/198fb5ed4ac7d096da03ea4a0a27832d18b1350f
Author: Samira Bazuzi <bazuzi at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
Log Message:
-----------
[clang][dataflow] Add captured parameters to ReferencedDecls for lamb… (#117771)
…da call operators.
This doesn't require that they be used in the operator's body, unlike
other ReferencedDecls. This is most obviously different from captured
local variables, which can be captured but will not appear in
ReferencedDecls unless they appear in the operator's body.
This difference simplifies the collection of the captured parameters,
but probably could be eliminated if desirable.
Commit: f67ba5855278401728413431216dda5d370ac2e0
https://github.com/llvm/llvm-project/commit/f67ba5855278401728413431216dda5d370ac2e0
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
Log Message:
-----------
[Clang] replace 'bitfield' with 'bit-field' for consistency (#117881)
Fixes #117711
Commit: 38049dc8eef0dca7e82c25e4012228a9a135e255
https://github.com/llvm/llvm-project/commit/38049dc8eef0dca7e82c25e4012228a9a135e255
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
Log Message:
-----------
[libc] Handle differing wavefront sizes correctly in the AMDHSA loader (#117788)
Summary:
The AMDGPU backend can handle wavefront sizes of 32 and 64, with the
native hardware preferring one or the other. The user can override the
hardware with `-mwavefrontsize64` or `-mwavefrontsize32` which
previously wasn't handled. We need to know the wavefront size to know
how much memory to allocate and how to index the RPC buffer. There isn't
a good way to do this with ROCm so we just use the LLVM support for
offloading to check this from the image.
Commit: 32ff209b87a84890a1487b4e0bbb4a7645d31645
https://github.com/llvm/llvm-project/commit/32ff209b87a84890a1487b4e0bbb4a7645d31645
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Analysis/Consumed.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
Log Message:
-----------
[Clang] skip consumed analysis for consteval conditions in control-flow terminators (#117403)
Fixes #117385
---
These changes extend the work done in #116513. The changes add
additional handling to ensure correct behavior by skipping further
checks when a **CFG** contains a `consteval` condition, where no
_explicit expression_ is present, which is required to proceed with
consumed analyses.
Commit: e98396f4846bfcaabe2c2ee568aab4b78655f307
https://github.com/llvm/llvm-project/commit/e98396f4846bfcaabe2c2ee568aab4b78655f307
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
Reapply [memprof] Add YAML-based deserialization for MemProf profile (#117829)
This patch adds YAML-based deserialization for MemProf profile.
It's been painful to write tests for MemProf passes because we do not
have a text format for the MemProf profile. We would write a test
case in C++, run it for a binary MemProf profile, and then finally run
a test written in LLVM IR with the binary profile.
This patch paves the way toward YAML-based MemProf profile.
Specifically, it adds new class YAMLMemProfReader derived from
MemProfReader. For now, it only adds a function to parse StringRef
pointing to YAML data. Subseqeunt patches will wire it to
llvm-profdata and read from a file.
The field names are based on various printYAML functions in MemProf.h.
I'm not aiming for compatibility with the format used in printYAML,
but I don't see a point in changing the field names.
This iteration works around the unavailability of
ScalarTraits<uintptr_t> on macOS.
Commit: 611f5b8ff913c21cfd85b0f4170ab880838a4c9e
https://github.com/llvm/llvm-project/commit/611f5b8ff913c21cfd85b0f4170ab880838a4c9e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/test/Transforms/GVN/setjmp.ll
Log Message:
-----------
[GVN] Add test for #116668 (NFC)
Commit: d668304998344d40c5a0b512fd0c0cb91e8d534c
https://github.com/llvm/llvm-project/commit/d668304998344d40c5a0b512fd0c0cb91e8d534c
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
Log Message:
-----------
[lld][MachO] Support `-allowable_client` (#117155)
Closes #117113.
Follow-up to #114638.
Commit: 969b7658fe34cf7638e1385d813e765a4c61dfc7
https://github.com/llvm/llvm-project/commit/969b7658fe34cf7638e1385d813e765a4c61dfc7
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
Log Message:
-----------
[OpenACC] Enable 'wait' for combined constructs
Once again a situation where the combined and compute do the exact same
thing as far as Sema/AST/etc is concerned, so this patch adds tests and
enables it.
Commit: 24593f1814dc02c7404526674838ccfb1c61d780
https://github.com/llvm/llvm-project/commit/24593f1814dc02c7404526674838ccfb1c61d780
Author: Saleem Abdulrasool <compnerd at compnerd.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
Log Message:
-----------
[lldb] build: cleanup extraneous include paths (#117615)
Clean up some unnecessary include paths. The use of `LibXml2::LibXml2`
with `target_link_libraries` on `libLLDBHost` ensures that the header
search path is properly propagated.
Commit: 8358437bbb5b06d9aebc2940475a5a4d86c091c9
https://github.com/llvm/llvm-project/commit/8358437bbb5b06d9aebc2940475a5a4d86c091c9
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl]: Print stack-trace on crash (#117896)
Call `llvm::sys::PrintStackTraceOnErrorSignal` at the start of main to
1. Print a strack trace on crash
2. Disable the assertion failed popup in Windows Debug Builds
Other tools (for example clang-check or clang-query) already do this.
This fixes debug build bots on windows hanging (waiting for the popup to
be dismissed) and ultimately getting terminated due to timeout.
Commit: b71704436e61057a5bd6426915c368e5d76cb7de
https://github.com/llvm/llvm-project/commit/b71704436e61057a5bd6426915c368e5d76cb7de
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Simplify generated code for validateOperandClass (#117889)
Implement the register operand handling in validateOperandClass with a
table lookup instead of a potentially huge switch.
Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
Commit: 2f02b5af6ecb973d3a7faad9b0daff22646e724d
https://github.com/llvm/llvm-project/commit/2f02b5af6ecb973d3a7faad9b0daff22646e724d
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy][modernize-use-starts-ends-with] Fix operator rewriting false negative (#117837)
In C++20, `operator!=` can be rewritten by negating `operator==`. This
is the case for `std::string`, where `operator!=` is not provided hence
relying on this rewriting.
Cover this case by matching `binaryOperation` and adding one case to
`isNegativeComparison`.
Commit: 1e3e199ed9f214594e358eb0c7892cdedc703f7a
https://github.com/llvm/llvm-project/commit/1e3e199ed9f214594e358eb0c7892cdedc703f7a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[Sema] Migrate away from PointerUnion::{is,get} (NFC) (#117498)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: c29e895ad2bce8ca36debd8ef09d0540dabc99b6
https://github.com/llvm/llvm-project/commit/c29e895ad2bce8ca36debd8ef09d0540dabc99b6
Author: knickish <knickish at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
Log Message:
-----------
[M68k] Handle 16 bit MOVs to and from CCR (#114714)
Builds on @TechnoElf 's CCR MOV pr
https://github.com/llvm/llvm-project/pull/107591 and adds some tests.
Fixes https://github.com/llvm/llvm-project/issues/106210.
---------
Co-authored-by: TechnoElf <technoelf at undertheprinter.com>
Commit: 991154d0fbc951e2b999589a95dabc7deff7acd1
https://github.com/llvm/llvm-project/commit/991154d0fbc951e2b999589a95dabc7deff7acd1
Author: Krzysztof Pszeniczny <kpszeniczny at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionImport.cpp
Log Message:
-----------
[LTO] Use .at instead of .lookup to avoid copies. (NFC) (#117888)
`DenseMap::lookup` returns by value (because it default-creates the
returned value if the key isn't present in the map), which means that we
do a lot of copying here. Since we assert that something is present in
the returned value two lines below this call, it's safe to use `.at`
here instead.
Copying and then destroying dense maps here is responsible for 60% of
the time spent in LTO indexing in a large internal build.
Commit: b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
https://github.com/llvm/llvm-project/commit/b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/test/Sema/builtin-counted-by-ref.c
Log Message:
-----------
[Clang] Improve Sema diagnostic performance for __builtin_counted_by_ref (#116719)
Implement the sema checks with a placeholder. We then check for that
placeholder in all of the places we care to emit a diagnostic.
Fixes: #115520
Commit: a4751804985554815899b5dc1544e27139bacdc4
https://github.com/llvm/llvm-project/commit/a4751804985554815899b5dc1544e27139bacdc4
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
Log Message:
-----------
[PowerPC] Use setbc for values from vector compare conditions (#114858)
For P10 use the setbc instruction to get int values from vector compare
summary condition results.
Commit: 9d55e862d938c17a5e3f970326139c53b9aaf37e
https://github.com/llvm/llvm-project/commit/9d55e862d938c17a5e3f970326139c53b9aaf37e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Fix warnings on MSVC
MSVC doesn't seem to count a use in static_assert as a use.
Commit: 35a5c7129a32f7eedf2d1913447c53cee96eab13
https://github.com/llvm/llvm-project/commit/35a5c7129a32f7eedf2d1913447c53cee96eab13
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
Log Message:
-----------
[OpenACC] Add tests forgotten in 969b7658fe
Commit: bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
https://github.com/llvm/llvm-project/commit/bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
Log Message:
-----------
[OpenACC] Enable 'attach' clause for combined constructs
Once again, this clause has the same implementation for compute
constructs as combined, so this adds the tests and enables it.
Commit: 87503fa51c8d726510d48e707a7d2885a5b5936c
https://github.com/llvm/llvm-project/commit/87503fa51c8d726510d48e707a7d2885a5b5936c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
Log Message:
-----------
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
This reverts commit e9c49901a43f5b16c3df416460b7e4dbdd24ce03.
Current AMDGPURegBankSelect does nothing different then RegBankSelect.
Revert to using generic RegBankSelect in preparation for adding new
regbankselect passes. New AMDGPURegBankSelect, that will use uniformity
analysis for regbank select decisions, will not subclass RegBankSelect.
Revert regression tests to use regbankselect since amdgpu-regbankselect
will be used by new pass and behavior will be different.
Commit: 2e9469885d4572a2eedf2669190742c9e3272e6a
https://github.com/llvm/llvm-project/commit/2e9469885d4572a2eedf2669190742c9e3272e6a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 87503fa51c8d
Commit: dae9cf3816bbb2b4589d258a82e6ac90fad71485
https://github.com/llvm/llvm-project/commit/dae9cf3816bbb2b4589d258a82e6ac90fad71485
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
Log Message:
-----------
[RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC
Improves coverage for more configurations.
Commit: d7643e86100a3515660dc807c88eea79bf755016
https://github.com/llvm/llvm-project/commit/d7643e86100a3515660dc807c88eea79bf755016
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support f32/f64 llvm.exp10 intrinsics.
Commit: 1bc9de247477b58a14547a31047d1c9a365e2d5d
https://github.com/llvm/llvm-project/commit/1bc9de247477b58a14547a31047d1c9a365e2d5d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
Commit: 92a15dd7482ff4e1fae7a07f888564e5b1d53eee
https://github.com/llvm/llvm-project/commit/92a15dd7482ff4e1fae7a07f888564e5b1d53eee
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][LLVM] Plumb range attributes on parameters and results through (#117801)
We've had the ability to define LLVM's `range` attribute through
#llvm.constant_range for some time, and have used this for some GPU
intrinsics. This commit allows using `llvm.range` as a parameter or
result attribute on function declarations and definitions.
Commit: 3ce8b7d2205507c91f1609337382ad950f3be805
https://github.com/llvm/llvm-project/commit/3ce8b7d2205507c91f1609337382ad950f3be805
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove inline call stacks (#117833)
Now that MemProf format version 1 has been removed, nobody uses:
- IndexedAllocationInfo::CallStack
- IndexedMemProfRecord::CallSites
This patch removed the dead struct fields.
You might notice that IndexedMemProfRecord::{clear,merge} do not
mention CallSiteIds at all. I think it's an oversight. clear doesn't
matter at the moment because we call it during serialization to reduce
memory footprint. merge is simply not as well tested as it should be.
I'll follow up with a separate patch to address these issues.
Commit: 82b437944e53afeb25dd85507664e2a980ddfe07
https://github.com/llvm/llvm-project/commit/82b437944e53afeb25dd85507664e2a980ddfe07
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use "using" directives in unit tests (NFC) (#117852)
This tests uses existing "using" directives to shorten unit tests.
- llvm::memprof::hashCallStack -> hashCallStack
- testing::Pair -> Pair
- testing::ElementsAreArray -> ElementsAre
- testing::Contains -> UnorderedElementsAre
Commit: 06246b2952d5b061e8fd75979bac9c90ccd493a4
https://github.com/llvm/llvm-project/commit/06246b2952d5b061e8fd75979bac9c90ccd493a4
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
Log Message:
-----------
[RISCV] Add shrinkwrap test cases showing gaps in current impl
This covers multiple interactions reduced from larger workloads:
1) Rematerializing addi s0, x0, <imm> to avoid the need to spill a CSR, with
the common user being a branch. (i.e. branch on immediate idioms)
2) Rematerializing addi s0, a0, <imm> to avoid the need to spill a CSR, with
the common user being a vector load or store. (i.e. because we don't
have (reg+imm) addressing on vector.)
3) Independent of the previous, we could still shrink wrap these by locally
using a non-CSR, and deferring the move into csr into the non-shrink
wrapped path.
4) Weirdly, MachineCSE is producing a different result when an edge is
manually split. This edge split should be irrelevant to the CSE?
Commit: c60b055d463a3e9f18a494aec075f35d38d447a0
https://github.com/llvm/llvm-project/commit/c60b055d463a3e9f18a494aec075f35d38d447a0
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
Log Message:
-----------
Reapply "Respect the [[clang::unsafe_buffer_usage]] attribute for field and constructor initializers (#91991)"
It was originally reverted due to an [existing bug](https://github.com/llvm/llvm-project/issues/116286). Relanding it as the bug was fixed by https://github.com/llvm/llvm-project/pull/116433.
Commit: d681e1030ffd71412294d3fadc7ef673f822b832
https://github.com/llvm/llvm-project/commit/d681e1030ffd71412294d3fadc7ef673f822b832
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/latch
M libcxx/include/semaphore
Log Message:
-----------
[libc++] Refactor atomic_wait using lambdas (#115746)
Now that we've dropped support for older C++ dialects in the
synchronization library, we can use lambdas to clarify some of the code
used to implement atomic_wait.
Commit: 8c1bd9792be1d7d19eebce57be556d5cadeb2d15
https://github.com/llvm/llvm-project/commit/8c1bd9792be1d7d19eebce57be556d5cadeb2d15
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-clause.c
A clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
Log Message:
-----------
[OpenACC] Expose 'no_create' clause in combined constructs
Once again, not much work besides ensuring they are supposed to work the
same.
Commit: b6ab04c69c907362dc7ab65eb43a9907c9adcdc1
https://github.com/llvm/llvm-project/commit/b6ab04c69c907362dc7ab65eb43a9907c9adcdc1
Author: Clément Fournier <clem.fournier at proton.me>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Matchers.h
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Fix arith maxnumf/minnumf folder (#114595)
Fix #114594
#### Context
[IEEE754-2019](https://ieeexplore.ieee.org/document/8766229) Sec 9.6
defines 2 minimum and 2 maximum operations. They are termed
- `maximum` and `maximumNumber`
- `minimum` and `minimumNumber`
In the arith dialect they are respectively named `maximumf` and
`maxnumf`, `minimumf` and `minnumf` so I use these names.
These operations only differ in how they handle NaN values. For
`maximumf` and `minimumf`, if any operand is NaN, then the result is
NaN, ie, NaN is propagated. For `maxnumf` and `minnumf`, if any operand
is NaN, then the other operand is returned, ie, NaN is absorbed. The
following identities hold:
```
maximumf(x, NaN) = maximumf(NaN, x) = NaN
maxnumf(x, NaN) = maxnumf(NaN, x) = x
```
(and same for min).
#### Arith folders
In the following I am talking about the folders for the arith
operations. The folders implement the following canonicalizations (`op`
is one of maximumf, maxnumf, minimumf, minnumf):
1. `op(x, x)` folds to `x`
2. for `op(x, y)`, if `y` folds to the neutral element of the `op`, then
the `op` is folded to `x`.
1. The neutral element of `maximumf` is -Infty
2. The neutral element of `minimumf` is +Infty
3. The neutral element of `maxnumf` and `minnumf` is NaN as shown above.
3. for `op(x, y)`, if both `x` and `y` fold to constants `x'` and `y'`,
then the `op` is folded and the result is calculated with a
corresponding runtime function.
The folders are properly implemented for `maximumf` and `minimumf`, but
the same implementations were copied for the respective `maxnumf` and
`minnumf` functions. This means the neutral element of the second folder
above is wrong:
- `maxnumf(x, -Infty)` is folded to `x`, but that's wrong, because if
`x` is NaN then -Infty should be the result
- `minnumf(x, +Infty)` is folded to `x`, but same thing, the result
should be +Infty when `x` is NaN.
This is fixed by using `NaN` as neutral element for the `maxnumf` and
`minnumf` ops.[^1]
Again because of copy paste mistake, the third pattern above is using
`llvm::maximum` instead of `llvm::maximumnum` to calculate the result in
case both arguments fold to a constant:
- `maxnumf(NaN, x')` would have been folded to `llvm::maximum(NaN, x')`
which is `NaN`, whereas the result should be `x'`.
This folder for `minnumf` already correctly uses `llvm::minnum`, but I
fixed the one for `maxnumf` in this PR.
[^1]: this is by the way already correctly implemented in
[`arith::getIdentityValueAttr`](https://github.com/oowekyala/llvm-project/blob/a821964e0320d1e35514ced149ec10ec06d7131a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp#L2493-L2498)
Commit: 854d7301f989dd1e3c838ef4f48cb57bb7d496e0
https://github.com/llvm/llvm-project/commit/854d7301f989dd1e3c838ef4f48cb57bb7d496e0
Author: Vigneshwar Jayakumar <vigneshwarjayakumar at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
A clang/test/SemaHIP/zero-sized-device-array.hip
Log Message:
-----------
[Clang/AMDGPU] Zero sized arrays not allowed in HIP device code. (#113470)
Added diagnosis to throw error when zero sized arrays are used in the
HIP device code. SWDEV-449592
---------
Co-authored-by: vigneshwar jayakumar <vigneshwar.jayakumar at amd.com>
Commit: 175051b05edcd10d997d8f98f142af1ff191b93a
https://github.com/llvm/llvm-project/commit/175051b05edcd10d997d8f98f142af1ff191b93a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support libcalls for f32/f64 acos/asin/atan/atan2/cosh/sinh/tanh.
Commit: 89d8e70031189eacb915beae2ffc642c0de1ec1a
https://github.com/llvm/llvm-project/commit/89d8e70031189eacb915beae2ffc642c0de1ec1a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/src/__support/RPC/rpc_client.cpp
M libc/src/__support/RPC/rpc_client.h
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Export a pointer to the RPC client directly (#117913)
Summary:
We currently have an unnecessary level of indirection when initializing
the RPC client. This is a holdover from when the RPC client was not
trivially copyable and simply makes it more complicated. Here we use the
`asm` syntax to give the C++ variable a valid name so that we can just
copy to it directly.
Another advantage to this, is that if users want to piggy-back on the
same RPC interface they need only declare theirs as extern with the same
symbol name, or make it weak to optionally use it if LIBC isn't
avaialb.e
Commit: 1d810ece2b2c8fab77720493864257f0ea3336a9
https://github.com/llvm/llvm-project/commit/1d810ece2b2c8fab77720493864257f0ea3336a9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/shared/rpc_opcodes.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
R libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Move libc server handlers to a shared header (#117908)
Summary:
We can simply include this header from the shared directory now and do
not need to have this level of indirection. Simply stash it with the
other libc opcode handlers.
If we were able to move the printf handlers to the shared directory then
this could just be a header as well, which would HEAVILY simplify the
mess associated with building the RPC server first in the projects
build, then copying it to the runtimes build.
Commit: 1669ac434cd4aa0ad47d42401c6d4e2afd826d30
https://github.com/llvm/llvm-project/commit/1669ac434cd4aa0ad47d42401c6d4e2afd826d30
Author: lialan <me at alanli.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
Log Message:
-----------
[MLIR] Refactor mask compression logic when emulating `vector.maskedload` ops (#116520)
This patch simplifies and extends the logic used when compressing masks
emitted by `vector.constant_mask` to support extracting 1-D vectors from
multi-dimensional vector loads. It streamlines mask computation, making
it applicable for multi-dimensional mask generation, improving the
overall handling of masked load operations.
Commit: febbf9105f7101d7124e802e87d8303237b64a80
https://github.com/llvm/llvm-project/commit/febbf9105f7101d7124e802e87d8303237b64a80
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Match vcompress during shuffle lowering (#117748)
This change matches a subset of vcompress patterns during shuffle
lowering. The subset implemented requires a contiguous prefix of
demanded elements followed by undefs. This subset was chosen for two
reasons: 1) which elements to spurious demand is a non-obvious problem,
and 2) my first several attempts at implementing the general case were
buggy. I decided to go with the simple case to start with.
vcompress scales better with LMUL than a general vrgather, and at least
the SpaceMit X60, has higher throughput even at m1. It also has the
advantage of requiring smaller vector constants at one bit per element
as opposed to vrgather which is a minimum of 8 bits per element. The
downside to using vcompress is that we can't fold a vselect into it, as
there is no masked vcompress variant.
For reference, here are the relevant throughputs from camel-cdr's data
table on BP3 (X60):
vrgather.vv v8,v16,v24 4.0 16.0 64.0 256.0
vcompress.vm v8,v16,v24 3.0 10.0 36.0 136.
vmerge.vvm v8,v16,v24,v0 2.0 4.0 8.0 16.0
The largest concern with the extra vmerge is that we locally increase
register pressure. If we do have masking, we also have a passthru,
without the ability to fold that into the vcompress, we need to keep it
alive a bit longer. This can hurt at e.g. m8 where we have very few
architectural registers. As compared with the vrgather.vv sequence, this
is only one additional m1 VREG - since we no longer need the index
vector. It compares slightly worse against vrgatherie16.vv which can use
index vectors smaller than other operands. Note that we could
potentially fold the vmerge if only tail elements are being preserved; I
haven't investigated this.
It is unfortunately hard given our current lowering structure to know if
we're emitting a shuffle where masking will follow. Thankfully, it
doesn't seem to show up much in practice, so I think we can probably
ignore it.
This patch only handles single source compress idioms at the moment.
This is an effort to avoid interacting with other patches on review for
changing how we canonicalize length changing shuffles.
Commit: e3fdc3aa81c7e8196d804fbde1a3f76796dbd5dd
https://github.com/llvm/llvm-project/commit/e3fdc3aa81c7e8196d804fbde1a3f76796dbd5dd
Author: Felipe Magno de Almeida <felipe.m.almeida at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Log Message:
-----------
[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044)
Change the intersect for the anticipated algorithm to ignore unknown
when anticipating. This effectively allows VXRM writes speculatively
because it could do a VXRM write even when there's branches where VXRM
is unneeded.
The importance of this change is because VXRM writes causes pipeline
flushes in some micro-architectures and so it makes sense to allow more
aggressive hoisting even if it causes some degradation for the slow
path.
An example is this code:
```
typedef unsigned char uint8_t;
__attribute__ ((noipa))
void foo (uint8_t *dst, int i_dst_stride,
uint8_t *src1, int i_src1_stride,
uint8_t *src2, int i_src2_stride,
int i_width, int i_height )
{
for( int y = 0; y < i_height; y++ )
{
for( int x = 0; x < i_width; x++ )
dst[x] = ( src1[x] + src2[x] + 1 ) >> 1;
dst += i_dst_stride;
src1 += i_src1_stride;
src2 += i_src2_stride;
}
}
```
With this patch, the code above generates a hoisting VXRM writes out of
the outer loop.
Commit: c6f2d35c4d698deff781366cea46e273ff508693
https://github.com/llvm/llvm-project/commit/c6f2d35c4d698deff781366cea46e273ff508693
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
Fix a build warning introduce by my febbf910
Commit: 4cb4516ae9ae2f267ec755ed0ec6b671fe6747b8
https://github.com/llvm/llvm-project/commit/4cb4516ae9ae2f267ec755ed0ec6b671fe6747b8
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
Log Message:
-----------
[OpenMP] Fix RPC client not being optimized out after changes
Summary:
I forgot that this check deliberately looked through the indirection I
removed. Fix it to just check if the symbol has no users.
Commit: 80afdbe6a55a10cb246cb748149f0d41e778d01b
https://github.com/llvm/llvm-project/commit/80afdbe6a55a10cb246cb748149f0d41e778d01b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Use RISCVSubtarget::is64Bit() instead of hasFeature(RISCV::Feature64Bit). NFC
Commit: 8df63211a65693c7cc760e361adf20edd450fafa
https://github.com/llvm/llvm-project/commit/8df63211a65693c7cc760e361adf20edd450fafa
Author: Pranav Kant <prka at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Bitstream/Reader/BitstreamReader.cpp
Log Message:
-----------
[BitstreamReader] Fix 32-bit overflow (#117363)
This got exposed when processing large LTO-generated files leading to
crashes.
Commit: 21af99ab84e434819b20452367325b187492d372
https://github.com/llvm/llvm-project/commit/21af99ab84e434819b20452367325b187492d372
Author: Maurice Heumann <MauriceHeumann at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86WinEHState.cpp
A llvm/test/CodeGen/WinEH/wineh-scope-statenumbering.ll
Log Message:
-----------
[WinEH] Emit state stores for SEH scopes (#116546)
At the moment Windows 32 bit SEH state stores are only emitted for
throwing calls.
Windows 32 bit SEH state stores should also be emitted before SEH scope
begin and before SEH scope end.
An invalid inline memory access would otherwise not trigger unwinding,
in combination with /EHa.
This fixes #90946
Commit: e573c6b67eb729a625431121139100bebc61ba1f
https://github.com/llvm/llvm-project/commit/e573c6b67eb729a625431121139100bebc61ba1f
Author: Yusuke MINATO <minato.yusuke at fujitsu.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/HLFIR/goto-do-body.f90
M flang/test/Lower/goto-do-body.f90
M flang/test/Lower/nsw.f90
Log Message:
-----------
[flang] Add nsw to DO loop parameters (#113854)
nsw is added to DO loop parameters (initial parameters, terminal
parameters, and incrementation parameters).
This can help vectorization in some cases like #110609.
See also the discussion in
https://discourse.llvm.org/t/rfc-add-nsw-flags-to-arithmetic-integer-operations-using-the-option-fno-wrapv/77584/20.
Commit: 9bdf683ba6cd9ad07667513d264a2bc02d969186
https://github.com/llvm/llvm-project/commit/9bdf683ba6cd9ad07667513d264a2bc02d969186
Author: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/extract-vselect-setcc.ll
Log Message:
-----------
[X86] Enforce strict pre-legalization to combine in scalarizeExtEltFP (#117681)
Use a `DCI` object to actually check the DAG combine level instead of
using the type `i1` because this assumption fails on AVX512 where we
have types like `v8i1` after legalization.
Closes #117684
Commit: 65339e4d74923711c1bf6babfd59fd46f74647ba
https://github.com/llvm/llvm-project/commit/65339e4d74923711c1bf6babfd59fd46f74647ba
Author: Stella Laurenzo <stellaraccident at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
Log Message:
-----------
[mlir] Add option to disable MLIR Python dev package configuration. (#117934)
Adds a CMake option MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES which
gates doing package discovery and configuration for Python dev packages
by MLIR (this was made opt-out to preserve compatibility with
find_package(MLIR) based uses which do not set the standard options).
The default Python setup that MLIR does has been a problem for
super-projects that include LLVM for a long time because it forces a
very specific package discovery mechanism that is not uniform in all
uses.
When reviewing #117922, I noted that this would effectively be a break
the world event for downstreams, forcing them to adapt their nanobind
dep to the exact way that MLIR does it. Adding the option to just
wholesale skip the built-in configuration heuristics at least gives us a
mechanism to tell downstreams to migrate to, giving them complete
control and not requiring packaging workarounds. This seemed a better
option than (once again) creating a situation where downstreams could
not integrate the dep change without doing tricky infra upgrades, and it
removes the burden from the author of that patch from needing to think
about how this affects super-projects that include MLIR (i.e. they can
just be told to do it themselves as needed vs being in a wedged state
and unable to upgrade).
Commit: d2b482b0efd1d523852c9add8ed6b2035ce1acd9
https://github.com/llvm/llvm-project/commit/d2b482b0efd1d523852c9add8ed6b2035ce1acd9
Author: Omar Hossam <moar.ahmed at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] (reland #117503) Implement process_mrelease (#117851)
This PR implements process_mrelease.
A previous PR was merged #117503, but failed on merge due to an issue in
the tests. Namely the failing tests were comparing against return type
as opposed to errno. This is fixed in this PR.
Commit: 63c5a422f07da9925a4700f54016ab8623567718
https://github.com/llvm/llvm-project/commit/63c5a422f07da9925a4700f54016ab8623567718
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/DeclCXX.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/SemaCXX/literal-type.cpp
Log Message:
-----------
[Clang] Fix constexpr-ness on implicitly deleted destructors (#116359)
In C++20, a defaulted but implicitly deleted destructor is constexpr if
and only if the class has no virtual base class. This hasn't been
changed in C++23 by P2448R2.
Constexpr-ness on a deleted destructor affects almost nothing. The
`__is_literal` intrinsic is related, while the corresponding
`std::is_literal_type(_v)` utility has been removed in C++20. A recently
added example in `test/AST/ByteCode/cxx23.cpp` will become valid, and
the example is already accepted by GCC.
Clang currently behaves correctly in C++23 mode, because the
constexpr-ness on defaulted destructor is relaxed by P2448R2. But we
should make similar relaxation for an implicitly deleted destructor.
Fixes #85550.
Commit: c8cd497c9889b051671c7fe2eb6e4b3bbe6606f9
https://github.com/llvm/llvm-project/commit/c8cd497c9889b051671c7fe2eb6e4b3bbe6606f9
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/UsersManual.rst
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[Driver] Support fprofile-sample-use= for CL (#117282)
Sampling PGO has already been supported on Windows. This patch adds
/fprofile-sample-use= /fprofile-sample-use: /fno-profile-sample-use and
supports -fprofile-sample-use= for CL.
Commit: 819b155c2a18460d2f22482975d33d77bb4f8831
https://github.com/llvm/llvm-project/commit/819b155c2a18460d2f22482975d33d77bb4f8831
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/src/sys/mman/linux/process_mrelease.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] skip test and return ENOSYS when processm_release unavailable (#117951)
Commit: 4a3f46de5022418452947bb630cdb5b9658e82ea
https://github.com/llvm/llvm-project/commit/4a3f46de5022418452947bb630cdb5b9658e82ea
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
Log Message:
-----------
[LV][EVL] Support call instruction with EVL-vectorization (#110412)
Commit: a24aa7dfa579c41365f23f8205b619b838e32184
https://github.com/llvm/llvm-project/commit/a24aa7dfa579c41365f23f8205b619b838e32184
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/plugins-nextgen/common/CMakeLists.txt
M runtimes/cmake/Modules/FindLibcCommonUtils.cmake
Log Message:
-----------
[Offload] Use libc 'hand-in-hand' module to find RPC header (#117928)
Summary:
We should now use the official™ way to include the files from
`libc/shared`. This required some code to make sure that it's not
included twice if multiple people use it as well as a sanity check on
the directory.
Commit: 054f914741421ca9dd1eaa58ea74a20f8695bae6
https://github.com/llvm/llvm-project/commit/054f914741421ca9dd1eaa58ea74a20f8695bae6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/utils/merge-json.py
M runtimes/CMakeLists.txt
Log Message:
-----------
[Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)
Summary:
When building a project in a runtime mode, the compilation database is a
separate CMake invocation. So its `compile_commands.json` file will be
placed elsewhere in the `runtimes/runtime-bins` directory. This is
somewhat annoying for ongoing development when a runtimes build is
necessary. This patch adds some CMake magic to merge the two files.
Commit: 700d9ac9ef82fa5aa6b2972e8656ab5055a90d15
https://github.com/llvm/llvm-project/commit/700d9ac9ef82fa5aa6b2972e8656ab5055a90d15
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
Log Message:
-----------
[libc] disable process_mrelease for riscv (#117956)
`process_mrelease` upsets the RV32 build bot. Disable it for now.
Commit: 1f422dc399e2b62d0c8fc64849af915d89c28d67
https://github.com/llvm/llvm-project/commit/1f422dc399e2b62d0c8fc64849af915d89c28d67
Author: sfzhu93 <42506672+sfzhu93 at users.noreply.github.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
Log Message:
-----------
[MLIR][mlir-opt] add support for disabling diagnostics (#117669)
This PR adds a command line argument `--mlir-disable-diagnostic` for
disabling diagnostic information for mlir-opt.
When debugging with mlir-opt, some developers would like to disable the
diagnostic information and focus specifically on the dumped IR. For
example, https://github.com/triton-lang/triton/pull/5250
Commit: db273c6c242f51792ed4298a24bd2c344214ce38
https://github.com/llvm/llvm-project/commit/db273c6c242f51792ed4298a24bd2c344214ce38
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/tools/mlir-tblgen/EnumsGen.cpp
Log Message:
-----------
[MLIR][ODS] Add support for wrapping enums with std::optional in Type/Attr definitions (#117719)
Commit: c8b15157d70c57489b9aba939065c01c3f697ddb
https://github.com/llvm/llvm-project/commit/c8b15157d70c57489b9aba939065c01c3f697ddb
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
Log Message:
-----------
[mlir-opt] Fix -Wcovered-switch-default in MlirOptMain.cpp (NFC)
/llvm-project/mlir/lib/Tools/mlir-opt/MlirOptMain.cpp:262:7:
error: default label in switch which covers all enumeration values [-Werror,-Wcovered-switch-default]
default:
^
1 error generated.
Commit: 3a115279f888b6489902df60c3fe2e76447d375c
https://github.com/llvm/llvm-project/commit/3a115279f888b6489902df60c3fe2e76447d375c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Transforms/DialectConversion.h
Log Message:
-----------
[mlir][Transforms][NFC] Dialect conversion: Improve docs for materializations (#117847)
The terms "legal type" and "illegal type" are ambiguous when talking
about materializations. E.g., for target materializations we do not
necessarily convert from illegal to legal types. We convert from the
most recently mapped value to the type that was produced by converting
the original type.
---------
Co-authored-by: Markus Böck <markus.boeck02 at gmail.com>
Commit: 81f544d4659a96772c7e2ffed1bbe557993f4b34
https://github.com/llvm/llvm-project/commit/81f544d4659a96772c7e2ffed1bbe557993f4b34
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A flang/include/flang/Common/OpenMP-utils.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/lib/Common/CMakeLists.txt
A flang/lib/Common/OpenMP-utils.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
A flang/test/Lower/OpenMP/generic-loop-rewriting.f90
A flang/test/Transforms/generic-loop-rewriting-todo.mlir
A flang/test/Transforms/generic-loop-rewriting.mlir
Log Message:
-----------
[flang][OpenMP] Rewrite `omp.loop` to semantically equivalent ops (#115443)
Introduces a new conversion pass that rewrites `omp.loop` ops to their
semantically equivalent op nests bases on the surrounding/binding
context of the `loop` op. Not all forms of `omp.loop` are supported yet.
See `isLoopConversionSupported` for more info on which forms are
supported.
Commit: 2918a47f421b3d41eb54dbd8751c6e8df2adbe23
https://github.com/llvm/llvm-project/commit/2918a47f421b3d41eb54dbd8751c6e8df2adbe23
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[mlir][OpenMP] Annotate `private` vars with `map_idx` when needed (#116770)
This PR extends the MLIR representation for `omp.target` ops by adding a
`map_idx` to `private` vars. This annotation stores the index of the map
info operand corresponding to the private var. If the variable does not
have a map operand, the `map_idx` attribute is either not present at all
or its value is `-1`.
This makes matching the private variable to its map info op easier (see
https://github.com/llvm/llvm-project/pull/116576 for usage).
Commit: f710b042336d93fd1080124d3ec889702b77a730
https://github.com/llvm/llvm-project/commit/f710b042336d93fd1080124d3ec889702b77a730
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Fail early in ExecutionSession::registerJITDispatchHandlers.
Check that we're not reusing any handler tag addresses before installing any
handlers. This ensures that either all of the handlers are installed*, or none
of them are, simplifying error recovery.
* Ignoring handlers whose tags couldn't be resolved at all: these were never
installed.
Commit: fb3765959f2fcb97fbb2a247b619150926f0e0b6
https://github.com/llvm/llvm-project/commit/fb3765959f2fcb97fbb2a247b619150926f0e0b6
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
A llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
Log Message:
-----------
[llvm-debuginfo-analyzer] Common handling of unsigned attribute values. (#116027)
- In the DWARF reader, for those attributes that can have an unsigned
value, allow for the following cases:
* Is an implicit constant
* Is an optional value
- The testing is done by creating a file with generated DWARF, using
`DwarfGenerator` (generate DWARF debug info for unit tests).
Commit: 1c7695846559c2b191463aec46beb26c4a5c2bae
https://github.com/llvm/llvm-project/commit/1c7695846559c2b191463aec46beb26c4a5c2bae
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
Log Message:
-----------
[NVPTX] Add unreachable for TMA Inst Printer (#117850)
This patch adds the llvm_reachable() for TMA
reduction opcode printer method, outside the
switch.
We had this inside the default-case leading to
the warning below (and hence was removed):
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f3cf24fcc46ab1b9612d7dcb55ec5f18ea2dc62f
https://github.com/llvm/llvm-project/commit/f3cf24fcc46ab1b9612d7dcb55ec5f18ea2dc62f
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/arrayset.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/box-offset-codegen.fir
M flang/test/Fir/box.fir
M flang/test/Fir/boxproc.fir
M flang/test/Fir/commute.fir
M flang/test/Fir/coordinateof.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/field-index.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/struct-passing-x86-64-byval.fir
M flang/test/Fir/target-rewrite-complex-10-x86.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Transforms/constant-argument-globalisation.fir
A flang/test/Transforms/function-attrs.fir
Log Message:
-----------
[flang] Apply nocapture attribute to dummy arguments (#116182)
Apply llvm.nocapture attribute to dummy arguments that do not have the
target, asynchronous, volatile, or pointer attributes in a procedure
that is not a bind(c). This was discussed in
https://discourse.llvm.org/t/applying-the-nocapture-attribute-to-reference-passed-arguments-in-fortran-subroutines/81401
Commit: d36a4c07156de01b05ea41d5876c671de64e99c6
https://github.com/llvm/llvm-project/commit/d36a4c07156de01b05ea41d5876c671de64e99c6
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll
Log Message:
-----------
[RISCV] Rename some Feature* to Tune* (#117966)
These features should be tune features.
Commit: 9ea5be639d31560faec993b4aebb3e10c7d4c8e2
https://github.com/llvm/llvm-project/commit/9ea5be639d31560faec993b4aebb3e10c7d4c8e2
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
Log Message:
-----------
Recommit "[LV][VPlan] Remove any-of reduction from precomputeCost. NFC (#117109)" (#117289)
Update the test cases contains `any-of` printings from the
precomputeCost().
Origin message:
The any-of reduction contains phi and select instructions.
The select instruction might be optimized and removed in the vplan which
may cause VF difference between legacy and VPlan-based model. But if the
select instruction be removed, planContainsAdditionalSimplifications()
will catch it and disable the assertion.
Therefore, we can just remove the ayn-of reduction calculation in the
precomputeCost().
Recommit "[LV][VPlan] Remove any-of reduction from precomputeCost. NFC
(#117109)"
Commit: c4645ffedacad18e4cd1dd372288aa55178b1c44
https://github.com/llvm/llvm-project/commit/c4645ffedacad18e4cd1dd372288aa55178b1c44
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcicsr-invalid.s
A llvm/test/MC/RISCV/xqcicsr-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: 93f7398bdba9d1547df21156db4d5393f0ab5ec8
https://github.com/llvm/llvm-project/commit/93f7398bdba9d1547df21156db4d5393f0ab5ec8
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
Log Message:
-----------
[RISCV] Add TuneDisableLatencySchedHeuristic
This tune feature will disable latency scheduling heuristic.
This can reduce the number of spills/reloads but will cause some
regressions on some cores.
CPU may add this tune feature if they find it's profitable.
Reviewers: lukel97, michaelmaitland, asb, preames, mshockwave, topperc
Reviewed By: michaelmaitland, mshockwave, topperc
Pull Request: https://github.com/llvm/llvm-project/pull/115858
Commit: c1dff7152592f1beee9059ee8e2cb3cc68baea4d
https://github.com/llvm/llvm-project/commit/c1dff7152592f1beee9059ee8e2cb3cc68baea4d
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Host/common/UDPSocket.h
M lldb/include/lldb/Host/linux/AbstractSocket.h
M lldb/include/lldb/Host/posix/DomainSocket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/common/UDPSocket.cpp
M lldb/source/Host/linux/AbstractSocket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/DomainSocket.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/debugserver/RNBSocketTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
Log Message:
-----------
[lldb] Remove child_process_inherit from the socket classes (#117699)
It's never set to true. Also, using inheritable FDs in a multithreaded
process pretty much guarantees descriptor leaks. It's better to
explicitly pass a specific FD to a specific subprocess, which we already
mostly can do using the ProcessLaunchInfo FileActions.
Commit: f6694534ac86cb6949b241c11ddc7fd8ee44f027
https://github.com/llvm/llvm-project/commit/f6694534ac86cb6949b241c11ddc7fd8ee44f027
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[Driver] Remove non MSVC CL flags /fprofile-sample-use (#117970)
Those flags are introduced in #117282. They are not supported by MSVC.
Commit: 69d66fafec968b17f84e30bc09faffb3dc8e5f15
https://github.com/llvm/llvm-project/commit/69d66fafec968b17f84e30bc09faffb3dc8e5f15
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Fix description for fprofile-sample-use= on Windows (#117973)
We only support -fprofile-sample-use= for clang-cl.
Commit: 3ffee0086c1e31094e544c878f9d5cc413d36b46
https://github.com/llvm/llvm-project/commit/3ffee0086c1e31094e544c878f9d5cc413d36b46
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
M llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
Log Message:
-----------
[llvm-debuginfo-analyzer] Fix compile/link errors on specific builders. (#117971)
Link errors on builders:
- llvm-nvptx-nvidia-ubuntu
- llvm-nvptx64-nvidia-ubuntu
Add explicitly references to DebugInfoDWARF and Object.
Compile errors on builders:
- ppc64le-lld-multistage-test
- clang-ppc64le-linux-multistage
- clang-ppc64le-rhel
error: comparison of integers of different signs:
Add to the constants used in the 'EXPECT_EQ' the 'u' postfix.
Commit: 60db321081be2324bec7e18eb76421cc566625fd
https://github.com/llvm/llvm-project/commit/60db321081be2324bec7e18eb76421cc566625fd
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-frame-tail.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
Log Message:
-----------
[AArch64] Do not mark homogeneous prolog/epilog functions optnone (#117959)
The verifier complains that synthesized IR functions have minsize and
optnone attributes which are incompatible. This patch removes optnone
attribute and updates affected tests as needed.
Commit: 7173a7d7f9d3035e39508746efa46c2ec5c80119
https://github.com/llvm/llvm-project/commit/7173a7d7f9d3035e39508746efa46c2ec5c80119
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NVPTX][NFC] Use NAME macro for TMA intrinsic defs (#117907)
This patch updates the TMA intrinsic definitions to use the "NAME"
macro (inside the multiclass) instead of an empty string.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 332719561000dcac94384234ace1fa959362ad8e
https://github.com/llvm/llvm-project/commit/332719561000dcac94384234ace1fa959362ad8e
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
Log Message:
-----------
[mlir][LLVM][NFC] Implement `print/parse` for `LLVMStructType` (#117930)
The printing and parsing logic for struct types was still using ad-hoc
functions instead of the more conventional `print` and `parse` methods
whose declarations are automatically generated by TableGen.
This PR effectively renames these functions and uses them directly as
implementations for `print` and `parse` of `LLVMStructType`.
This additionally fixes linking errors when users or auto generated code
may call `print` and `parse` directly.
Fixes https://github.com/llvm/llvm-project/issues/117927
Commit: 76e6c8d3fc3dc097a3bd96e8959f73a809493976
https://github.com/llvm/llvm-project/commit/76e6c8d3fc3dc097a3bd96e8959f73a809493976
Author: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
A clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
Log Message:
-----------
Codegen changes for strict modifier with grainsize/num_tasks of taskloop construct (#117196)
Initial parsing/sema for 'strict' modifier with 'num_tasks' and
‘grainsize’ clause is present in these commits
[grainsize_parsing](https://github.com/llvm/llvm-project/commit/ab9eac762c35068e77f57795e660d06f578c9614)
and
[num_tasks_parsing](https://github.com/llvm/llvm-project/commit/56c166017055595a9f26933e85bfd89e30c528d0#diff-4184486638e85284c3a2c961a81e7752231022daf97e411007c13a6732b50db9R6545)
. However, this implementation appears incomplete as it lacks code
generation support. A runtime patch was introduced in this runtime
commit
[runtime_patch](https://github.com/llvm/llvm-project/commit/540007b42701b5ac9adba076824bfd648a265413#diff-5e95f9319910d6965d09c301359dbe6b23f3eef5ce4d262ef2c2d2137875b5c4R374)
, which adds a new API, _kmpc_taskloop_5, to accommodate the strict
modifier.
In this patch I have added codegen support. When the strict modifier is
present alongside the grainsize or num_tasks clauses of taskloop
construct, the code now emits a call to _kmpc_taskloop_5, which includes
an additional parameter of type i32 with the value 1 to indicate the
strict modifier. If the strict modifier is not present, it falls back to
the existing _kmpc_taskloop API call.
---------
Co-authored-by: Chandra Ghale <ghale at pe31.hpc.amslabs.hpecorp.net>
Commit: 89b08c8ee7b5184f8cfb0d356f2762173fb87d42
https://github.com/llvm/llvm-project/commit/89b08c8ee7b5184f8cfb0d356f2762173fb87d42
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Simplify generated code for isSubclass (#117351)
Implement isSubclass with direct lookup into some tables instead of
nested switches.
Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
Commit: 71648a4ef93867ce47afa512f6cf808be3cd0a2e
https://github.com/llvm/llvm-project/commit/71648a4ef93867ce47afa512f6cf808be3cd0a2e
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
Log Message:
-----------
Make MCDCRecord::getNumConditions() `const&`
Some users were trying to get a reference to the return value.
Commit: 0604d13790b20f6b385507bb63c62aa87162da9b
https://github.com/llvm/llvm-project/commit/0604d13790b20f6b385507bb63c62aa87162da9b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/SemaCXX/attr-no-specializations.cpp
Log Message:
-----------
[Clang] Add [[clang::no_specializations]] (#101469)
This can be used to inform users when a template should not be
specialized. For example, this is the case for the standard type traits
(except for `common_type` and `common_reference`, which have more
complicated rules).
Commit: f8f238d38eaa0a2e27f09fb6d01bcc8e7eab9e93
https://github.com/llvm/llvm-project/commit/f8f238d38eaa0a2e27f09fb6d01bcc8e7eab9e93
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[AArch64] Add extra add/cast tests for select-optimize.
Extra tests for https://github.com/llvm/llvm-project/pull/115489
with different operand order. Also fixes the target triple.
Commit: 2c242b98c608021e6768f0369498f5b8b5144d34
https://github.com/llvm/llvm-project/commit/2c242b98c608021e6768f0369498f5b8b5144d34
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
Log Message:
-----------
[clang] Add a lifetime_capture_by testcase for temporary capturing object. (#117733)
Add a test case to indicate this is an expected behavior.
Commit: 88c2af80fac423fc338027c007e1499333f05ddb
https://github.com/llvm/llvm-project/commit/88c2af80fac423fc338027c007e1499333f05ddb
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[NFC][clang][FMV][TargetInfo] Refactor API for FMV feature priority. (#116257)
Currently we have code with target hooks in CodeGenModule shared between
X86 and AArch64 for sorting MultiVersionResolverOptions. Those are used
when generating IFunc resolvers for FMV. The RISCV target has different
criteria for sorting, therefore it repeats sorting after calling
CodeGenFunction::EmitMultiVersionResolver.
I am moving the FMV priority logic in TargetInfo, so that it can be
implemented by the TargetParser which then makes it possible to query it
from llvm. Here is an example why this is handy:
https://github.com/llvm/llvm-project/pull/87939
Commit: 3b8426d340ab730ee3303257ea204ee083b1273a
https://github.com/llvm/llvm-project/commit/3b8426d340ab730ee3303257ea204ee083b1273a
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M .ci/generate_test_report.py
Log Message:
-----------
[ci] Fix unit tests for test report generator
Last time I fixed a bug here I forgot to update them.
Commit: 0c0f765cab4b16eb0342d514584cdf64cabc433a
https://github.com/llvm/llvm-project/commit/0c0f765cab4b16eb0342d514584cdf64cabc433a
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/test/CodeGen/Thumb/frame-chain.ll
A llvm/test/CodeGen/Thumb/returnaddress.ll
Log Message:
-----------
[ARM] Fix llvm.returnaddress for Thumb1 with R11 frame-pointer (#117735)
When the llvm.returnaddress intrinsic is used, the LR is marked as
live-in to the function, so it must be preserved through the prologue.
This is normally fine, but there is one case for Thumb1 where we use LR
as a temporary in the prologue to set up a frame chain using r11 as the
frame pointer. There are no other registers guaranteed to be free to do
this, so we have to re-load LR from the stack after pushing the callee
saved registers.
Commit: 79eb406a67fe08458548289da72cda18248a9313
https://github.com/llvm/llvm-project/commit/79eb406a67fe08458548289da72cda18248a9313
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A mlir/include/mlir/Conversion/MeshToMPI/MeshToMPI.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
A mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
Log Message:
-----------
[mlir][mesh, MPI] Mesh2mpi (#104566)
Pass for lowering `Mesh` to `MPI`.
Initial commit lowers `UpdateHaloOp` only.
Commit: 04a2d50efd668b752718f90811a7c628bfa761d7
https://github.com/llvm/llvm-project/commit/04a2d50efd668b752718f90811a7c628bfa761d7
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
A llvm/test/CodeGen/PowerPC/frameindex-negative-offset.ll
Log Message:
-----------
[PPC] Use getSignedConstant() for frame index offset
The offset is signed. Fixes assertion failure reported at:
https://github.com/llvm/llvm-project/pull/117558#issuecomment-2504413074
Commit: 61653f8e39666ea974561fd9ddccd7d473852fad
https://github.com/llvm/llvm-project/commit/61653f8e39666ea974561fd9ddccd7d473852fad
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/test/CodeGen/AArch64/init-undef.mir
Log Message:
-----------
Reland "[InitUndef] handleSubReg should skip artificial subregs. (#116248)"
This patch can now reland after 318c69de52b6 relanded #114827.
This reverts commit 1683f84d289348ba6879635c4161979204f75230.
Commit: 243c9791872a694ca341cc51c18d96fbc189a06b
https://github.com/llvm/llvm-project/commit/243c9791872a694ca341cc51c18d96fbc189a06b
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
Log Message:
-----------
Reland "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)"
This patch can now reland after 318c69de52b6 relanded #114827.
This reverts commit 14a58a1390a72ba6c66606e58e86425dcb902763.
Commit: 0f131704386db648e6b9388172bb93824823e277
https://github.com/llvm/llvm-project/commit/0f131704386db648e6b9388172bb93824823e277
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
Log Message:
-----------
[SPIR-V] Implement intrinsics llvm.scmp.* and llvm.ucmp.* (#117341)
This PR add translation of intrinsics `llvm.scmp.*` and `llvm.ucmp.*`.
Commit: 831469fb552ba03d15fb717eeb526a71bfac8b6d
https://github.com/llvm/llvm-project/commit/831469fb552ba03d15fb717eeb526a71bfac8b6d
Author: Marc Auberer <marc.auberer at chillibits.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M .github/new-issues-labeler.yml
Log Message:
-----------
Automatically add false-positive/false-negative labels (#117811)
Fixes #117762
Commit: 82821254f532c1dbdfd5d985ef7130511efaaa83
https://github.com/llvm/llvm-project/commit/82821254f532c1dbdfd5d985ef7130511efaaa83
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-alloca-in-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)
If IVUpdateMayOverflow is false, we proved that the induction increment
cannot overflow in the vector loop. This allows setting NUW in some
cases when folding the tail.
PR: https://github.com/llvm/llvm-project/pull/111758
Commit: 871e3dc8d8717bbcf5e3ad44331a21c3417c2639
https://github.com/llvm/llvm-project/commit/871e3dc8d8717bbcf5e3ad44331a21c3417c2639
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/tools/lldb-server/lldb-gdbserver.cpp
Log Message:
-----------
[lldb] Fixup #117699 for windows builds
Commit: 992b00020fae2d8b0f150a45885768551a867a10
https://github.com/llvm/llvm-project/commit/992b00020fae2d8b0f150a45885768551a867a10
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Reland #2 - [Offload] Introduce offload-tblgen and initial new API implementation (#108413. #117704) (#117894)
Relands #117704, which relanded changes from #108413 - this was reverted
due to build issues. The new offload library did not build with
`LIBOMPTARGET_OMPT_SUPPORT` enabled, which was not picked up by
pre-merge testing.
The last commit contains the fix; everything else is otherwise identical
to the approved PR.
___
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
# From the runtime build directory
$ ninja LibomptUnitTests
$ OFFLOAD_TRACE=1 ./offload/unittests/OffloadAPI/offload.unittests
```
### Open questions and future work
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: 98204a2e5bb754b0260175e42614c5463807beb5
https://github.com/llvm/llvm-project/commit/98204a2e5bb754b0260175e42614c5463807beb5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
A llvm/test/Bitcode/Inputs/invalid-initializer.bc
M llvm/test/Bitcode/invalid.test
Log Message:
-----------
[Bitcode] Verify types for aggregate initializers
Unfortunately all the nice error messages get lost because we
don't forward errors from lazy value materialization.
Fixes https://github.com/llvm/llvm-project/issues/117707.
Commit: b869f1bd4fc96fd1d2038720bd1ca84788d71370
https://github.com/llvm/llvm-project/commit/b869f1bd4fc96fd1d2038720bd1ca84788d71370
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
Log Message:
-----------
[clang] Remove unused lambda capture (NFC)
/llvm-project/clang/lib/Basic/Targets/X86.cpp:1368:23:
error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture]
auto getPriority = [this](StringRef Feature) -> unsigned {
^~~~
1 error generated.
Commit: 159e6012beb5cfd9864b4e2a910086d6f1230b03
https://github.com/llvm/llvm-project/commit/159e6012beb5cfd9864b4e2a910086d6f1230b03
Author: 执着 <118413413+dty2 at users.noreply.github.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Stop.h
M flang/include/flang/Runtime/stop.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/runtime/stop.cpp
A flang/test/Lower/Intrinsics/backtrace.f90
Log Message:
-----------
[flang]Add new intrinsic function backtrace and complete the TODO of abort (#117603)
Hey guys, I found that Flang's built-in ABORT function is incomplete
when I was using it. Compared with gfortran's ABORT (which can both
abort and print out a backtrace), flang's ABORT implementation lacks the
function of printing out a backtrace. This feature is essential for
debugging and understanding the call stack at the failure point.
To solve this problem, I completed the "// TODO:" of the abort function,
and then implemented an additional built-in function BACKTRACE for
flang. After a brief reading of the relevant source code, I used
backtrace and backtrace_symbols in "execinfo.h" to quickly implement
this. But since I used the above two functions directly, my
implementation is slightly different from gfortran's implementation (in
the output, the function call stack before main is additionally output,
and the function line number is missing). In addition, since I used the
above two functions, I did not need to add -g to embed debug information
into the ELF file, but needed -rdynamic to ensure that the symbols are
added to the dynamic symbol table (so that the function name will be
printed out).
Here is a comparison of the output between gfortran 's backtrace and my
implementation:
gfortran's implemention output:
```
#0 0x557eb71f4184 in testfun2_
at /home/hunter/plct/fortran/test.f90:5
#1 0x557eb71f4165 in testfun1_
at /home/hunter/plct/fortran/test.f90:13
#2 0x557eb71f4192 in test_backtrace
at /home/hunter/plct/fortran/test.f90:17
#3 0x557eb71f41ce in main
at /home/hunter/plct/fortran/test.f90:18
```
my impelmention output:
```
Backtrace:
#0 ./test(_FortranABacktrace+0x32) [0x574f07efcf92]
#1 ./test(testfun2_+0x14) [0x574f07efc7b4]
#2 ./test(testfun1_+0xd) [0x574f07efc7cd]
#3 ./test(_QQmain+0x9) [0x574f07efc7e9]
#4 ./test(main+0x12) [0x574f07efc802]
#5 /usr/lib/libc.so.6(+0x25e08) [0x76954694fe08]
#6 /usr/lib/libc.so.6(__libc_start_main+0x8c) [0x76954694fecc]
#7 ./test(_start+0x25) [0x574f07efc6c5]
```
test program is:
```
function testfun2() result(err)
implicit none
integer :: err
err = 1
call backtrace
end function testfun2
subroutine testfun1()
implicit none
integer :: err
integer :: testfun2
err = testfun2()
end subroutine testfun1
program test_backtrace
call testfun1()
end program test_backtrace
```
I am well aware of the importance of line numbers, so I am now working
on implementing line numbers (by parsing DWARF information) and
supporting cross-platform (Windows) support.
Commit: 1858a4ebf0ebe9f1f3be6204af204e420e33bb6a
https://github.com/llvm/llvm-project/commit/1858a4ebf0ebe9f1f3be6204af204e420e33bb6a
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Stop.h
M flang/include/flang/Runtime/stop.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/runtime/stop.cpp
R flang/test/Lower/Intrinsics/backtrace.f90
Log Message:
-----------
Revert "[flang]Add new intrinsic function backtrace and complete the TODO of abort" (#117990)
Reverts llvm/llvm-project#117603 due to failed buildbot
https://lab.llvm.org/buildbot/#/builders/152/builds/710
The important bit of the log was
```
FAILED: CMakeFiles/FortranRuntime.dir/stop.cpp.o
ccache /usr/bin/g++ -DFLANG_LITTLE_ENDIAN=1 -DGTEST_HAS_RTTI=0 -DRT_USE_LIBCUDACXX=1 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/../include -I/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/build -I/home/buildbot/worker/third-party/nv/cccl/libcudacxx/include -fvisibility-inlines-hidden -Werror=date-time -fno-lifetime-dse -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -Wimplicit-fallthrough -Wno-nonnull -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -fno-lto -O3 -DNDEBUG -U_GLIBCXX_ASSERTIONS -U_LIBCPP_ENABLE_ASSERTIONS -UNDEBUG -std=c++17 -fno-exceptions -fno-unwind-tables -fno-asynchronous-unwind-tables -fno-rtti -MD -MT CMakeFiles/FortranRuntime.dir/stop.cpp.o -MF CMakeFiles/FortranRuntime.dir/stop.cpp.o.d -o CMakeFiles/FortranRuntime.dir/stop.cpp.o -c /home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/stop.cpp
/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/stop.cpp:19:10: fatal error: llvm/Config/config.h: No such file or directory
19 | #include "llvm/Config/config.h"
| ^~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
```
CC @dty2
Commit: 6f55d7d22c1ebf2b8425c5864b335762bc3d5363
https://github.com/llvm/llvm-project/commit/6f55d7d22c1ebf2b8425c5864b335762bc3d5363
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/79eb406a67fe08458548289da72cda18248a9313
Commit: cf47898453c83c977f92155c03e9cf205bfb2b19
https://github.com/llvm/llvm-project/commit/cf47898453c83c977f92155c03e9cf205bfb2b19
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
Log Message:
-----------
[clang] Remove unused lambda capture. (#117988)
Fixes regression in sanitizer buildbots caused by #116257.
Commit: b7749efb749541716b6785c48fc8d6c2a4453ffb
https://github.com/llvm/llvm-project/commit/b7749efb749541716b6785c48fc8d6c2a4453ffb
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/lib/Dialect/MPI/IR/CMakeLists.txt
M mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
Log Message:
-----------
adding MLIRMemRefDialect (#117986)
fixing post-CI failures #104566
Commit: 32ef417603e1b747c2be946f8193fdb7c31d957e
https://github.com/llvm/llvm-project/commit/32ef417603e1b747c2be946f8193fdb7c31d957e
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
Log Message:
-----------
Fix CMake dependencies on mlir-linalg-ods-yaml-gen (#113565)
Fix a number of dependencies issue to build mlir-linalg-ods-yaml-gen
host binary which make a cross-build using the Make generator fail.
Namely:
- do not use binary path for the custom target created when
LLVM_USE_HOST_TOOLS is true;
- use target name instead of name of variable holding the target name
for add_custom_target and set_target_properties in setup_host_tool();
- force setting of executable and target cache variable which are only
used as global variables;
- remove dependency on target defined in different directory in
add_linalg_ods_yaml_gen() since add_custom_target DEPENDS can only be
used on "files and outputs of custom commands created with
add_custom_command() command calls in the same directory";
- remove unneeded dependency on ${MLIR_LINALG_ODS_YAML_GEN_EXE}, the
target dependency will ensure the binary will be built.
Note that we keep using ${MLIR_LINALG_ODS_YAML_GEN_EXE} in the COMMAND
rather than use ${MLIR_LINALG_ODS_YAML_GEN_TARGET} because when
LLVM_NATIVE_TOOL_DIR is used the latter is an empty string.
Testing-wise, all three codepaths in get_host_tool_path() were tested
with both GNU Make and Ninja generators:
- cross-compiling with LLVM_NATIVE_TOOL_DIR checks the if path;
- cross-compiling without LLVM_NATIVE_TOOL_DIR checks the elseif path;
- native build without LLVM_NATIVE_TOOL_DIR checks the else path.
Commit: 6e720df1ae23c715aefc36476ab46284a96e9371
https://github.com/llvm/llvm-project/commit/6e720df1ae23c715aefc36476ab46284a96e9371
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
Log Message:
-----------
[clang] Improve the lifetime_capture_by diagnostic on the constructor. (#117792)
With this change, the lifetime_capture_by code path will not handle the
constructor decl to avoid bogus diagnostics (see the testcase).
Instead, we reuse the lifetimebound code as the
lifetime_capture_by(this) has the same semantic as lifetimebound in
constructor. The downside is that the lifetimebound diagnostic is reused
for the capture case (I think it is not a big issue).
Fixes #117680
Commit: cb5bdf8ce095b0b9fe874545e4d54d97d552a1c4
https://github.com/llvm/llvm-project/commit/cb5bdf8ce095b0b9fe874545e4d54d97d552a1c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
Log Message:
-----------
[X86] Remove HSW/BDW incorrect MOVQ2DQ override
MOVQ2DQ is treated the same as other vector moves on Port015 (matches SandyBridge, not Skylake or later).
Confirmed by augner/uops.info
Commit: 5208bc3694473f9378fc0d98eeee63e5ad5c5f04
https://github.com/llvm/llvm-project/commit/5208bc3694473f9378fc0d98eeee63e5ad5c5f04
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "Reland #2 - [Offload] Introduce offload-tblgen and initial new API implementation (#108413. #117704)" (#117995)
Reverts llvm/llvm-project#117894
Buildbot failures in OpenMP/Offload bots.
https://lab.llvm.org/buildbot/#/builders/30/builds/11193
Commit: 392bd3404b98c2be74e4e94d2019dffaa85919eb
https://github.com/llvm/llvm-project/commit/392bd3404b98c2be74e4e94d2019dffaa85919eb
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
Log Message:
-----------
[WebAssembly] use poison instead of undef as placeholder for missing args [NFC]
Commit: 12ccb628da231f3ab751c8e7b759e9920d38510b
https://github.com/llvm/llvm-project/commit/12ccb628da231f3ab751c8e7b759e9920d38510b
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
Log Message:
-----------
[clang] Add a common definition of isPointerLikeType for lifetime analysis (#117315)
Also checks for annotation for template specializations which sometimes
may not have the annotation attached.
Commit: e4ee970c4b286b472a4c0b0cb43da85f77e97d79
https://github.com/llvm/llvm-project/commit/e4ee970c4b286b472a4c0b0cb43da85f77e97d79
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/utils/TableGen/SveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
Log Message:
-----------
[AArch64] Implement intrinsics for F1CVTL/F2CVTL and BF1CVTL/BF2CVTL (#116959)
This patch implements the following intrinsics:
8-bit floating-point convert to deinterleaved half-precision or
BFloat16.
``` c
// Variant is also available for: _bf16[_mf8]_x2
svfloat16x2_t svcvtl1_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm) __arm_streaming;
svfloat16x2_t svcvtl2_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm) __arm_streaming;
```
Defined in https://github.com/ARM-software/acle/pull/323
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Marian Lukac marian.lukac at arm.com
Commit: c952f0ee5436318733c1ab21a8a7402f7f0a4caa
https://github.com/llvm/llvm-project/commit/c952f0ee5436318733c1ab21a8a7402f7f0a4caa
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/critical_within_default.f90
Log Message:
-----------
[Flang][OpenMP] Do not default privatize symbols that are not variables (#117886)
Fixes an issue where the compiler is trying to default privatize
construct names.
Fixes #112572
Commit: 53326ee0cf45fce3f80e2e98638dd27edb20c516
https://github.com/llvm/llvm-project/commit/53326ee0cf45fce3f80e2e98638dd27edb20c516
Author: Nathan Gauër <brioche at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/branching/if-merging.ll
M llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll
M llvm/test/CodeGen/SPIRV/instructions/ret-type.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll
M llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll
M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-simple-while-identity.ll
M llvm/test/CodeGen/SPIRV/structurizer/return-early.ll
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVSortBlocksTests.cpp
Log Message:
-----------
[SPIR-V] Fix block sorting with irreducible CFG (#116996)
Block sorting was assuming reducible CFG. Meaning we always had a best
node to continue with. Irreducible CFG makes breaks this assumption, so
the algorithm looped indefinitely because no node was a valid candidate.
Fixes #116692
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 79dab3f5ebac85b7cd1f4b1943d72776db9bcf70
https://github.com/llvm/llvm-project/commit/79dab3f5ebac85b7cd1f4b1943d72776db9bcf70
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
Log Message:
-----------
[CostModel][X86] Add shuffle 'splat' tests for broadcasts of non-zero element index.
As noticed on #115201 - its possible for SK_Broadcast to occur for non-zero element index which we don't currently handle.
Commit: ddaf1d68784a03fd3d476e25689f25ba9c5f961a
https://github.com/llvm/llvm-project/commit/ddaf1d68784a03fd3d476e25689f25ba9c5f961a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/gfni-lzcnt.ll
A llvm/test/CodeGen/X86/gfni-tzcnt.ll
Log Message:
-----------
[X86] Add GFNI test coverage for vXi8 LZCNT/TZCNT
Commit: 07a8ebed56cfa223d1587903e4de0d5788b5f777
https://github.com/llvm/llvm-project/commit/07a8ebed56cfa223d1587903e4de0d5788b5f777
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/warn-memaccess.cpp
Log Message:
-----------
[clang] Move warning about memset/memcpy to NonTriviallyCopyable type… (#117387)
…s to its own flag
Namely -Wnontrivial-memcall, implied by -Wnontrivial-memaccess
This is a followup to #111434
Commit: c5cd1e958c2cea9fe5a6a9087c3481537d598e24
https://github.com/llvm/llvm-project/commit/c5cd1e958c2cea9fe5a6a9087c3481537d598e24
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/__vector/vector_bool.h
M libcxx/test/std/containers/sequences/vector.bool/ctor_exceptions.pass.cpp
A libcxx/test/std/containers/sequences/vector/common.h
Log Message:
-----------
[libc++] Add exception guard for vector<bool>::__init_with_sentinel (#115491)
As a drive-by, also improve the test coverage for throwing exceptions
in vector<bool> constructors.
Commit: 3923e0451a4b02c4fe7c394e0f0ec90708ebca7a
https://github.com/llvm/llvm-project/commit/3923e0451a4b02c4fe7c394e0f0ec90708ebca7a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
Log Message:
-----------
[AMDGPU] Preserve all analyses if nothing changed (#117994)
Commit: 6cbc37383f4ad32474a59976df3da0ee53f68fed
https://github.com/llvm/llvm-project/commit/6cbc37383f4ad32474a59976df3da0ee53f68fed
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/CMakeLists.txt
R libcxx/src/legacy_pointer_safety.cpp
Log Message:
-----------
[libc++] Remove the pointer safety functions from the dylib (#117390)
The pointer safety functions were never implemented by anyone in a
non-trivial way, which lead us to removing them entirely from the
headers when they were removed in C++23. This also means that just about
nobody ever called these functions, especially not in production code.
Because of that, we expect there to be no references in the wild to the
functions in the dylib. Because of that, this patch removes the symbols
from the dylib.
Commit: c4fbb6500a557fec592af8b9c398169591cdcc5d
https://github.com/llvm/llvm-project/commit/c4fbb6500a557fec592af8b9c398169591cdcc5d
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_GNU_template_name.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/DW_AT_GNU_template_name.ll
Log Message:
-----------
[llvm-debuginfo-analyzer] Add support for DW_AT_GNU_template_name. (#115724)
For the given C++ code:
```
template <typename T> class Foo { T Member; };
template <template <typename T> class TemplateType>
class Bar {
TemplateType<int> Int;
};
template <template <template <typename> class> class TemplateTemplateType>
class Baz {
TemplateTemplateType<Foo> Foo;
};
typedef Baz<Bar> Example;
Example TT;
```
The '--attribute=encoded' option, will produce the logical view:
```
{Class} 'Foo<int>'
{Encoded} <int>
{Class} 'Bar<Foo>'
{Encoded} <> <-- Missing the template argument info (Foo)
{Class} 'Baz<Bar>'
{Encoded} <> <-- Missing the template argument info (Bar)
```
When the template argument is another template it is not included in the
{Encoded} field. The correct output should be:
```
{Class} 'Foo<int>'
{Encoded} <int>
{Class} 'Bar<Foo>'
{Encoded} <Foo>
{Class} 'Baz<Bar>'
{Encoded} <Bar>
```
Commit: b5ed375f9d63c1f37bb490f32898e6dc711c8a15
https://github.com/llvm/llvm-project/commit/b5ed375f9d63c1f37bb490f32898e6dc711c8a15
Author: Peter Waller <peter.waller at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/check-init-not-moved.s
Log Message:
-----------
[BOLT] Skip _init; avoiding GOT breakage for static binaries (#117751)
_init is used during startup of binaires. Unfortunately, its
address can be shared (at least on AArch64 glibc static binaries) with a
data
reference that lives in the GOT. The GOT rewriting is currently unable
to distinguish between data addresses and function addresses. This leads
to the data address being incorrectly rewritten, causing a crash on
startup of the binary:
Unexpected reloc type in static binary.
To avoid this, don't consider _init for being moved, by skipping it.
~We could add further conditions to narrow the skipped case for known
crashes, but as a straw man I thought it'd be best to keep the condition
as simple as possible and see if there any objections to this.~
(Edit: this broke the test
bolt/test/runtime/X86/retpoline-synthetic.test,
because _init was skipped from the retpoline pass and it has an indirect
call in it, so I include a check for static binaries now, which avoids
the test failure,
but perhaps this could/should be narrowed further?)
For now, skip _init for static binaries on any architecture; we could
add further conditions to narrow the skipped case for known crashes, but
as a straw man I thought it'd be best to keep the condition as simple as
possible and see if there any objections to this.
Updates #100096.
Commit: 3a01b46dae1a00f77ed8c46a4239595803c9e35e
https://github.com/llvm/llvm-project/commit/3a01b46dae1a00f77ed8c46a4239595803c9e35e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Move getGFNICtrlMask before CTLZ/CTTZ lowering. NFC.
Pulled out of #118012
Commit: 2a6e5896a572c3be47ffe78afed8ba6ef278d336
https://github.com/llvm/llvm-project/commit/2a6e5896a572c3be47ffe78afed8ba6ef278d336
Author: Rafael Eckstein <44746868+Casperento at users.noreply.github.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/unittests/Transforms/Utils/CMakeLists.txt
A llvm/unittests/Transforms/Utils/MergeFunctionsTest.cpp
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Log Message:
-----------
[MergeFunctions] Add support to run the pass over a set of function pointers (#111045)
This modification will enable the usage of `MergeFunctions` as a
standalone library. Currently, `MergeFunctions` can only be applied to
an entire module. By adopting this change, developers will gain the
flexibility to reuse the `MergeFunctions` code within their own
projects, choosing which functions to merge; hence, promoting code
reusability. Notice that this modification will not break backward
compatibility, because `MergeFunctions` will still work as a pass after
the modification.
Commit: b96e7570c991f1bb67646a20427a83f247326a25
https://github.com/llvm/llvm-project/commit/b96e7570c991f1bb67646a20427a83f247326a25
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/IPO/CMakeLists.txt
A llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
M llvm/unittests/Transforms/Utils/CMakeLists.txt
R llvm/unittests/Transforms/Utils/MergeFunctionsTest.cpp
Log Message:
-----------
[UnitTests] Move MergeFunction test from Utils to IPO
So we depend on the correct library.
Commit: 45b567be8d0d430c786c41f826d192fadf863bb8
https://github.com/llvm/llvm-project/commit/45b567be8d0d430c786c41f826d192fadf863bb8
Author: Nathan Gauër <brioche at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVPartialOrderingVisitorTests.cpp
Log Message:
-----------
[SPIR-V] Add partial order tests, assert reducible (#117887)
Add testing for the visitor and added a note explaining irreducible CFG
are not supported.
Related to #116692
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 66d350a01738c0c64a28b943af5e995a5fbc348d
https://github.com/llvm/llvm-project/commit/66d350a01738c0c64a28b943af5e995a5fbc348d
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/PowerPC/ssubo-32.ll
Log Message:
-----------
[PowerPC][NFC] Pre-commit test case to prepare for patch to custom lower ssubo
Commit: f623df6376b94906671ad6e875e6f504b74fed31
https://github.com/llvm/llvm-project/commit/f623df6376b94906671ad6e875e6f504b74fed31
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
Log Message:
-----------
[InstSimplify] Add tests for monotonic icmps (NFC)
Commit: 12cefcc7ecd2615069206b35b0ea81b9e78bb1ea
https://github.com/llvm/llvm-project/commit/12cefcc7ecd2615069206b35b0ea81b9e78bb1ea
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
A llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int-also-fusable-multiply.ll
Log Message:
-----------
[Matrix] Skip already fused instructions before trying to fuse multiply.
lowerDotProduct called above may already lower a matrix multiply and
mark it as procssed by adding it to FusedInsts. Don't try to process it
again in LowerMatrixMultiplyFused by checking if FusedInsts.
Without this change, we trigger an assertion when trying to erase the
same original matrix multiply twice.
Commit: 26fd693b979f17c83cbd5a3313fdea950ce3d356
https://github.com/llvm/llvm-project/commit/26fd693b979f17c83cbd5a3313fdea950ce3d356
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
Log Message:
-----------
RegisterCoalescer: Fix creating full / empty subrange on undef subreg use (#117936)
Commit: aa5cdcea3950b26a6b755201706bb1961e65eaa5
https://github.com/llvm/llvm-project/commit/aa5cdcea3950b26a6b755201706bb1961e65eaa5
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
LAA: improve code in a couple of routines (NFC) (#108092)
Commit: 4e8eabd93e2c60a9dc2f6afde506012fbca77f81
https://github.com/llvm/llvm-project/commit/4e8eabd93e2c60a9dc2f6afde506012fbca77f81
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DeadStoreElimination/stores-of-existing-values.ll
Log Message:
-----------
DSE: pre-commit tests for scalable vectors (#110669)
As AliasAnalysis now has support for scalable sizes, add tests to
DeadStoreElimination covering the scalable vectors case, in preparation
to extend it.
Commit: b207a17ea07df4cbcae5509dee3e8e1d09a485df
https://github.com/llvm/llvm-project/commit/b207a17ea07df4cbcae5509dee3e8e1d09a485df
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
R llvm/utils/merge-json.py
M runtimes/CMakeLists.txt
Log Message:
-----------
Revert "[Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)"
This reverts commit 054f914741421ca9dd1eaa58ea74a20f8695bae6, which was
found to break the runtimes build.
Commit: 261a4026e8a367eda229879838709b92abaf445c
https://github.com/llvm/llvm-project/commit/261a4026e8a367eda229879838709b92abaf445c
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate2.f90
M flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
Log Message:
-----------
[Flang][OpenMP] Use internal linkage for OpenMP code-gen'ed helper functions (#117911)
When compiling WORKSHARE construct in different compilation units, a
linker error happened, when two equal WORKSHARE constructs with a copy
operation have been compiled:
```
/usr/bin/ld: module2.o: in function `_workshare_copy_f64':
FIRModule:(.text+0x0): multiple definition of `_workshare_copy_f64'; module1.o:FIRModule:(.text+0x0): first defined here
```
Reason is that the generate copy function has the wrong linkage:
```
0000000000000000 T _workshare_copy_f64
```
while it should be
```
0000000000000000 t _workshare_copy_f64
```
Commit: 335cfb3441242a78447d1db42cd67ce9eba829db
https://github.com/llvm/llvm-project/commit/335cfb3441242a78447d1db42cd67ce9eba829db
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Headers/avx512vpopcntdqintrin.h
M clang/lib/Headers/avx512vpopcntdqvlintrin.h
M clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c
M clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
Log Message:
-----------
[clang][x86] Add initial constexpr support for VPOPCNTDQ intrinsics (#118017)
#117473 added constexpr support to __builtin_elementwise_popcount - which the VPOPCNTDQ intrinsics just wrap.
Still working on how to make __builtin_ia32_select* intrinsic wrappers constexpr
Commit: 611ccfcae9842a1356195189d5595ef1684e3df4
https://github.com/llvm/llvm-project/commit/611ccfcae9842a1356195189d5595ef1684e3df4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Add reduced test case for #114360
Commit: 448ac7d3418a31d35b462440c8bf644287efac8a
https://github.com/llvm/llvm-project/commit/448ac7d3418a31d35b462440c8bf644287efac8a
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
Log Message:
-----------
[lldb][Mach-O] Handle shared cache binaries correctly (#117832)
The Mach-O load commands have an LC_SYMTAB / struct symtab_command which
represents the offset of the symbol table (nlist records) and string
table for this binary. In a mach-o binary on disk, these are file
offsets. If a mach-o binary is loaded in memory with all segments
consecutive, the `symoff` and `stroff` are the offsets from the TEXT
segment (aka the mach-o header) virtual address to the virtual address
of the start of these tables.
However, if a Mach-O binary is a part of the shared cache, then the
segments will be separated -- they will have different slide values. And
it is possible for the LINKEDIT segment to be greater than 4GB away from
the TEXT segment in the virtual address space, so these 32-bit offsets
cannot express the offset from TEXT segment to these tables.
Create separate uint64_t variables to track the offset to the symbol
table and string table, instead of reusing the 32-bit ones in the
symtab_command structure.
rdar://140432279
Commit: a4c8ef0f401d86040594cc6f01bcdad9392e8ee2
https://github.com/llvm/llvm-project/commit/a4c8ef0f401d86040594cc6f01bcdad9392e8ee2
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Fix detecting _Float16 support for secondary targets (#117813)
It turns out we were not passing -m32 to the check_c_source_compiles()
invocation since CMAKE_REQUIRE_FLAGS needs to be string separated list
and
we were passing a ;-separated CMake list which appears to be parsed by
CMake as 'ignore all arguments beyond the first'.
Fix this by transforming the list to a command line first.
With this change, Clang 17 no longer claims to support _Float16 for
i386.
Commit: dab4121a55225fd00f3db1cb232cf563ea573ef2
https://github.com/llvm/llvm-project/commit/dab4121a55225fd00f3db1cb232cf563ea573ef2
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
M llvm/test/CodeGen/PowerPC/ssubo-32.ll
Log Message:
-----------
[PowerPC] Add custom lowering for ssubo (#111748) (#115875)
This patch is to improve the codegen for ssubo node for i32 by custom lowering.
Commit: 961c66c57144ac46b65277338d9d1ebdc284e0df
https://github.com/llvm/llvm-project/commit/961c66c57144ac46b65277338d9d1ebdc284e0df
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] shrinkAndImmediate - bail on failed constant fold
Workaround for issue #114360 where shrinkAndImmediate folds away the AND after the ZEXT has already been folded away to SUBREG_TO_REG losing the implicit zext guarantee.
There's the possibility that other instructions can result in a similar regression, but this is a stopgap until I can investigate whether shrinkAndImmediate needs to be replaced entirely.
Fixes #114360
Commit: 056153f36eca184f81969f5cd5c8cd967c935f96
https://github.com/llvm/llvm-project/commit/056153f36eca184f81969f5cd5c8cd967c935f96
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__vector/vector.h
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/GenerateInput.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
Optimize vector::assign for InputIterator-only pair inputs (#113852)
This PR optimizes the input iterator overload of `assign(_InputIterator,
_InputIterator)` in `std::vector<_Tp, _Allocator>` by directly assigning
to already initialized memory, rather than first destroying existing
elements and then constructing new ones. By eliminating unnecessary
destruction and construction, the proposed algorithm enhances the
performance by up to 2x for trivial element types (e.g.,
`std::vector<int>`), up to 2.6x for non-trivial element types like
`std::vector<std::string>`, and up to 3.4x for more complex non-trivial
types (e.g., `std::vector<std::vector<int>>`).
### Google Benchmarks
Benchmark tests (`libcxx/test/benchmarks/vector_operations.bench.cpp`)
were conducted for the `assign()` implementations before and after this
patch. The tests focused on trivial element types like
`std::vector<int>`, and non-trivial element types such as
`std::vector<std::string>` and `std::vector<std::vector<int>>`.
#### Before
```
-------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------------------------------------------------
BM_AssignInputIterIter/vector_int/1024/1024 1157 ns 1169 ns 608188
BM_AssignInputIterIter<32>/vector_string/1024/1024 14559 ns 14710 ns 47277
BM_AssignInputIterIter<32>/vector_vector_int/1024/1024 26846 ns 27129 ns 25925
```
#### After
```
-------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------------------------------------------------
BM_AssignInputIterIter/vector_int/1024/1024 561 ns 566 ns 1242251
BM_AssignInputIterIter<32>/vector_string/1024/1024 5604 ns 5664 ns 128365
BM_AssignInputIterIter<32>/vector_vector_int/1024/1024 7927 ns 8012 ns 88579
```
Commit: 81c88135e402d3dfee7387acef86b173132cfb64
https://github.com/llvm/llvm-project/commit/81c88135e402d3dfee7387acef86b173132cfb64
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/locale
Log Message:
-----------
[libc++] Use the __strtoNUM functions from __locale instead of the old API (#118029)
The commit where I switched from using the old locale base API to the
new functions defined inside the __locale namespace forgot to update
references to the strtoNUM functions. This patch fixes that.
Commit: 59716479fc2f78ccabb2fc47b23cdc636d4ce122
https://github.com/llvm/llvm-project/commit/59716479fc2f78ccabb2fc47b23cdc636d4ce122
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A libcxx/docs/CodingGuidelines.rst
M libcxx/docs/Contributing.rst
M libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
R libcxx/docs/DesignDocs/NodiscardPolicy.rst
M libcxx/docs/index.rst
Log Message:
-----------
[libc++] Add coding guidelines to the docs (#117051)
We have a buch of coding guidelines which are either documented as
design docs, which aren't really applicable or not at all. This moves
coding guidelines we have currently in the design docs into a separate
file and adds a bunch of guidelines which we have but aren't documented
anywhere.
Commit: d648eed5899c4be10f1f7866eebef2bc171e673f
https://github.com/llvm/llvm-project/commit/d648eed5899c4be10f1f7866eebef2bc171e673f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++] Simplify the implementation of reserve() and shrink_to_fit() (#113453)
Since we changed the implementation of `reserve(size_type)` to only ever
extend,
it doesn't make a ton of sense anymore to have `__shrink_or_extend`,
since the code
paths of `reserve` and `shrink_to_fit` are now almost completely
separate.
This patch splits up `__shrink_or_extend` so that the individual parts
are in `reserve`
and `shrink_to_fit` depending on where they are needed.
Commit: d9c269577e6e68e1336461f266b20780f4d78dba
https://github.com/llvm/llvm-project/commit/d9c269577e6e68e1336461f266b20780f4d78dba
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Remove manual constant fold in VPWidenIntOrFpInductionRecipe. NFC (#118028)
This manual constant folding was added in 2017 in
https://reviews.llvm.org/D29956, but since then it looks like IRBuilder
has learnt to fold it away itself.
I'm not sure at what point this happened, I just verified this by
stepping through the call to CreateVectorSplat in the debugger.
Commit: d106a39c3372b924668f203fedbce69aa986cf50
https://github.com/llvm/llvm-project/commit/d106a39c3372b924668f203fedbce69aa986cf50
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[AArch64] Minor cleanup and speedup for getVectorInstrCostHelper
If UserToExtractIdx is empty then we can skip checking the users.
Commit: f2d500c61701fc50f5c0c2cd9660a93e15ecc9b9
https://github.com/llvm/llvm-project/commit/f2d500c61701fc50f5c0c2cd9660a93e15ecc9b9
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Fix bug in `UnresolvedMaterializationRewrite` rollback (#105949)
When an unresolved materialization (`unrealized_conversion_cast` op) is
rolled back, the mapping should be rolled back as well, regardless of
whether it is a source, target or argument materialization. Otherwise,
we accumulate pointers to erased IR in the `mapping`. This is harmless
in most cases, but can cause issues when a new operation is allocated at
the same memory location and the pointer is "reused".
It is not possible to write a test case for this because I cannot
trigger the pointer reuse programmatically.
Commit: c2171d748685be8c7ce2366deefe01aaae1c61a0
https://github.com/llvm/llvm-project/commit/c2171d748685be8c7ce2366deefe01aaae1c61a0
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
Log Message:
-----------
[gn] port fb3765959f
Commit: 7c5300e73445310ba40515bc01c2da59d4c58d50
https://github.com/llvm/llvm-project/commit/7c5300e73445310ba40515bc01c2da59d4c58d50
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn build] Port 45b567be8d0d
Commit: 958ab3a4a53357ddf27b7ccae8bdbae5878d3cca
https://github.com/llvm/llvm-project/commit/958ab3a4a53357ddf27b7ccae8bdbae5878d3cca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn build] Port 53326ee0cf45
Commit: bfa6c9a959e15e4548e411144fc7eda7d6b7e4dc
https://github.com/llvm/llvm-project/commit/bfa6c9a959e15e4548e411144fc7eda7d6b7e4dc
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
Log Message:
-----------
[gn build] Port 6cbc37383f4a
Commit: eb42e94d9793d5426de64266ef637b3267ed0b40
https://github.com/llvm/llvm-project/commit/eb42e94d9793d5426de64266ef637b3267ed0b40
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Transforms/IPO/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port b96e7570c991
Commit: c5ab28a42db95e287bf7f4623e8f5703b2f200d9
https://github.com/llvm/llvm-project/commit/c5ab28a42db95e287bf7f4623e8f5703b2f200d9
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
Commit: dab9fa2d7f3b3092d4ab0c815868ec68a968a31a
https://github.com/llvm/llvm-project/commit/dab9fa2d7f3b3092d4ab0c815868ec68a968a31a
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Flang.h
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Driver/mabi-loongarch.f90
A flang/test/Fir/struct-passing-loongarch64-byreg.fir
A flang/test/Fir/struct-passing-return-loongarch64-bystack.fir
A flang/test/Fir/struct-return-loongarch64-byreg.fir
Log Message:
-----------
[Flang] LoongArch64 support for BIND(C) derived types in mabi=lp64d. (#117108)
This patch:
- Supports both the passing and returning of BIND(C) type parameters.
- Adds `mabi` check for LoongArch64. Currently, flang only supports
`mabi=` option
set to `lp64d` in LoongArch64, other ABIs will report an error and may
be supported
in the future.
Reference ABI:
https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#subroutine-calling-sequence
Commit: d714b221c77203107284544b8f5543bd4c35ccc9
https://github.com/llvm/llvm-project/commit/d714b221c77203107284544b8f5543bd4c35ccc9
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/AArch64/extract_float_streaming.ll
Log Message:
-----------
[AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. (#117749)
If the getRegisterBitWidth is zero (such as in sme streaming functions),
then we could hit a crash from using % RegWidth.
Commit: b2d3cb1e7502a5ddb7d6688dce5cf51573f6189c
https://github.com/llvm/llvm-project/commit/b2d3cb1e7502a5ddb7d6688dce5cf51573f6189c
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[TTI][RISCV] Remove deduplicate type-based VP costing of VPReduction.NFC (#117708)
Refered to: #115983
Commit: d83148f9b9debde1358f0686594da208ce33182e
https://github.com/llvm/llvm-project/commit/d83148f9b9debde1358f0686594da208ce33182e
Author: Abhishek Varma <avarma094 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[MLIR][Affine] Update ::fold() to have constant basis attr for affine.delinearize_index/linearize_index (#117572)
-- This commit updates `::fold()` to have constant(CST)
attribute for affine.delinearize_index/linearize_index op's basis
wherever applicable.
-- Essentially the code checks if the mixed basis OpFoldResult
set contains any constant SSA value and converts it to a constant
integer instead.
Signed-off-by: Abhishek Varma <abhvarma at amd.com>
Commit: 8fcbba82d6c8038c4a0c5859275523414107b198
https://github.com/llvm/llvm-project/commit/8fcbba82d6c8038c4a0c5859275523414107b198
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcisls-invalid.s
A llvm/test/MC/RISCV/xqcisls-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)
This extension adds 8 load/store instructions with a scaled index
addressing mode.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: d02c1676d75a6bab1252b48da9a955fc7dc1251f
https://github.com/llvm/llvm-project/commit/d02c1676d75a6bab1252b48da9a955fc7dc1251f
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Support/Error.h
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Object/XCOFFObjectFile.cpp
M llvm/lib/Support/DataExtractor.cpp
Log Message:
-----------
[Support][Error] Add ErrorAsOutParameter constructor that takes an Error by ref.
ErrorAsOutParameter's Error* constructor supports cases where an Error might not
be passed in (because in the calling context it's known that this call won't
fail). Most clients always have an Error present however, and for them an Error&
overload is more convenient.
Commit: cf478bf744fa2aacb634b151b7f6c9844f0d3851
https://github.com/llvm/llvm-project/commit/cf478bf744fa2aacb634b151b7f6c9844f0d3851
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] always clean up child process to avoid hanging ninja (#118049)
Commit: 01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
https://github.com/llvm/llvm-project/commit/01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
A llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
Log Message:
-----------
[RISCV] Set a barrier between mask producer and user of V0 (#114012)
Here we add a scheduling mutation in pre-ra scheduling, which will
add an artificial dependency edge between mask producer and its
previous nearest instruction that uses V0 register.
This prevents the overlap of live intervals of mask registers and
as a consequence we can reduce some spills/moves.
>From the test changes, we can see some improvements and also some
regressions (more vtype toggles).
Partially fixes #113489.
Commit: 9b163d2ee78383fe9a89e1f2e9c8c635a557cdf4
https://github.com/llvm/llvm-project/commit/9b163d2ee78383fe9a89e1f2e9c8c635a557cdf4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 01a15dca09e5
Commit: 9b5b3edd64e56af02295c0365269177443d4a64d
https://github.com/llvm/llvm-project/commit/9b5b3edd64e56af02295c0365269177443d4a64d
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
Log Message:
-----------
[clang-format][doc] Fix formatting, etc.
Commit: 18760ce0fd811140fe6cb9a01b766d73bb50bf4d
https://github.com/llvm/llvm-project/commit/18760ce0fd811140fe6cb9a01b766d73bb50bf4d
Author: AlexErofeev <framalex at nxt.ru>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/StmtPrinter.cpp
A clang/test/AST/ast-print-packindexingexpr.cpp
Log Message:
-----------
[Clang][AST] Fix PackIndexingExpr AST printout (#117947)
Fixes #116486
Also added a test
Commit: 2df0d2962725a26a1d8c438888f7e70946943589
https://github.com/llvm/llvm-project/commit/2df0d2962725a26a1d8c438888f7e70946943589
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in AffineOps.cpp (NFC)
/llvm-project/mlir/lib/Dialect/Affine/IR/AffineOps.cpp:4590:25:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare]
if (dynamicBasisIndex == dynamicBasis.size())
~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
1 error generated.
Commit: 96dd39c575be64896995e08881b9bc27688ce5d1
https://github.com/llvm/llvm-project/commit/96dd39c575be64896995e08881b9bc27688ce5d1
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M compiler-rt/lib/xray/weak_symbols.txt
M compiler-rt/lib/xray/xray_flags.cpp
M compiler-rt/lib/xray/xray_flags.h
A compiler-rt/test/xray/TestCases/Posix/default-options.cpp
M llvm/docs/XRay.rst
Log Message:
-----------
[XRay] Add `__xray_default_options` to specify build-time defined options (#117921)
Similar to `__asan_default_options`, users can specify default options
upon building the instrumented binaries by providing their own
definition of `__xray_default_options` which returns the option strings.
This is useful in cases where setting the `XRAY_OPTIONS` environment
variable might be difficult. Plus, it's a convenient way to populate
XRay options when you always want the instrumentation to be enabled.
Commit: 3b43276575fc939b4f6e8089277fac083c770990
https://github.com/llvm/llvm-project/commit/3b43276575fc939b4f6e8089277fac083c770990
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
Log Message:
-----------
[ORC] Remove some SymbolStringPtr copies.
Commit: e034c4ef7b52635bb9cc78b6d3f97a4af5002f92
https://github.com/llvm/llvm-project/commit/e034c4ef7b52635bb9cc78b6d3f97a4af5002f92
Author: vabridgers <58314289+vabridgers at users.noreply.github.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/ChrootChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/chroot.c
M clang/test/Analysis/show-checker-list.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[analyzer] Modernize, improve and promote chroot checker (#117791)
This change modernizes, improves and promotes the chroot checker from
alpha to the Unix family of checkers. This checker covers the POS05
recommendations for use of chroot.
The improvements included modeling of a success or failure from chroot
and not falsely reporting a warning along an error path. This was made
possible through modernizing the checker to be flow sensitive.
---------
Co-authored-by: einvbri <vince.a.bridgers at ericsson.com>
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: 91285e26bf67179a6804c931203c93f07c08183d
https://github.com/llvm/llvm-project/commit/91285e26bf67179a6804c931203c93f07c08183d
Author: Clement Courbet <courbet at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
A clang-tools-extra/test/clang-reorder-fields/FieldAnnotationsInMacros.cpp
Log Message:
-----------
[clang-reorder-fields] Handle macros fields declarations. (#118005)
Right now fields with macro declarations break the tool:
```
struct Foo {
Mutex mu;
int x GUARDED_BY(mu);
int y;
};
```
reordered by mu,y,x yields:
```
struct Foo {
Mutex mu;
int y GUARDED_BY(mu);
int x;
};
```
Commit: d7791f51cecbaaa81a65e4a16d781fbf338f9272
https://github.com/llvm/llvm-project/commit/d7791f51cecbaaa81a65e4a16d781fbf338f9272
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
Log Message:
-----------
[llvm-debuginfo-analyzer] Remove superfluous link components. (#118052)
As 'LLVM_TARGETS_TO_BUILD' control which targets are enabled, the lines:
AllTargetsDescs
AllTargetsDisassemblers
AllTargetsInfos
are redundant.
Commit: aa9d36869090fdff8cd416c83a5106a1b45b0ff7
https://github.com/llvm/llvm-project/commit/aa9d36869090fdff8cd416c83a5106a1b45b0ff7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
Log Message:
-----------
[mlir][linalg] Relax scalable vectorization restrictions (#117991)
Currently, the Linalg vectorizer disallows non-trailing parallel
dimensions to be scalable, e.g., `vector_sizes [[8], 1]` (*), for cases
like:
```mlir
%0 = linalg.fill ins(%arg0 : f32) outs(%A : tensor<?x?xf32>) -> tensor<?x?xf32>
```
This restriction exists to avoid generating "scalable" arrays of
aggregates, which LLVM does not support (multi-dim vectors are lowered
into arrays of aggregates at the LLVM level).
This patch relaxes that restriction when the trailing parallel vector
dimension is `1`, e.g., for `vector_sizes [[8], 1]`. Such cases are safe
since trailing unit dimensions can be collapsed. This relaxation is
necessary to support scalable vectorization for tensor.pack, where inner
tile sizes are `[8]` (scalable) and `1` (scalar).
(*) Transform Dialect notation
Commit: a943922c0de52efb78e84e08dbc5d74f428b2377
https://github.com/llvm/llvm-project/commit/a943922c0de52efb78e84e08dbc5d74f428b2377
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Remove duplicate instruction `FF 25 ...`. (#116894)
It appears already some lines above with this comment:
"Cannot overwrite control-instruction. Return 0 to indicate failure.".
Replacing just the comment in the first appearance.
Found after creating the test in #113085.
Commit: 9b2ec87f5bce57cc900cf52a99f805d999716053
https://github.com/llvm/llvm-project/commit/9b2ec87f5bce57cc900cf52a99f805d999716053
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/iterator-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling-aggressive-std-find-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling.cpp
M clang/test/Analysis/template-param-objects.cpp
Log Message:
-----------
[analyzer] Avoid creating LazyCompoundVal when possible (#116840)
In #115916 I allowed copying empty structs.
Later in #115917 I changed how objects are copied, and basically when we
would want to copy a struct (an LCV) of a single symbol (likely coming
from an opaque fncall or invalidation), just directly bind that symbol
instead of creating an LCV referring to the symbol. This was an
optimization to skip a layer of indirection.
Now, it turns out I should have apply the same logic in #115916. I
should not have just blindly created an LCV by calling
`createLazyBinding()`, but rather check if I can apply the shortcut
described in #115917 and only create the LCV if the shortcut doesn't
apply.
In this patch I check if there is a single default binding that the copy
would refer to and if so, just return that symbol instead of creating an
LCV.
There shouldn't be any observable changes besides that we should have
fewer LCVs. This change may surface bugs in checkers that were
associating some metadata with entities in a wrong way. Notably,
STLAlgorithmModeling and DebugIteratorModeling checkers would likely
stop working after this change.
I didn't investigate them deeply because they were broken even prior to
this patch. Let me know if I should migrate these checkers to be just as
bugged as they were prior to this patch - thus make the tests pass.
Commit: 352f8688d0ca250c9e8774321f6c3bcd4298cc09
https://github.com/llvm/llvm-project/commit/352f8688d0ca250c9e8774321f6c3bcd4298cc09
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaAttr.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
Log Message:
-----------
[clang] Fix incorrect inferred lifetime_capture_by attr on STL (#118013)
We incorrectly annotate the iterator parameter for `insert` method
(`void insert(const_iterator, const value_type& value)`), because
iterator is also a gsl-pointer type.
This patch fixes it.
Commit: 27e01ee5aafb79a8aeca5fc9eb41e7f1243a7a46
https://github.com/llvm/llvm-project/commit/27e01ee5aafb79a8aeca5fc9eb41e7f1243a7a46
Author: Dmitry Sidorov <dmitry.sidorov at intel.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
Log Message:
-----------
[SPIR-V][NFC] Fix number of operands for cooperative matrix instructions (#118014)
This PR fixes number of operands of SPIR-V wrapper builtins for
cooperative matrix instructions.
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov at intel.com>
Commit: 26baa00908b2eb8b2925800af6bc64fbe53cac48
https://github.com/llvm/llvm-project/commit/26baa00908b2eb8b2925800af6bc64fbe53cac48
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/AST/ByteCode/records.cpp
A clang/test/SemaCXX/cxx20-warn-dangling-paren-list-agg-init.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
Log Message:
-----------
[clang] Diagnose dangling references for parenthesized aggregate initialization. (#117690)
Unlike brace initialization, the parenthesized aggregate initialization
in C++20 does not extend the lifetime of a temporary object bound to a
reference in an aggreate. This can lead to dangling references:
```
struct A { const int& r; };
A a1(1); // well-formed, but results in a dangling reference.
```
With this patch, clang will diagnose this common dangling issues.
Fixes #101957
Commit: e9be21786c972de93206599d4e06b79c2ca8f772
https://github.com/llvm/llvm-project/commit/e9be21786c972de93206599d4e06b79c2ca8f772
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/cmake/modules/GetHostTriple.cmake
Log Message:
-----------
[CMake] Handle clang in MSVC mode in GetHostTriple (#116701)
When configuring CMake with Clang in MSVC mode, Clang can either be
invoked with the MSVC style driver (clang-cl) or the GNU style driver
(clang). When using the MSVC style driver, CMake sets the CMake variable
MSVC (which indicates the kind of command line interface), but when
using the GNU style driver, this variable isn't set, while Clang still
operates in MSVC mode.
Even though CMake doesn't set the variable MSVC, it still does set
CMAKE_C_COMPILER_ARCHITECTURE_ID, which it does set for MSVC and Clang
in MSVC mode, but not for Clang in MinGW mode.
For this configuration, use the MSVC style,
CMAKE_C_COMPILER_ARCHITECTURE_ID based GetHostTriple implementation.
Commit: ed7f36e1ecc26d6360126fc6ed0514b592fcc029
https://github.com/llvm/llvm-project/commit/ed7f36e1ecc26d6360126fc6ed0514b592fcc029
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] update a couple of struct/vector creation examples to use poison
Commit: a174aa1e416c4e27945f5a8c646b119126dc8441
https://github.com/llvm/llvm-project/commit/a174aa1e416c4e27945f5a8c646b119126dc8441
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
Log Message:
-----------
[clang-repl] Fix generation of wasm binaries while running clang-repl in browser (#117978)
Co-authored-by: Vassil Vassilev <v.g.vassilev at gmail.com>
Commit: cb4f22c0a737b13c06f54566dac1e40cc4ec06c8
https://github.com/llvm/llvm-project/commit/cb4f22c0a737b13c06f54566dac1e40cc4ec06c8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Adjust triple on test case for #114360
An attempt to fix a buildbot failure on clang-x64-windows-msvc
Commit: 26ffca08439f23e8db43beeb021c4cae32716822
https://github.com/llvm/llvm-project/commit/26ffca08439f23e8db43beeb021c4cae32716822
Author: lonely eagle <2020382038 at qq.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/test/Dialect/Affine/ops.mlir
Log Message:
-----------
[mlir][gpu]add AffineScope to gpu.func op. (#118010)
This PR in order to solve the following problem.
https://github.com/llvm/llvm-project/pull/117721.
To efficiently implement the thread-to-data mapping relationship, I
introduced AffineScope in gpu.func(Data or thread layout).
Commit: 9c97aa5abb6aa4ce4055095a89ae7d72e1b61803
https://github.com/llvm/llvm-project/commit/9c97aa5abb6aa4ce4055095a89ae7d72e1b61803
Author: Richard Dzenis <richard at dzenis.dev>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
A llvm/test/tools/llvm-objcopy/MachO/dysymtab-zero-indirectsym.test
Log Message:
-----------
[llvm-objcopy] Always update indirectsymoff in MachO (#117726)
Let's say we've run llvm-strip over some MachO. The resulting MachO
became smaller and there are no indirect symbols anymore.
Then according to previous code we would not update indirectsymoff
field. This would lead to `MachOWriter::totalSize()` report size that is
larger than the new MachO. As a result we would get MachO that has zero
bytes past contents of the very last load command.
Codesign has a strict check that size of MachO file must be equal to
lastLoadCommand.offset + lastLoadCommand.size
If this is not satisfied codesign reports the following error
main executable failed strict validation
Fixes #117723
Commit: 7ed36b9ec6147fbada27592292bca28f9f76c983
https://github.com/llvm/llvm-project/commit/7ed36b9ec6147fbada27592292bca28f9f76c983
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Add missing REQUIRES to test case for #114360
Commit: 0d1d1b363d9588c192152cec4f256f3edfea7e48
https://github.com/llvm/llvm-project/commit/0d1d1b363d9588c192152cec4f256f3edfea7e48
Author: itrofimow <i.trofimow at yandex.ru>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
Log Message:
-----------
[DebugInfo] Clean up LLVMSymbolizer::DemangleName API: const string& -> StringRef (#118056)
Commit: b68340c83529bd8d13d1c4441777baa31863d1cf
https://github.com/llvm/llvm-project/commit/b68340c83529bd8d13d1c4441777baa31863d1cf
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A llvm/include/llvm/CodeGen/SpillPlacement.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/SpillPlacement.cpp
R llvm/lib/CodeGen/SpillPlacement.h
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port SpillPlacement analysis to NPM (#116618)
Commit: 8dd0da5bd1c427a7ba2091b918c59b3ee7a8b79f
https://github.com/llvm/llvm-project/commit/8dd0da5bd1c427a7ba2091b918c59b3ee7a8b79f
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Log Message:
-----------
[AArch64] Silence warning with different types in ternary. NFC
This just casts the Register to an unsigned, to fit in with the other types
returned from the function.
Commit: 5540eac4e5161d124ac547e4a9d3451408bb71e9
https://github.com/llvm/llvm-project/commit/5540eac4e5161d124ac547e4a9d3451408bb71e9
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable `from_elements` for scalable vectors (#117868)
Disables `vector.from_elements` for scalable vectors. Given that the
length of scalable vectors is unknown at compile time, the semantics of
this Op are unclear in this context.
Commit: 044362215d5264280abc807ea1da6c652530c926
https://github.com/llvm/llvm-project/commit/044362215d5264280abc807ea1da6c652530c926
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/mmx-cvt.ll
Log Message:
-----------
[X86] Add test for new _mm_movpi64_epi64 lowering
With the MMX retirement, _mm_movpi64_epi64 now lowers to shuffle((__m64)(double)x,(__m64)0) pattern - which demonstrates a unnecessary FPU->GPU->FPU transfer
Commit: 1784275e43976df2388a27805fb684def76c5c8a
https://github.com/llvm/llvm-project/commit/1784275e43976df2388a27805fb684def76c5c8a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-masked.ll
Log Message:
-----------
[X86] vector-shuffle-masked.ll - update extract_subvector shuffle tests to take poison arg instead of undef
Commit: 568ae0afabe07837ecfae8f8fe9dacf0de74a1e5
https://github.com/llvm/llvm-project/commit/568ae0afabe07837ecfae8f8fe9dacf0de74a1e5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
Log Message:
-----------
[X86] widen_shuffle-1.ll - update shuffle tests to take poison arg instead of undef
Commit: e04d7549cca3b82fb0f71d2b073fa88654ae2212
https://github.com/llvm/llvm-project/commit/e04d7549cca3b82fb0f71d2b073fa88654ae2212
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[llvm][docs] Link to correct maintainers file for clang-tools-extra
5eeb3fef61bf5542c3fdcb71622fc4e826527789 moved it from CODE_OWNERS.txt.
Commit: 59f57be94f38758616b1339b293b43af845571af
https://github.com/llvm/llvm-project/commit/59f57be94f38758616b1339b293b43af845571af
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
Revert "[libc++] Simplify the implementation of reserve() and shrink_to_fit() (#113453)"
This reverts commit d648eed5899c4be10f1f7866eebef2bc171e673f. Breaks
anything that relies on sized deallocation, e.g. asan and tcmalloc.
Commit: 55dd475d1d89db5cd23534a4d9b200854410703d
https://github.com/llvm/llvm-project/commit/55dd475d1d89db5cd23534a4d9b200854410703d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/mmx-cvt.ll
Log Message:
-----------
[X86] Fold (v2i64 (scalar_to_vector (i64 (bitcast (double))))) -> (bitcast (v2f64 scalar_to_vector))
This can occur more frequently after the MMX retirement if anyone is still using MMX intrinsics that now wrap to SSE
Commit: baaf1115ca007f95fd08c52dc8bec54d310f5b27
https://github.com/llvm/llvm-project/commit/baaf1115ca007f95fd08c52dc8bec54d310f5b27
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/unittests/ADT/BitmaskEnumTest.cpp
Log Message:
-----------
[BitmaskEnum] Add support for shift operators. (#118007)
For enums that describe a bitmask where successive bits within that mask
describe some enum value (as described in the same enum), it is useful
to support operator<< and operator>> as well.
For example:
```
enum class E : unsigned {
// 2 bits per option
OptionA = 0,
OptionB = 1,
OptionC = 2,
OptionD = 3,
OptionMask = 3,
// Given 3 values in the bitmask X, Y and Z, each is 2 bits in size
// and represents a choice of OptionA..OptionD.
ShiftX = 0,
ShiftY = 2,
ShiftZ = 4,
};
// The mask can be encoded with:
E mask;
mask |= getOptionFor(X) << E::ShiftX;
mask |= getOptionFor(Y) << E::ShiftY;
mask |= getOptionFor(Z) << E::ShiftZ;
// And to extract a value:
E OptionForX = (mask >> E::ShiftX) & E::OptionMask;
E OptionForY = (mask >> E::ShiftY) & E::OptionMask;
E OptionForZ = (mask >> E::ShiftZ) & E::OptionMask;
```
Commit: 9300274a12d758368c036812d903b73d70d64ea4
https://github.com/llvm/llvm-project/commit/9300274a12d758368c036812d903b73d70d64ea4
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqcicsr-invalid.s
M llvm/test/MC/RISCV/xqcicsr-valid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xqcisls-valid.s
Log Message:
-----------
[RISCV][NFCI] Fix Xqci Line Endings
Changes the new files for `Xqci`, including `Xqcicsr` and `Xqcisls`, to
use Unix line endings rather than Windows line endings.
Commit: bbea1dee28f4bd7cfa897a79e38c5331fca5d796
https://github.com/llvm/llvm-project/commit/bbea1dee28f4bd7cfa897a79e38c5331fca5d796
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
Log Message:
-----------
[X86][FP16] Fix masking problem of VF[,C]MADDCSH intrinsics (#118071)
Fixes: #98306
Commit: 6f4b4f41ca41d7d0b44a32d9968aef7667c68184
https://github.com/llvm/llvm-project/commit/6f4b4f41ca41d7d0b44a32d9968aef7667c68184
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
R llvm/test/Transforms/LoopVectorize/AArch64/scatter-cost.ll
Log Message:
-----------
[AArch64] Remove LoopVectorizer/AArch64/scatter-cost.ll test. NFC
This test checks the costs, not vectorization, so is better placed in the
existing gather/scatter cost modelling tests. An extra neoverse-v2 check line
has been added for both gathers and scatters.
Commit: f4974e09312afc9549fcfc0304b738d235da9eca
https://github.com/llvm/llvm-project/commit/f4974e09312afc9549fcfc0304b738d235da9eca
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/ashr-node-with-poison.ll
Log Message:
-----------
[SLP] Add a check for poison value in AShrChecker
Need to check if the value in AShrChecker is a poison before casting it
to instruction to avoid compiler crash
Fixes #118030
Commit: 2b3266c1701f315d7e89c81977800001563afacb
https://github.com/llvm/llvm-project/commit/2b3266c1701f315d7e89c81977800001563afacb
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
Log Message:
-----------
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11) (#116259)
SVE2.2 introduces instructions with predicated forms with zeroing of the
inactive lanes. This allows in some cases to save a `movprfx` or a `mov`
instruction when emitting code for `_x` or `_z` variants of intrinsics.
This patch adds support for emitting the zeroing forms of `ABS`, `NEG`,
`FABS`, and `FNEG` instructions.
Commit: e973f7ae52e753ebe53f5414ddf1c4d29e49deb5
https://github.com/llvm/llvm-project/commit/e973f7ae52e753ebe53f5414ddf1c4d29e49deb5
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV][Xqcicsr] Instructions have Side Effects (#118089)
Xqcicsr was added in #117169. I missed that `hasSideEffects` was set to
0, rather than 1 (which all other CSR-modifying instructions have).
This has no effect on the current assembly-only support, but I think is
worth fixing before I forget. I accidentally fixed the closing comment
in 9300274a12d758368c036812d903b73d70d64ea4.
Commit: ef86a31a593a023946a2dc805948360efdad3930
https://github.com/llvm/llvm-project/commit/ef86a31a593a023946a2dc805948360efdad3930
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/cmake/modules/GetHostTriple.cmake
Log Message:
-----------
[CMake] Fix mismatched endif warning
Caused by https://github.com/llvm/llvm-project/pull/116701.
Seems like a lot of arguments to repeat, so just use a plain endif().
Commit: 2a18162daa96e1cca5144a634bb03134405b52cb
https://github.com/llvm/llvm-project/commit/2a18162daa96e1cca5144a634bb03134405b52cb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
Log Message:
-----------
[X86] update shuffle lowering tests to take poison arg instead of undef
Commit: 5c181a9191bfb758575329ff7eb8db4fc46ffac9
https://github.com/llvm/llvm-project/commit/5c181a9191bfb758575329ff7eb8db4fc46ffac9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
Log Message:
-----------
[X86] update vector shift lowering tests to take poison arg instead of undef
Commit: 38098b486e44ad077b674e512eee399fc6f5a30c
https://github.com/llvm/llvm-project/commit/38098b486e44ad077b674e512eee399fc6f5a30c
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable CompressStoreOp/ExpandLoadOp for scalable vectors (#117538)
These operations were introduced as counterparts to the following LLVM
intrinsics:
* `@llvm.masked.expandload.*`,
* `@llvm.masked.compressstore.*`.
Currently, there is minimal test coverage for scalable vector use cases
involving these Ops (both LLVM and MLIR). Additionally, the verifier is
flawed - it incorrectly allows mixing fixed-width and scalable vectors.
To address these issues, scalable vector support for these Ops is being
disabled for now. This decision can be revisited if a clear need arises
for their use with scalable vectors in the future.
Commit: b40714b01206abef4130d3a39a90ac82aa96f18f
https://github.com/llvm/llvm-project/commit/b40714b01206abef4130d3a39a90ac82aa96f18f
Author: Tyler Nowicki <tyler.nowicki at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A llvm/lib/Transforms/Coroutines/CoroCloner.h
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Log Message:
-----------
[Coroutines][NFC] Refactor CoroCloner (#116885)
* Move CoroCloner to its own header. For now, the header is located in llvm/lib/Transforms/Coroutines
* Change private to protected to allow inheritance
* Create CoroSwitchCloner and move some of the switch specific code into this cloner. More code will follow in later commits.
Commit: ef50d790c276600da609b465259a8e636e3531bc
https://github.com/llvm/llvm-project/commit/ef50d790c276600da609b465259a8e636e3531bc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libcxx/utils/ci/run-buildbot-container
Log Message:
-----------
[libc++] Update run-buildbot-container with up-to-date image information
Commit: 31b7d4333a6c10aa8b7e1a7ca5aa0e281f124ec2
https://github.com/llvm/llvm-project/commit/31b7d4333a6c10aa8b7e1a7ca5aa0e281f124ec2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
M llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll
M llvm/test/CodeGen/X86/load-partial.ll
Log Message:
-----------
[DAG] Extend extract_element(bitcast(scalar_to_vector(X))) -> trunc(srl(X,C)) (#117900)
When extracting a smaller integer from a scalar_to_vector source, we were limited to only folding/truncating the lowest bits of the scalar source.
This patch extends the fold to handle extraction of any other element, by right shifting the source before truncation.
Fixes a regression from #117884
Commit: fe042904829b83a61c1f4bc904f8f9e5b6da891e
https://github.com/llvm/llvm-project/commit/fe042904829b83a61c1f4bc904f8f9e5b6da891e
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
Log Message:
-----------
[AArch64] Change the default vscale-for-tuning to 1. (#117174)
Most AArch64 cpus outside of Neoverse V1 (256) and A64FX (512) have an
SVE vector length of 128, and in environments like Android (where no
mcpu option is common) we would expect all cpus to match. This patch
changes the default vector length to 128 with -mcpu=generic, to match
the most common case.
Commit: 8fb748b4a7c45b56c2e4f37c327fd88958ab3758
https://github.com/llvm/llvm-project/commit/8fb748b4a7c45b56c2e4f37c327fd88958ab3758
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/InlineCost.h
M llvm/lib/Analysis/InlineCost.cpp
A llvm/test/Transforms/Inline/AArch64/memcpy-constant-size.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/memcpy-constant-size.ll
Log Message:
-----------
[Inliner] Don't count a call penalty for foldable __memcpy_chk and similar (#117876)
When the size is an appropriate constant, __memcpy_chk will turn into a
memcpy that gets folded away by InstCombine. Therefore this patch avoids
counting these as calls for purposes of inlining costs.
This is only really relevant on platforms whose headers redirect memcpy
to __memcpy_chk (such as Darwin). On platforms that use intrinsics,
memcpy and similar functions are already exempt from call penalties.
Commit: 77c2b005539c4b0c0e2b7edeefd5f57b95019bc9
https://github.com/llvm/llvm-project/commit/77c2b005539c4b0c0e2b7edeefd5f57b95019bc9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A .ci/metrics/Dockerfile
A .ci/metrics/metrics.py
A .ci/metrics/requirements.lock.txt
A .ci/metrics/requirements.txt
Log Message:
-----------
[CI] Upstream metrics script and container definition (#117461)
This patch includes the script that pulls information from Github and
pushes it to Grafana. This is currently running in the cluster and
pushes information to
https://llvm.grafana.net/public-dashboards/6a1c1969b6794e0a8ee5d494c72ce2cd.
This script is designed to accept other jobs relatively easily and can
be easily modified to look at other metrics.
Commit: be75a14207ab0dac6ad9f9097957f14a918ac611
https://github.com/llvm/llvm-project/commit/be75a14207ab0dac6ad9f9097957f14a918ac611
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateDeduction.cpp
A clang/test/SemaTemplate/template-args-deduction-aggregates.cpp
Log Message:
-----------
[Clang] fix crash due to incorrect argument position in merging deduced template arguments (#118041)
Fixes #113659
Commit: 9ebab700cde7e47bd7b6c3386529262369e8fa2c
https://github.com/llvm/llvm-project/commit/9ebab700cde7e47bd7b6c3386529262369e8fa2c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A .github/workflows/build-metrics-container.yml
Log Message:
-----------
[Github] Add new workflow to build metrics container (#117462)
This patch adds a new Github Actions workflow to build the metrics
container and push it to the Github Container Registry.
Commit: 820403c4e04db1f4adc8528bec33d393a5be3856
https://github.com/llvm/llvm-project/commit/820403c4e04db1f4adc8528bec33d393a5be3856
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/test/Analysis/initializer.cpp
Log Message:
-----------
[analyzer] Never create Regions wrapping reference TypedValueRegions (NFCI) (#118096)
Like in the test case:
```c++
struct String {
String(const String &) {}
};
struct MatchComponent {
unsigned numbers[2];
String prerelease;
MatchComponent(MatchComponent const &) = default;
};
MatchComponent get();
void consume(MatchComponent const &);
MatchComponent parseMatchComponent() {
MatchComponent component = get();
component.numbers[0] = 10;
component.numbers[1] = 20;
return component; // We should have no stack addr escape warning here.
}
void top() {
consume(parseMatchComponent());
}
```
When calling `consume(parseMatchComponent())` the
`parseMatchComponent()` would return a copy of a temporary of
`component`. That copy would invoke the
`MatchComponent::MatchComponent(const MatchComponent &)` ctor.
That ctor would have a (reference typed) ParamVarRegion, holding the
location (lvalue) of the object we are about to copy (&component). So
far so good, but just before evaluating the binding operation for
initializing the `numbers` field of the temporary, we evaluate the
ArrayInitLoopExpr representing the by-value elementwise copy of the
array `component.numbers`. This is represented by a LazyCompoundVal,
because we (usually) don't just copy large arrays and bind many
individual direct bindings. Rather, we take a snapshot by using a LCV.
However, notice that the LCV representing this copy would look like
this:
lazyCompoundVal{ParamVarRegion{"reference param of cctor"}.numbers}
Notice that it refers to the numbers field of a reference. It would be
much better to desugar the reference to the actual object, thus it
should be: `lazyCompoundVal{component.numbers}`
Actually, when binding the result of the ArrayInitLoopExpr to the
`temp_object.numbers` in the compiler-generated member initializer of
the cctor, we should have two individual direct bindings because this is
a "small array":
```
binding &Element{temp_object.numbers, 0} <- loadFrom(&Element{component.numbers, 0})
binding &Element{temp_object.numbers, 1} <- loadFrom(&Element{component.numbers, 1})
```
Where `loadFrom(...)` would be:
```
loadFrom(&Element{component.numbers, 0}): 10 U32b
loadFrom(&Element{component.numbers, 1}): 20 U32b
```
So the store should look like this, after PostInitializer of
`temp_object.numbers`:
```
temp_object at offset 0: 10 U32b
temp_object at offset 32: 20 U32b
```
The lesson is that it's okay to have TypedValueRegions of references as
long as we don't form subregions of those. If we ever want to refer to a
subregion of a "reference" we actually meant to "desugar" the reference
and slice a subregion of the pointee of the reference instead.
Once this canonicalization is in place, we can also drop the special
handling of references in `ProcessInitializer`, because now reference
TypedValueRegions are eagerly desugared into their referee region when
forming a subregion of it.
There should be no practical differences, but there are of course bugs
that this patch may surface.
Commit: b5132b7d044a5bc83eba9b09bd158cd77a511403
https://github.com/llvm/llvm-project/commit/b5132b7d044a5bc83eba9b09bd158cd77a511403
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVDuplicatesTracker.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
M llvm/test/CodeGen/SPIRV/instructions/ret-type.ll
A llvm/test/CodeGen/SPIRV/pointers/builtin-ret-reg-type.ll
A llvm/test/CodeGen/SPIRV/pointers/gep-types-1.ll
A llvm/test/CodeGen/SPIRV/pointers/gep-types-2.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-via-store-load-args-rev.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
A llvm/test/CodeGen/SPIRV/validate/sycl-hier-par-basic.ll
Log Message:
-----------
[SPIR-V] Improve type inference: fix types of return values in call lowering (#116609)
Goals of the PR are:
* to ensure that correct types are applied to virtual registers which
were used as return values in call lowering. A reproducer is attached as
a new test case, before the PR it fails because spirv-val considers
output invalid due to wrong result/operand types in OpPhi's;
* improve type inference by speeding up postprocessing of types: by
limiting iterations by checking what remains to process, and processing
each instruction just once for any number of operands with uncomplete
types;
* improve type inference by more accurate work with uncomplete types
(pass uncomplete property to dependent operands, ensure consistency of
uncomplete-types data structure);
* change processing order and add traversing of PHI nodes when type
inference apply instructions results to specify/update/cast operands
type (fixes an issue with OpPhi's result type mismatch with operand
types).
Commit: 2de2e7aa6f82ac283bc17945ca9750c01016a331
https://github.com/llvm/llvm-project/commit/2de2e7aa6f82ac283bc17945ca9750c01016a331
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M .github/workflows/build-metrics-container.yml
Log Message:
-----------
[Github] Fix build metrics container push (#118130)
This patch fixes a couple typos that were preventing the build metrics
container job from pushing the container to GHCR.
Commit: cbf495fd12ba08c3a8e10dbcd482df1bf80736ed
https://github.com/llvm/llvm-project/commit/cbf495fd12ba08c3a8e10dbcd482df1bf80736ed
Author: Reno Dakota <paparodeo at proton.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/unsupported-option.c
Log Message:
-----------
[Clang][Driver] report unsupported option error when link + compile in same process (#116476)
Fixes: https://github.com/llvm/llvm-project/issues/116278
This change updates clang to report unsupported option errors regardless
of the command line argument order.
When clang is invoked with a source file and without `-c` it will both
compile and link. When an unsupported option is also part of the command
line clang should generated an error. However, if the source file name
comes before an object file, eg: `-lc`, the error is ignored.
```
$ clang --target=x86_64 -lc hello.c -mhtm
clang: error: unsupported option '-mhtm' for target 'x86_64'
$ echo $?
1
```
but if `-lc` comes after `hello.c` the error is dropped
```
$ clang --target=x86_64 hello.c -mhtm -lc
$ echo $?
0
```
after this change clang will report the error regardless of the command
line argument order.
Commit: 0ad6be1927f89cef09aa5d0fb244873f687997c9
https://github.com/llvm/llvm-project/commit/0ad6be1927f89cef09aa5d0fb244873f687997c9
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
Log Message:
-----------
[SLPVectorizer, TargetTransformInfo, SystemZ] Improve SLP getGatherCost(). (#112491)
As vector element loads are free on SystemZ, this patch improves the cost
computation in getGatherCost() to reflect this.
getScalarizationOverhead() gets an optional parameter which can hold the actual
Values so that they in turn can be passed (by BasicTTIImpl) to
getVectorInstrCost().
SystemZTTIImpl::getVectorInstrCost() will now recognize a LoadInst and
typically return a 0 cost for it, with some exceptions.
Commit: 6bfb6d4092a284e1fcd135625c0e713d019f0572
https://github.com/llvm/llvm-project/commit/6bfb6d4092a284e1fcd135625c0e713d019f0572
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallPtrSet.h
Log Message:
-----------
[SmallPtrSet] Optimize contains (NFC) (#118092)
Instead of going through find_imp(), implement a specialized
contains_imp() that directly returns a boolean instead of a pointer that
needs to be compared to EndPointer().
This gives a compile-time improvement of around 0.2-0.3%.
Commit: 05ff6e7948df3c152982814ea2367c7b83138cea
https://github.com/llvm/llvm-project/commit/05ff6e7948df3c152982814ea2367c7b83138cea
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/Symbols.cpp
M lld/test/ELF/invalid-eh-frame3.s
M lld/test/ELF/invalid-eh-frame6.s
M lld/test/ELF/tls.s
M lld/test/ELF/undef-multi.s
M lld/test/ELF/undef.s
Log Message:
-----------
[ELF] Use lower case offset in getObjMsg
to improve consistency with other diagnostics. While here, migrate to
use ELFSyncStream to drop toStr/getCtx uses and avoid string overhead.
Commit: ae9b91acc76e03a3c38e2f92b59308c508901817
https://github.com/llvm/llvm-project/commit/ae9b91acc76e03a3c38e2f92b59308c508901817
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
Log Message:
-----------
[libc++] Fix malformed CSV entry for C++26 LWG issue
Commit: 2dc0de753b6df83e35f3d98e0e6a26c95e3399c0
https://github.com/llvm/llvm-project/commit/2dc0de753b6df83e35f3d98e0e6a26c95e3399c0
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
Log Message:
-----------
[clang] recognize hexagon-*-ld.lld variants (#117338)
If we create a cross toolchain with a ${triple}-ld.lld symlink, clang
finds that symlink and when it uses it, it's not recognized as "lld".
Let's resolve that symlink and consider it when determining lld-ness.
For example, clang provides hexagon-link specific link arguments such as
`-mcpu=hexagonv65` and `-march=hexagon` when
hexagon-unknown-linux-musl-ld.lld is found. lld rejects this with the
following error:
hexagon-unknown-linux-musl-ld.lld: error: unknown emulation:
cpu=hexagonv65
Commit: 52690db47da36a739ee506d3b3a7457fb918dc1e
https://github.com/llvm/llvm-project/commit/52690db47da36a739ee506d3b3a7457fb918dc1e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[clang] Fix -Wdangling false negative regressions caused by 117315 (#118088)
A specialization declaration can have an attribute even if the primary
template does not, particularly when the specialization is instantiated
from an annotated using-alias declaration.
Fix #118064
Commit: 8ac2b77a11c9db9879557ce1c26e38628e1ef45f
https://github.com/llvm/llvm-project/commit/8ac2b77a11c9db9879557ce1c26e38628e1ef45f
Author: vabridgers <58314289+vabridgers at users.noreply.github.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/BranchCloneCheck.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/redundant-expression.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/alpha-core-identicalexpr.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
R clang/lib/StaticAnalyzer/Checkers/IdenticalExprChecker.cpp
R clang/test/Analysis/identical-expressions.cpp
Log Message:
-----------
[analyzer] Remove alpha.core.IdenticalExpr Checker (#114715)
This change removes the alpha.core.IdenticalExpr static analysis checker
since it's checks are present in the clang-tidy checks
misc-redundant-expression and bugprone-branch-clone. This check was
implemented as a static analysis check using AST matching, and since
alpha and duplicated in 2 clang-tidy checks may be removed.
Co-authored-by: Vince Bridgers <vince.a.bridgers at ericsson.com>
Commit: 666de79595dc2460b7abca0b99d79d058c10cadf
https://github.com/llvm/llvm-project/commit/666de79595dc2460b7abca0b99d79d058c10cadf
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
Log Message:
-----------
[ELF] Move some ObjFile members to ELFFileBase to simplify getSrcMsg
Commit: f28e071dc075fd5591344bc5aabd7b298aaecf50
https://github.com/llvm/llvm-project/commit/f28e071dc075fd5591344bc5aabd7b298aaecf50
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
Log Message:
-----------
[rtsan] NFC: Fix style of some interceptors not using MAYBE (#118145)
There were a few interceptors that weren't using the newer MAYBE style -
fixed them up for uniform style.
Commit: b22cc5a650deb729f4a1f18206e14971616d07ee
https://github.com/llvm/llvm-project/commit/b22cc5a650deb729f4a1f18206e14971616d07ee
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port 8ac2b77a11c9
Commit: 9df63b2651b2435c02a7d825953ca2ddc65c778e
https://github.com/llvm/llvm-project/commit/9df63b2651b2435c02a7d825953ca2ddc65c778e
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/lib/Dialect/Func/Transforms/FuncConversions.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/decompose-call-graph-types.mlir
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][Transforms] Add 1:N `matchAndRewrite` overload (#116470)
This commit adds a new `matchAndRewrite` overload to `ConversionPattern`
to support 1:N replacements. This is the first of two main PRs that
merge the 1:1 and 1:N dialect conversion drivers.
The existing `matchAndRewrite` function supports only 1:1 replacements,
as can be seen from the `ArrayRef<Value>` parameter.
```c++
LogicalResult ConversionPattern::matchAndRewrite(
Operation *op, ArrayRef<Value> operands /*adaptor values*/,
ConversionPatternRewriter &rewriter) const;
```
This commit adds a `matchAndRewrite` overload that is called by the
dialect conversion driver. By default, this new overload dispatches to
the original 1:1 `matchAndRewrite` implementation. Existing
`ConversionPattern`s do not need to be changed as long as there are no
1:N type conversions or value replacements.
```c++
LogicalResult ConversionPattern::matchAndRewrite(
Operation *op, ArrayRef<ValueRange> operands /*adaptor values*/,
ConversionPatternRewriter &rewriter) const {
// Note: getOneToOneAdaptorOperands produces a fatal error if at least one
// ValueRange has 0 or more than 1 value.
return matchAndRewrite(op, getOneToOneAdaptorOperands(operands), rewriter);
}
```
The `ConversionValueMapping`, which keeps track of value replacements
and materializations, still does not support 1:N replacements. We still
rely on argument materializations to convert N replacement values back
into a single value. The `ConversionValueMapping` will be generalized to
1:N mappings in the second main PR.
Before handing the adaptor values to a `ConversionPattern`, all argument
materializations are "unpacked". The `ConversionPattern` receives N
replacement values and does not see any argument materializations. This
implementation strategy allows us to use the 1:N infrastructure/API in
`ConversionPattern`s even though some functionality is still missing in
the driver. This strategy was chosen to keep the sizes of the PRs
smaller and to make it easier for downstream users to adapt to API
changes.
This commit also updates the the "decompose call graphs" transformation
and the "sparse tensor codegen" transformation to use the new 1:N
`ConversionPattern` API.
Note for LLVM conversion: If you are using a type converter with 1:N
type conversion rules or if your patterns are performing 1:N
replacements (via `replaceOpWithMultiple` or
`applySignatureConversion`), conversion pattern applications will start
failing (fatal LLVM error) with this error message: `pattern 'name' does
not support 1:N conversion`. The name of the failing pattern is shown in
the error message. These patterns must be updated to the new 1:N
`matchAndRewrite` API.
Commit: 04ab599363eacc156e11238da9343c1d9d90db56
https://github.com/llvm/llvm-project/commit/04ab599363eacc156e11238da9343c1d9d90db56
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp
Log Message:
-----------
[clang-tidy] fix false positive in bugprone-return-const-ref-from-parameter (#117734)
Fix https://github.com/llvm/llvm-project/issues/115743
Commit: 1f13713dbb323d678c37efd5aa98a69e8f633b26
https://github.com/llvm/llvm-project/commit/1f13713dbb323d678c37efd5aa98a69e8f633b26
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Target.cpp
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Change getSrcMsg to use ELFSyncStream. NFC
Commit: 58389b220a9354ed6c34bdb9310a35165579c5e3
https://github.com/llvm/llvm-project/commit/58389b220a9354ed6c34bdb9310a35165579c5e3
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/CodeGen/FIROpPatterns.h
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir] Fix build after #116470 (#118147)
This should have been part of #116470.
Commit: 10b98473e8f9e3886bd4a51966c755d760de14ed
https://github.com/llvm/llvm-project/commit/10b98473e8f9e3886bd4a51966c755d760de14ed
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M lld/ELF/ICF.cpp
Log Message:
-----------
[ELF] Simplify --print-icf-sections
Commit: ee19eb3037c781361e6f82c524b500ed5f55be18
https://github.com/llvm/llvm-project/commit/ee19eb3037c781361e6f82c524b500ed5f55be18
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/i386-sections-max-va-overflow.s
M lld/test/ELF/linkerscript/locationcountererr-arm-exidx.test
M lld/test/ELF/linkerscript/sections-max-va-overflow.s
Log Message:
-----------
[ELF] Change some upper-case utohexstr to lower-case to improve consistency
The convention is to use lower-case addresses.
Commit: b9ac390cc7ec208fc738a91540b070f499b292b8
https://github.com/llvm/llvm-project/commit/b9ac390cc7ec208fc738a91540b070f499b292b8
Author: antangelo <contact at antangelo.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
Log Message:
-----------
[GISel] Add generic implementation for @llvm.expect.with.probability when optimizations are disabled (#117835)
Handle @llvm.expect.with.probability in GlobalISel in the same way
@llvm.expect is handled, passing the value through as-is. This can be
encountered if the intrinsic is used without optimizations, which would
otherwise transform it out.
Fixes #115411 for GlobalISel
Commit: 691e55643daa3470ff19b02a55e3e2503d2de0c9
https://github.com/llvm/llvm-project/commit/691e55643daa3470ff19b02a55e3e2503d2de0c9
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
Log Message:
-----------
[Driver] BuildCompilation: remove unused BaseArg. NFC
setBaseArg, only used by -XArch_* options, are called in BuildJobs.
When processing --config and CL /clang:, BaseArg is always nullptr.
The unneeded parameter was introduced in https://reviews.llvm.org/D24933
Commit: a348f223cab54b21a7b1c38dec7bc6aa2f81c949
https://github.com/llvm/llvm-project/commit/a348f223cab54b21a7b1c38dec7bc6aa2f81c949
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrFormats.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/test/CodeGen/ARM/add-like-or.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/ARM/atomic-64bit.ll
M llvm/test/CodeGen/ARM/atomic-ops-v8.ll
M llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/ARM/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
M llvm/test/CodeGen/ARM/bfi.ll
M llvm/test/CodeGen/ARM/cmov_fp16.ll
M llvm/test/CodeGen/ARM/cse-call.ll
M llvm/test/CodeGen/ARM/cttz.ll
M llvm/test/CodeGen/ARM/fadd-select-fneg-combine.ll
M llvm/test/CodeGen/ARM/fcmp-xo.ll
M llvm/test/CodeGen/ARM/fpclamptosat.ll
M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
M llvm/test/CodeGen/ARM/fpscr-multi-use.ll
M llvm/test/CodeGen/ARM/fptoi-sat-store.ll
M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
M llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
M llvm/test/CodeGen/ARM/funnel-shift-rot.ll
M llvm/test/CodeGen/ARM/funnel-shift.ll
M llvm/test/CodeGen/ARM/ifcvt1.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon_vabd.ll
M llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/ARM/sadd_sat.ll
M llvm/test/CodeGen/ARM/sadd_sat_plus.ll
M llvm/test/CodeGen/ARM/select.ll
M llvm/test/CodeGen/ARM/select_const.ll
M llvm/test/CodeGen/ARM/shift-i64.ll
M llvm/test/CodeGen/ARM/ssub_sat.ll
M llvm/test/CodeGen/ARM/ssub_sat_plus.ll
M llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
M llvm/test/CodeGen/ARM/uadd_sat.ll
M llvm/test/CodeGen/ARM/uadd_sat_plus.ll
M llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/ARM/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/ARM/usub_sat.ll
M llvm/test/CodeGen/ARM/usub_sat_plus.ll
M llvm/test/CodeGen/ARM/vselect_imax.ll
M llvm/test/CodeGen/ARM/wide-compares.ll
M llvm/test/CodeGen/Thumb/arm_q15_to_q31.ll
M llvm/test/CodeGen/Thumb/select.ll
M llvm/test/CodeGen/Thumb/smul_fix_sat.ll
M llvm/test/CodeGen/Thumb/stack-guard-xo.ll
M llvm/test/CodeGen/Thumb/umul_fix_sat.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
M llvm/test/CodeGen/Thumb2/float-ops.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-doublereduct.ll
M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-fmas.ll
M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
M llvm/test/CodeGen/Thumb2/mve-pred-or.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
M llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
M llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
M llvm/test/CodeGen/Thumb2/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/Thumb2/umulo-64-legalisation-lowering.ll
Log Message:
-----------
[ARM] Stop gluing ALU nodes to branches / selects (#116970)
Following #116547 and #116676, this PR changes the type of results and
operands of some nodes to accept / return a normal type instead of Glue.
Unfortunately, changing the result type of one node requires changing
the operand types of all potential consumer nodes, which in turn
requires changing the result types of all other possible producer nodes.
So this is a bulk change.
Pull Request: https://github.com/llvm/llvm-project/pull/116970
Commit: a8a494faab8af60754c4647dbb7b24bc86a80aab
https://github.com/llvm/llvm-project/commit/a8a494faab8af60754c4647dbb7b24bc86a80aab
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/lib/Support/SmallPtrSet.cpp
Log Message:
-----------
[SmallPtrSet] Remove SmallArray member (NFC) (#118099)
Currently SmallPtrSet stores CurArray and SmallArray, with the former
pointing to the latter in small representation. Instead, only use
CurArray and a separate IsSmall boolean.
Most of the implementation doesn't need the separate SmallArray member
-- we only need it for copy/move/swap operations, where we may switch
back from large to small representation. In those cases, we explicitly
pass down the pointer to SmallStorage.
This reduces the size of SmallPtrSet and improves compile-time.
Commit: 04cc492ec3e2792e3fa790750ff678baa90bd436
https://github.com/llvm/llvm-project/commit/04cc492ec3e2792e3fa790750ff678baa90bd436
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M libcxx/include/__configuration/availability.h
Log Message:
-----------
[libc++][NFC] Remove unused macros from <__configuration/availability.h>
Commit: 39209724e66a20080bdebc609a051dfa0eb6b49f
https://github.com/llvm/llvm-project/commit/39209724e66a20080bdebc609a051dfa0eb6b49f
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/lib/Support/YAMLTraits.cpp
M llvm/unittests/Support/YAMLIOTest.cpp
Log Message:
-----------
[YAML] Fix incorrect dash output in nested sequences (#116488)
Nested sequences could be defined but the YAML output was incorrect.
`Output::newLineCheck()` was not able to emit multiple dashes `- ` and
YAML parser sometimes didn't accept its output as the result.
This fixes for emitting corresponding dashes for consecutive
`inSeqFirstElement`, but suppresses emission to the top
`inSeqFirstElement`.
This also fixes for emitting flow elements onto nested sequences.
Commit: 1c702d38540dd8bad50f22947b71769b4d0c1202
https://github.com/llvm/llvm-project/commit/1c702d38540dd8bad50f22947b71769b4d0c1202
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
A llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
Log Message:
-----------
[SCEV] Add tests where one wrap predicate implies another.
Commit: f89fa238faa6a63168997a8a1d03c15b71da8080
https://github.com/llvm/llvm-project/commit/f89fa238faa6a63168997a8a1d03c15b71da8080
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
Log Message:
-----------
[clang-tidy][use-internal-linkage]fix false positives for global overloaded operator new and operator delete (#117945)
Commit: 4148aa63e2285ec7198c67d9b231b9097076ba8e
https://github.com/llvm/llvm-project/commit/4148aa63e2285ec7198c67d9b231b9097076ba8e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
A llvm/utils/merge-json.py
M runtimes/CMakeLists.txt
Log Message:
-----------
[Reland][Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)
Summary:
When building a project in a runtime mode, the compilation database is a
separate CMake invocation. So its `compile_commands.json` file will be
placed elsewhere in the `runtimes/runtime-bins` directory. This is
somewhat annoying for ongoing development when a runtimes build is
necessary. This patch adds some CMake magic to merge the two files.
Fixed issue w/ standalone runtimes build by checking if the LLVM src and
CMake src are the same.
Commit: 2e30df740ef0b9f8edb7075768540ce08678023d
https://github.com/llvm/llvm-project/commit/2e30df740ef0b9f8edb7075768540ce08678023d
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Fix validateOperandClass for non Phyical Reg (#118146)
https://github.com/llvm/llvm-project/commit/b71704436e61
Rewrote the register operands handling,
but the Table only contains physical regs, we will SEGV when there are
non physical regs.
---------
Co-authored-by: Sergei Barannikov <barannikov88 at gmail.com>
Commit: 9a0f25158c2eff539de1efbd55de71e711135db7
https://github.com/llvm/llvm-project/commit/9a0f25158c2eff539de1efbd55de71e711135db7
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[SelectOpt] Support ADD and SUB with zext operands. (#115489)
Extend the support for implicit selects in the form of OR with a ZExt
operand to support ADD and SUB binops as well. They similarly can form
implicit selects which can be profitable to convert back the branches.
PR: https://github.com/llvm/llvm-project/pull/115489
Commit: 92ba7e397377b8005206cb01a2052a750780827e
https://github.com/llvm/llvm-project/commit/92ba7e397377b8005206cb01a2052a750780827e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/test/CodeGen/AMDGPU/bitop3.ll
Log Message:
-----------
AMDGPU/GlobalISel: Do not try to form v_bitop3_b32 for SGPR results (#117940)
Commit: 1c7e4074b1efe7c3c9110f1d116b16f50fce9c88
https://github.com/llvm/llvm-project/commit/1c7e4074b1efe7c3c9110f1d116b16f50fce9c88
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-30 (Sat, 30 Nov 2024)
Changed paths:
M lldb/unittests/debugserver/RNBSocketTest.cpp
Log Message:
-----------
[lldb] Fix warning: 'sprintf' is deprecated in RNBSocketTest
Fixes warning: 'sprintf' is deprecated: This function is provided for
compatibility reasons only. Due to security concerns inherent in the
design of sprintf(3), it is highly recommended that you use snprintf(3)
instead.
Commit: 6568ceb9fa1c49383b2fa102a04fd8fd3af01491
https://github.com/llvm/llvm-project/commit/6568ceb9fa1c49383b2fa102a04fd8fd3af01491
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
A llvm/test/Transforms/CodeGenPrepare/X86/pr118172.ll
Log Message:
-----------
[CodeGenPrepare] Drop nsw flags in `optimizeLoadExt` (#118180)
Alive2: https://alive2.llvm.org/ce/z/pMcD7q
Closes https://github.com/llvm/llvm-project/issues/118172.
Commit: 017c75bfacdfa25594f8212a427627cff7aa98f3
https://github.com/llvm/llvm-project/commit/017c75bfacdfa25594f8212a427627cff7aa98f3
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir] Fix typo in test vector transform pass descriptions (#118194)
Fix some typos in the description of vector transform passes.
Commit: 6881c6d2a6ef2b9f1736afb124b2486d6b8bc603
https://github.com/llvm/llvm-project/commit/6881c6d2a6ef2b9f1736afb124b2486d6b8bc603
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcia-invalid.s
A llvm/test/MC/RISCV/xqcia-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)
This extension adds 11 instructions that perform integer arithmetic.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: 94df95de6bab20930c1a77bc785221ff2f670dba
https://github.com/llvm/llvm-project/commit/94df95de6bab20930c1a77bc785221ff2f670dba
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
Log Message:
-----------
[TTI][X86] getShuffleCosts - for SK_PermuteTwoSrc, if the masks are known to be "inlane" no need to scale the costs by worst-case legalization (#117999)
SK_PermuteTwoSrc legalization has to assume any of the legalised source registers could be referenced in split shuffles, but if we already know that each 128-bit lane only references elements from the same lane of the source operands, then this scaling won't occur.
Hopefully this can help with #113356 without us having to get full processShuffleMasks canonicalization finished first.
Commit: f7ef0721d60f85e1f699f8d1b83d4402ae19b122
https://github.com/llvm/llvm-project/commit/f7ef0721d60f85e1f699f8d1b83d4402ae19b122
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/pr117133.ll
A llvm/test/Transforms/IndVarSimplify/pr117133.ll
Log Message:
-----------
[SCEV] Do not allow refinement in the rewriting of BEValue (#117152)
See the following case:
```
; bin/opt -passes="print<scalar-evolution>" test.ll --disable-output
define i32 @widget() {
b:
br label %b1
b1: ; preds = %b5, %b
%phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ]
%phi2 = phi i32 [ 1, %b ], [ %add, %b5 ]
%icmp = icmp eq i32 %phi, 0
br i1 %icmp, label %b3, label %b8
b3: ; preds = %b1
%udiv = udiv i32 10, %phi2
%urem = urem i32 %udiv, 10
%icmp4 = icmp eq i32 %urem, 0
br i1 %icmp4, label %b7, label %b5
b5: ; preds = %b3
%udiv6 = udiv i32 %phi2, 0
%add = add i32 %phi2, 1
br label %b1
b7: ; preds = %b3
ret i32 5
b8: ; preds = %b1
ret i32 7
}
```
```
%phi2 = phi i32 [ 1, %b ], [ %add, %b5 ] --> {1,+,1}<nuw><nsw><%b1>
%udiv6 = udiv i32 %phi2, 0 --> ({1,+,1}<nuw><nsw><%b1> /u 0)
%phi = phi i32 [ 0, %b ], [ %udiv6, %b5 ] --> ({0,+,1}<nuw><nsw><%b1> /u 0)
```
`ScalarEvolution::createAddRecFromPHI` gives a wrong SCEV result for
`%phi`:
https://github.com/llvm/llvm-project/blob/d7d6fb1804415b0f3e7f1cc9290bfb3d711cb707/llvm/lib/Analysis/ScalarEvolution.cpp#L5926-L5950
It converts `phi(0, ({1,+,1}<nuw><nsw><%b1> /u 0))` into `phi(0 / 0,
({1,+,1}<nuw><nsw><%b1> /u 0))`. Then it simplifies the expr into
`{0,+,1}<nuw><nsw><%b1> /u 0`.
As we did in
https://github.com/llvm/llvm-project/commit/acd700a24b6f767413db3d525e06d03e4245aa40,
this patch disallows udiv simplification if we cannot prove that the
denominator is a well-defined non-zero value.
Fixes https://github.com/llvm/llvm-project/issues/117133.
Commit: 22417ec6cca0ed8ccecb0c2b77011e591378fd2a
https://github.com/llvm/llvm-project/commit/22417ec6cca0ed8ccecb0c2b77011e591378fd2a
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/codeview-column-info.c
Log Message:
-----------
[Driver] Do not add gno-column-info when using sampling PGO (#117954)
Column info is important for sampling PGO to generate/load profile file.
On windows, it will be automatically added when using -gdwarf to
generate
profile file. It should also be generated when fprofile-sample-use= is
used.
Commit: 1a3eace82a885fca01a70472b3816007dbee9d9f
https://github.com/llvm/llvm-project/commit/1a3eace82a885fca01a70472b3816007dbee9d9f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/saturating-add-sub.ll
Log Message:
-----------
[InstCombine] Fold `umax(X, C) + -C` into `usub.sat(X, C)` (#118195)
Alive2: https://alive2.llvm.org/ce/z/oSWe5S
Closes https://github.com/llvm/llvm-project/issues/118155
Commit: 4a074330c6d587be51494f651f539c8055be201c
https://github.com/llvm/llvm-project/commit/4a074330c6d587be51494f651f539c8055be201c
Author: Chris Apple <cja-private at pm.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan] Intercept various file system functions (#118183)
Adds interceptors for
* chmod
* fchmod
* mkdir
* rmdir
* umask
Commit: 82ed9c0319c9f0373bcb633a03ce6d35ebac3661
https://github.com/llvm/llvm-project/commit/82ed9c0319c9f0373bcb633a03ce6d35ebac3661
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove APValue Result argument where unnecessary (#118199)
This is unneeded in almost all circumstances. We only return an APValue
back to clang when the evaluation is finished, and that is always done
by an EvalEmitter - which has its own implementation of the Ret
instructions.
Commit: 31bde711c4098b3136edd1cb92dd4e0cc1d4d179
https://github.com/llvm/llvm-project/commit/31bde711c4098b3136edd1cb92dd4e0cc1d4d179
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Support __builtin_reduce_add (#117672)
Commit: 77767986ed423f868805d8ee9652f6dcc85c6adc
https://github.com/llvm/llvm-project/commit/77767986ed423f868805d8ee9652f6dcc85c6adc
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[LV] Use IsaPred in a few more places (NFC).
Simplifies the code slightly by removing explicit lambdas.
Commit: 9becc4a3c966d46b95ddfcf856b3c433c030db1e
https://github.com/llvm/llvm-project/commit/9becc4a3c966d46b95ddfcf856b3c433c030db1e
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
Log Message:
-----------
[ELF] ObjFile::parse: check EM_AARCH64 for SHT_AARCH64_MEMTAG_GLOBAL_STATIC
and reorder sh_type checks to make SHT_PROGBITS/SHT_GROUP fast.
Commit: 2a5e1da57a42fa2fc081bbc11970871a1eecb3b3
https://github.com/llvm/llvm-project/commit/2a5e1da57a42fa2fc081bbc11970871a1eecb3b3
Author: Martin Storsjö <martin at martin.st>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrFormats.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/test/CodeGen/ARM/add-like-or.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/ARM/atomic-64bit.ll
M llvm/test/CodeGen/ARM/atomic-ops-v8.ll
M llvm/test/CodeGen/ARM/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/ARM/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
M llvm/test/CodeGen/ARM/bfi.ll
M llvm/test/CodeGen/ARM/cmov_fp16.ll
M llvm/test/CodeGen/ARM/cse-call.ll
M llvm/test/CodeGen/ARM/cttz.ll
M llvm/test/CodeGen/ARM/fadd-select-fneg-combine.ll
M llvm/test/CodeGen/ARM/fcmp-xo.ll
M llvm/test/CodeGen/ARM/fpclamptosat.ll
M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
M llvm/test/CodeGen/ARM/fpscr-multi-use.ll
M llvm/test/CodeGen/ARM/fptoi-sat-store.ll
M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
M llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
M llvm/test/CodeGen/ARM/funnel-shift-rot.ll
M llvm/test/CodeGen/ARM/funnel-shift.ll
M llvm/test/CodeGen/ARM/ifcvt1.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/neon_vabd.ll
M llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/ARM/sadd_sat.ll
M llvm/test/CodeGen/ARM/sadd_sat_plus.ll
M llvm/test/CodeGen/ARM/select.ll
M llvm/test/CodeGen/ARM/select_const.ll
M llvm/test/CodeGen/ARM/shift-i64.ll
M llvm/test/CodeGen/ARM/ssub_sat.ll
M llvm/test/CodeGen/ARM/ssub_sat_plus.ll
M llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
M llvm/test/CodeGen/ARM/uadd_sat.ll
M llvm/test/CodeGen/ARM/uadd_sat_plus.ll
M llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/ARM/umulo-64-legalisation-lowering.ll
M llvm/test/CodeGen/ARM/usub_sat.ll
M llvm/test/CodeGen/ARM/usub_sat_plus.ll
M llvm/test/CodeGen/ARM/vselect_imax.ll
M llvm/test/CodeGen/ARM/wide-compares.ll
M llvm/test/CodeGen/Thumb/arm_q15_to_q31.ll
M llvm/test/CodeGen/Thumb/select.ll
M llvm/test/CodeGen/Thumb/smul_fix_sat.ll
M llvm/test/CodeGen/Thumb/stack-guard-xo.ll
M llvm/test/CodeGen/Thumb/umul_fix_sat.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
M llvm/test/CodeGen/Thumb2/float-ops.ll
M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
M llvm/test/CodeGen/Thumb2/mve-doublereduct.ll
M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-fmas.ll
M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
M llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
M llvm/test/CodeGen/Thumb2/mve-pred-or.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
M llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
M llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
M llvm/test/CodeGen/Thumb2/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/Thumb2/umulo-64-legalisation-lowering.ll
Log Message:
-----------
Revert "[ARM] Stop gluing ALU nodes to branches / selects" (#118232)
Reverts llvm/llvm-project#116970.
This change broke Wine compiled for armv7, causing segfaults when
starting Wine. See llvm/llvm-project#116970 for more detailed discussion
about the issue.
Commit: 603d41ab7b4078a00a5d3b899d3b9d14eea2d8ff
https://github.com/llvm/llvm-project/commit/603d41ab7b4078a00a5d3b899d3b9d14eea2d8ff
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M lld/ELF/InputSection.cpp
Log Message:
-----------
[ELF] decompress: remove mutex
decompress() is in the parallel code path splitIntoPieces
and we should avoid mutex.
Commit: a09df64f406be162b0bd096dbe2466603b7a4f29
https://github.com/llvm/llvm-project/commit/a09df64f406be162b0bd096dbe2466603b7a4f29
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
Log Message:
-----------
[ELF] postParse: remove some branches in the fast path
Commit: 73f087b3318a8f887cd867f27608f693fee6dc7b
https://github.com/llvm/llvm-project/commit/73f087b3318a8f887cd867f27608f693fee6dc7b
Author: antangelo <contact at antangelo.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
R llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
M llvm/test/CodeGen/X86/fast-isel-expect.ll
Log Message:
-----------
[NFC][SelectionDAG] Replace generic @llvm.expect.with.probability codegen test with X86 test (#117848)
Adds test case for X86 to check that the output of
@llvm.expect.with.probability's generic lowering is reasonable. This
replaces a generic test which only asserts that llc does not crash.
Commit: 574f64ca61d252dbcf98621e056ab02b93d928bc
https://github.com/llvm/llvm-project/commit/574f64ca61d252dbcf98621e056ab02b93d928bc
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/include/llvm/Support/TimeProfiler.h
Log Message:
-----------
[TimeProfiler] Remove unneeded check
Commit: 92a4b443260ccf9237b873850a9b511fdcffd79a
https://github.com/llvm/llvm-project/commit/92a4b443260ccf9237b873850a9b511fdcffd79a
Author: Abdul Raheem <abdulraheembeigh at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
Log Message:
-----------
[MLIR][NFC] Fixed a typo of member variable static_basis (#117678)
-- Fixed a typo of member variable static_basis of
AffineDelinearizeIndexOp operation in AffineOps.td
Signed-off: Abdul Raheem Beigh <abdulraheembeigh at gmail.com>
Commit: a4c3683b665c6ac875b4821f5c6a881fdf5fef70
https://github.com/llvm/llvm-project/commit/a4c3683b665c6ac875b4821f5c6a881fdf5fef70
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M mlir/include/mlir/Interfaces/DestinationStyleOpInterface.td
Log Message:
-----------
[mlir][NFC] Fix typo. (#118163)
Fixes https://github.com/llvm/llvm-project/issues/117222.
Commit: 427fb5cc5ac34414c4682c90d3db0c63c5a1b227
https://github.com/llvm/llvm-project/commit/427fb5cc5ac34414c4682c90d3db0c63c5a1b227
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Log Message:
-----------
[ORC] Track all dependencies on symbols that aren't Ready yet.
AsynchronousSymbolQuery tracks the symbols that it depends on in order to (1)
detach the query in the event of a failure, and (2) report those dependencies
to clients of the ExecutionSession::lookup method (via the RegisterDependencies
argument). Previously we tracked only dependencies on symbols that didn't meet
the required state (the only symbols that the query needs to be attached to),
but this is insufficient to report all necessary dependencies to lookup clients.
E.g. A lookup requiring SymbolState::Resolved where some matched symbol is
already Resolved but not yet Emitted or Ready would result in the dependency on
that symbol not being reported, which could result in illegal access in
concurrent JIT setups. (This bug was discovered by @mikaoP on discord with a
simple concurrent JIT setup).
This patch tracks and reports all dependencies on symbols that aren't Ready yet,
correcting the under-reporting issue. AsynchronousSymbolQuery::detach is updated
to stop asserting that all depended-upon symbols have a query attached.
Commit: ed7a8f15564f11ce8ceabaa925a26842302b8450
https://github.com/llvm/llvm-project/commit/ed7a8f15564f11ce8ceabaa925a26842302b8450
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M offload/test/mapping/map_both_pointer_pointee.c
M offload/test/mapping/power_of_two_alignment.c
Log Message:
-----------
[NFC][Offload] Correct the compile command of two C test files (#118243)
The compile command for the two C test files are `compilexx`, which is
actually
for C++ compilation.
Commit: 8cb44859cc31929521c09fc6a8add66d53db44de
https://github.com/llvm/llvm-project/commit/8cb44859cc31929521c09fc6a8add66d53db44de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
R offload/test/mapping/power_of_two_alignment.c
A offload/test/mapping/power_of_two_alignment.cpp
Log Message:
-----------
FIX: Fix test failure in offload/test/mapping/power_of_two_alignment.c
A C file with `template` in it. Awesome.
Commit: c4a1e0efe6b0767dfb5861a7e8814d7db0c0de8a
https://github.com/llvm/llvm-project/commit/c4a1e0efe6b0767dfb5861a7e8814d7db0c0de8a
Author: Richard Trieu <57020969+Weverything at users.noreply.github.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M clang/lib/AST/ASTDiagnostic.cpp
M clang/test/Misc/diag-template-diffing-cxx98.cpp
Log Message:
-----------
[clang] Remove redundant integer values in template type diffing
Look through SubstNonTypeTemplateParmExpr to find an IntegerLiteral
node when attempting to determine if extra info is printed via
the aka mechanism. This will avoid printing types such as
"array<5 aka 5>" and will only show "array<5>".
Commit: a9ad9e27caba2153b82fb3029694bfadaa5803cb
https://github.com/llvm/llvm-project/commit/a9ad9e27caba2153b82fb3029694bfadaa5803cb
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
M llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test
Log Message:
-----------
[PAC][llvm-readobj][AArch64] Move PAuth GOT relocs out of private space (#118214)
Apply change from the spec
https://github.com/ARM-software/abi-aa/pull/300
Commit: 010317e1731d76b91c00ed1241583e518380d65f
https://github.com/llvm/llvm-project/commit/010317e1731d76b91c00ed1241583e518380d65f
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-module.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
Log Message:
-----------
[clang-tidy][use-internal-linkage]fix false positives for ExportDecl (#117901)
Fixed: #97190
Commit: 91f69b70e075a475b550e3ef832816c47311e2bd
https://github.com/llvm/llvm-project/commit/91f69b70e075a475b550e3ef832816c47311e2bd
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Remove redundant check from ObjectLinkingLayer.
Non-locally scoped symbols must have names.
Commit: 0a44b24d6697ee8542583960c4a4166fc805883c
https://github.com/llvm/llvm-project/commit/0a44b24d6697ee8542583960c4a4166fc805883c
Author: Adam Yang <hanbyang at microsoft.com>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll
M llvm/utils/TableGen/DXILEmitter.cpp
Log Message:
-----------
[DXIL] Add GroupMemoryBarrierWithGroupSync intrinsic (#114349)
fixes #112974
partially fixes #70103
An earlier version of this change was reverted so some issues could be fixed.
### Changes
- Added new tablegen based way of lowering dx intrinsics to DXIL ops.
- Added int_dx_group_memory_barrier_with_group_sync intrinsic in
IntrinsicsDirectX.td
- Added expansion for int_dx_group_memory_barrier_with_group_sync in
DXILIntrinsicExpansion.cpp`
- Added DXIL backend test case
### Related PRs
* [[clang][HLSL] Add GroupMemoryBarrierWithGroupSync intrinsic
#111883](https://github.com/llvm/llvm-project/pull/111883)
* [[SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic
#111888](https://github.com/llvm/llvm-project/pull/111888)
Commit: d9d656edd4d6d7ca1be5c2f2e0cca4d1ef773dd5
https://github.com/llvm/llvm-project/commit/d9d656edd4d6d7ca1be5c2f2e0cca4d1ef773dd5
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-01 (Sun, 01 Dec 2024)
Changed paths:
M lld/ELF/Symbols.cpp
Log Message:
-----------
[ELF] resolve LazySymbol: remove a branch in the fast path
Commit: dd0d9561b8945d4128814bd7eda1bc470a1552f7
https://github.com/llvm/llvm-project/commit/dd0d9561b8945d4128814bd7eda1bc470a1552f7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
A clang/test/AST/ByteCode/altivec.c
M clang/test/AST/ByteCode/vectors.cpp
Log Message:
-----------
[clang][bytecode] Support vector-to-vector bitcasts (#118230)
Commit: 08c1a6b3e181c3af019b18489139bfe4b03d9d08
https://github.com/llvm/llvm-project/commit/08c1a6b3e181c3af019b18489139bfe4b03d9d08
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Log Message:
-----------
Revert "[ORC] Track all dependencies on symbols that aren't Ready yet."
This reverts commit 427fb5cc5ac34414c4682c90d3db0c63c5a1b227 while I investigate
the bot failure in https://lab.llvm.org/buildbot/#/builders/95/builds/6835.
Commit: eaa6cc547e7300b122efbbaf8940ee9d15f7964c
https://github.com/llvm/llvm-project/commit/eaa6cc547e7300b122efbbaf8940ee9d15f7964c
Author: Shankhin <44582011+firestrike007 at users.noreply.github.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M libc/src/__support/threads/linux/rwlock.h
Log Message:
-----------
Fixes #118231: Corrected spelling mistake in has_acitive_owner function (#118266)
Fixes #118231
- Updated the method name to `has_active_owner` in
`llvm-project/libc/src/__support/threads/linux/rwlock.h`
- Verified usage and updated all references to the method.
- Ran tests:
- `check-llvm-unit`
- `check-all`
Commit: 979a0356d4c90ec855be4f2d2f6687132cf10298
https://github.com/llvm/llvm-project/commit/979a0356d4c90ec855be4f2d2f6687132cf10298
Author: Veera <32646674+veera-sivarajan at users.noreply.github.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/test/CodeGen/attr-counted-by.c
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
A llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/saturating-add-sub.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
Log Message:
-----------
[InstCombine] Fold `X Pred C2 ? X BOp C1 : C2 BOp C1` to `min/max(X, C2) BOp C1` (#116888)
Fixes #82414.
General Proof: https://alive2.llvm.org/ce/z/ERjNs4
Proof for Tests: https://alive2.llvm.org/ce/z/K-934G
This PR transforms `select` instructions of the form `select (Cmp X C1)
(BOp X C2) C3` to `BOp (min/max X C1) C2` iff `C3 == BOp C1 C2`.
This helps in eliminating a noop loop in
https://github.com/rust-lang/rust/issues/123845 but does not improve
optimizations.
Commit: 7bbc049688a1586827d87ad8e2fc7cb3638ef2fc
https://github.com/llvm/llvm-project/commit/7bbc049688a1586827d87ad8e2fc7cb3638ef2fc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
Log Message:
-----------
[InstCombine] Consolidate another fold into select value equivalence (#117746)
We had a separate fold that handled just the trivial case where we're
replacing exactly the argument of the select. Handle this in select
value equivalence by relaxing the infinite loop protection to allow a
replacement of a non-constant with a constant.
This also fixes https://github.com/llvm/llvm-project/issues/113301, as
the separate fold did not handle undef values correctly.
Commit: 770adc56097342d3478c1b3b6d3e67cdf6d2c93e
https://github.com/llvm/llvm-project/commit/770adc56097342d3478c1b3b6d3e67cdf6d2c93e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaAttr.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
Log Message:
-----------
[clang] Infer lifetime_capture_by for map's subscript operator. (#118078)
Commit: a545cf5c6da6decbde95287f95e1ffce40116d23
https://github.com/llvm/llvm-project/commit/a545cf5c6da6decbde95287f95e1ffce40116d23
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
A flang/test/HLFIR/eval_in_mem-codegen.fir
A flang/test/HLFIR/eval_in_mem.fir
M flang/test/HLFIR/invalid.fir
Log Message:
-----------
[flang][hlfir] add hlfir.eval_in_mem operation (#118067)
See HLFIROps.td change for the description of the operation.
The goal is to ease temporary storage elision for expression evaluation
(typically evaluating the RHS directly inside the LHS) for expressions
that do not have abtsractions in HLFIR and for which it is not clear
adding one would bring much. The case that is implemented in [the
following lowering
patch](https://github.com/llvm/llvm-project/pull/118070) is the array
call case, where adding a new hlfir.call would add complexity (needs to
deal with dispatch, inlining ....).
Commit: 8201926ec0a61ea182e3b25c23e3dbaae6036dbf
https://github.com/llvm/llvm-project/commit/8201926ec0a61ea182e3b25c23e3dbaae6036dbf
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
Log Message:
-----------
[InstSimplify] Generalize simplification of icmps with monotonic operands (#69471)
InstSimplify currently folds patterns like `(x | y) uge x` and `(x & y)
ule x` to true. However, it cannot handle combinations of such
situations, such as `(x | y) uge (x & z)` etc.
To support this, recursively collect operands of monotonic instructions
(that preserve either a greater-or-equal or less-or-equal relationship)
and then check whether any of them match.
Fixes https://github.com/llvm/llvm-project/issues/69333.
Commit: 54fcf3ec26ad192e91b6ac924f6d3eb562e3647d
https://github.com/llvm/llvm-project/commit/54fcf3ec26ad192e91b6ac924f6d3eb562e3647d
Author: antangelo <contact at antangelo.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseDecl.cpp
M clang/test/CXX/drs/cwg722.cpp
A clang/test/Parser/cxx2c-oxford-variadic-comma.cpp
M clang/www/cxx_status.html
Log Message:
-----------
[clang] Implement P3176R1: The Oxford variadic comma (#117524)
Emit a deprecation warning when a variadic parameter in a
parameter-declaration-clause is not preceded by a comma for C++26.
Commit: 4851dbb8d6f1c00ad382ff4780293ca9a743c609
https://github.com/llvm/llvm-project/commit/4851dbb8d6f1c00ad382ff4780293ca9a743c609
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonPatterns.td
A llvm/test/CodeGen/Hexagon/addrmode-neg-offset.ll
Log Message:
-----------
[Hexagon] Use getSignedConstant for RoundTo8 XForm
To handle negative offset addrmodes correctly.
Fixes https://github.com/llvm/llvm-project/pull/117558#issuecomment-2510208764.
Commit: 98e747ba56b2f8b51a7c797a3f379d02c545c42b
https://github.com/llvm/llvm-project/commit/98e747ba56b2f8b51a7c797a3f379d02c545c42b
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/test/CodeGen/AArch64/pure-scalable-args.c
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
M clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
M clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
M clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
M clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-cast.c
M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-codegen.c
M clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
M clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
M clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
Log Message:
-----------
[clang] Use poison instead of undef as the placeholder when creating a new vector [NFC] (#117064)
Call `@llvm.vector.insert` with a `poison` vector when coercing a fixed
vector to a scalable vector with the same element type.
Commit: 7be501c1d3b3153e08603670873e1b3b700c9598
https://github.com/llvm/llvm-project/commit/7be501c1d3b3153e08603670873e1b3b700c9598
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] Allow import of similar friend template with different depth (#115734)
This fix applies to a case that occurs when the AST contains a friend
template that is contained within another template and this (outer)
template has specialization. (See the added test code in the commit.)
Commit: 9cbbf15db925c8d588b998487115a46250954dc1
https://github.com/llvm/llvm-project/commit/9cbbf15db925c8d588b998487115a46250954dc1
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
Log Message:
-----------
[AMDGPU] Only insert intrinsic declarations when needed (#117998)
Commit: 085e7d2b22876ebc03948a0690580e0189cddcc1
https://github.com/llvm/llvm-project/commit/085e7d2b22876ebc03948a0690580e0189cddcc1
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
R bolt/CODE_OWNERS.TXT
A bolt/Maintainers.txt
M llvm/Maintainers.md
Log Message:
-----------
[bolt] Move CODE_OWNERS.txt to Maintainers.txt (#118082)
To align with: https://llvm.org/docs/DeveloperPolicy.html#maintainers
I have not changed the format of the file, my only goal here is that the
project have a `bolt/Maintainers.*` so it is easy to find.
Commit: fec0eb4c3ef2a1fa2e0e413b0ea4871ee0bcebd1
https://github.com/llvm/llvm-project/commit/fec0eb4c3ef2a1fa2e0e413b0ea4871ee0bcebd1
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
R compiler-rt/CODE_OWNERS.TXT
A compiler-rt/Maintainers.txt
M llvm/Maintainers.md
Log Message:
-----------
[compiler-rt] Move CODE_OWNERS.txt to Maintainers.txt (#118086)
To align with https://llvm.org/docs/DeveloperPolicy.html#maintainers
No format change, I just want each project to have a `Maintainers.*`
file so it is easy to find.
Commit: df10f1c6f79a77e45e44c62974a186decb0f1f33
https://github.com/llvm/llvm-project/commit/df10f1c6f79a77e45e44c62974a186decb0f1f33
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Use getRISCVInstructionCost for split cost in mask reductions. NFC
This is effectively the same due to how the mask instructions have an
LMUL of 1 and cost of 1, but matches how we use LT.first elsewhere in
RISCVTargetTransformInfo.cpp by using it to multiply another
instruction cost.
Commit: 51003076ebc1ccc0cf339f9d96b2cfec84ab867c
https://github.com/llvm/llvm-project/commit/51003076ebc1ccc0cf339f9d96b2cfec84ab867c
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
A bolt/unittests/Core/MemoryMaps.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
Log Message:
-----------
Reapply [BOLT] DataAggregator support for binaries with multiple text segments (#118023)
When a binary has multiple text segments, the Size is computed as the
difference of the last address of these segments from the BaseAddress.
The base addresses of all text segments must be the same.
Introduces flag 'perf-script-events' for testing, which allows passing
perf events without BOLT having to parse them by invoking 'perf script'.
The flag is used to pass a mock perf profile that has two memory
mappings for a mock binary that has two text segments. The mapping
size is updated as `parseMMapEvents` now processes all text segments.
Commit: 7a7a426188eea0b181738436205759e13ad6fd7b
https://github.com/llvm/llvm-project/commit/7a7a426188eea0b181738436205759e13ad6fd7b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
Log Message:
-----------
[LVI] Fix insertelement of constexpr
Bail out when evaluating an insertelement of a constant expression.
Unlike other ValueLattice kinds, these don't have implicit splat
semantics and we end up with type mismatches. If we actually wanted
to handle these, we should actually evaluate the insertion via
constant folding. I'm not bothering with that, as these should
get constant folded on construction already.
Commit: 5248e1d4e1ee950d1703ec57141257b02446dd67
https://github.com/llvm/llvm-project/commit/5248e1d4e1ee950d1703ec57141257b02446dd67
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
A llvm/test/CodeGen/AArch64/stack-hazard-windows.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
Log Message:
-----------
[AArch64] Fix frame-pointer offset with hazard padding (#118091)
The `-aarch64-stack-hazard-size=<val>` option disables register paring
(as the hazard padding may mean the offset is too large for STP/LDP).
This broke setting the frame-pointer offset, as the code to find the
frame record looked for a (FP, LR) register pair.
This patch resolves this by looking for FP, LR as two unpaired registers
when hazard padding is enabled.
Commit: ede570980a2534c4a21850777b92505c02924416
https://github.com/llvm/llvm-project/commit/ede570980a2534c4a21850777b92505c02924416
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV][TTI] Add llvm.vp.select into canSplatOperand. (#117982)
The second operand of llvm.vp.select is a splat operand , it can help
llvm.vp.select fold vv instructions to vx instructions.
Commit: fe1c4f0106fe4fd6d61c38ba46e71fda8f4d1573
https://github.com/llvm/llvm-project/commit/fe1c4f0106fe4fd6d61c38ba46e71fda8f4d1573
Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
Log Message:
-----------
[mlir][vector][nfc] Remove redundant "`"
Commit: 57693edffccfdf0be92d669c6c5b26c8c35fba52
https://github.com/llvm/llvm-project/commit/57693edffccfdf0be92d669c6c5b26c8c35fba52
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-12-02 (Mon, 02 Dec 2024)
Changed paths:
M .ci/generate_test_report.py
A .ci/metrics/Dockerfile
A .ci/metrics/metrics.py
A .ci/metrics/requirements.lock.txt
A .ci/metrics/requirements.txt
M .github/new-issues-labeler.yml
A .github/workflows/build-metrics-container.yml
R bolt/CODE_OWNERS.TXT
A bolt/Maintainers.txt
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/check-init-not-moved.s
M bolt/unittests/Core/CMakeLists.txt
A bolt/unittests/Core/MemoryMaps.cpp
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
M clang-tools-extra/clang-tidy/bugprone/BranchCloneCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp
M clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/branch-clone.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/redundant-expression.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
A clang-tools-extra/test/clang-reorder-fields/FieldAnnotationsInMacros.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
A clang-tools-extra/test/clang-tidy/checkers/bugprone/alpha-core-identicalexpr.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-module.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
M clang/lib/AST/ASTDiagnostic.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/Analysis/Consumed.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Flang.h
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Headers/avx512vpopcntdqintrin.h
M clang/lib/Headers/avx512vpopcntdqvlintrin.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/ChrootChecker.cpp
R clang/lib/StaticAnalyzer/Checkers/IdenticalExprChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
A clang/test/AST/ByteCode/altivec.c
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/ByteCode/vectors.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/AST/ast-print-packindexingexpr.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/chroot.c
M clang/test/Analysis/ctor-trivial-copy.cpp
M clang/test/Analysis/explain-svals.cpp
R clang/test/Analysis/identical-expressions.cpp
M clang/test/Analysis/initializer.cpp
M clang/test/Analysis/iterator-modeling.cpp
M clang/test/Analysis/show-checker-list.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/stl-algorithm-modeling-aggressive-std-find-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling.cpp
M clang/test/Analysis/template-param-objects.cpp
M clang/test/CXX/drs/cwg722.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/test/CodeGen/AArch64/pure-scalable-args.c
M clang/test/CodeGen/AArch64/sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
M clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
M clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
M clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
M clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-cast.c
M clang/test/CodeGen/RISCV/attr-rvv-vector-bits-codegen.c
M clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
M clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
M clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c
M clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
M clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/Driver/cl-options.c
M clang/test/Driver/codeview-column-info.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/unsupported-option.c
M clang/test/Misc/diag-template-diffing-cxx98.cpp
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
A clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp
A clang/test/Parser/cxx2c-oxford-variadic-comma.cpp
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/test/Sema/builtin-counted-by-ref.c
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
A clang/test/SemaCXX/attr-no-specializations.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
A clang/test/SemaCXX/cxx20-warn-dangling-paren-list-agg-init.cpp
M clang/test/SemaCXX/literal-type.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
M clang/test/SemaCXX/warn-memaccess.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
A clang/test/SemaHIP/zero-sized-device-array.hip
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-clause.c
A clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
A clang/test/SemaTemplate/template-args-deduction-aggregates.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/www/cxx_status.html
R compiler-rt/CODE_OWNERS.TXT
A compiler-rt/Maintainers.txt
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/xray/weak_symbols.txt
M compiler-rt/lib/xray/xray_flags.cpp
M compiler-rt/lib/xray/xray_flags.h
A compiler-rt/test/xray/TestCases/Posix/default-options.cpp
A flang/include/flang/Common/OpenMP-utils.h
M flang/include/flang/Optimizer/CodeGen/FIROpPatterns.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/lib/Common/CMakeLists.txt
A flang/lib/Common/OpenMP-utils.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Driver/mabi-loongarch.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/arrayset.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/box-offset-codegen.fir
M flang/test/Fir/box.fir
M flang/test/Fir/boxproc.fir
M flang/test/Fir/commute.fir
M flang/test/Fir/coordinateof.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/field-index.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
A flang/test/Fir/struct-passing-loongarch64-byreg.fir
A flang/test/Fir/struct-passing-return-loongarch64-bystack.fir
M flang/test/Fir/struct-passing-x86-64-byval.fir
A flang/test/Fir/struct-return-loongarch64-byreg.fir
M flang/test/Fir/target-rewrite-complex-10-x86.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Lower/HLFIR/goto-do-body.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate2.f90
A flang/test/Lower/OpenMP/generic-loop-rewriting.f90
M flang/test/Lower/goto-do-body.f90
M flang/test/Lower/nsw.f90
A flang/test/Semantics/OpenMP/critical_within_default.f90
M flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
M flang/test/Transforms/constant-argument-globalisation.fir
A flang/test/Transforms/function-attrs.fir
A flang/test/Transforms/generic-loop-rewriting-todo.mlir
A flang/test/Transforms/generic-loop-rewriting.mlir
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/shared/rpc_opcodes.h
M libc/spec/linux.td
M libc/src/__support/RPC/rpc_client.cpp
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/threads/linux/rwlock.h
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M libc/utils/gpu/server/CMakeLists.txt
R libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
A libcxx/docs/CodingGuidelines.rst
M libcxx/docs/Contributing.rst
M libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
R libcxx/docs/DesignDocs/NodiscardPolicy.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/index.rst
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/latch
M libcxx/include/locale
M libcxx/include/semaphore
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/CMakeLists.txt
R libcxx/src/legacy_pointer_safety.cpp
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/GenerateInput.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
M libcxx/test/std/containers/sequences/vector.bool/ctor_exceptions.pass.cpp
A libcxx/test/std/containers/sequences/vector/common.h
M libcxx/utils/ci/run-buildbot-container
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputFiles.h
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Target.cpp
M lld/ELF/Writer.cpp
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
M lld/include/lld/Common/ErrorHandler.h
M lld/test/ELF/invalid-eh-frame3.s
M lld/test/ELF/invalid-eh-frame6.s
M lld/test/ELF/linkerscript/i386-sections-max-va-overflow.s
M lld/test/ELF/linkerscript/locationcountererr-arm-exidx.test
M lld/test/ELF/linkerscript/sections-max-va-overflow.s
M lld/test/ELF/tls.s
M lld/test/ELF/undef-multi.s
M lld/test/ELF/undef.s
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Host/common/UDPSocket.h
M lldb/include/lldb/Host/linux/AbstractSocket.h
M lldb/include/lldb/Host/posix/DomainSocket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/common/UDPSocket.cpp
M lldb/source/Host/linux/AbstractSocket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/DomainSocket.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/debugserver/RNBSocketTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/AddLLVM.cmake
M llvm/cmake/modules/GetHostTriple.cmake
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/XRay.rst
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/include/llvm/ADT/SmallPtrSet.h
M llvm/include/llvm/Analysis/InlineCost.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/AArch64.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
A llvm/include/llvm/CodeGen/SpillPlacement.h
M llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/Support/Error.h
M llvm/include/llvm/Support/TimeProfiler.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitstream/Reader/BitstreamReader.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SpillPlacement.cpp
R llvm/lib/CodeGen/SpillPlacement.h
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Object/XCOFFObjectFile.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Support/SmallPtrSet.cpp
M llvm/lib/Support/YAMLTraits.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVDuplicatesTracker.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Target/X86/X86WinEHState.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
A llvm/lib/Transforms/Coroutines/CoroCloner.h
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Analysis/CostModel/AArch64/extract_float_streaming.ll
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
A llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
A llvm/test/Analysis/ScalarEvolution/pr117133.ll
A llvm/test/Bitcode/Inputs/invalid-initializer.bc
M llvm/test/Bitcode/invalid.test
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-frame-tail.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/init-undef.mir
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
A llvm/test/CodeGen/AArch64/stack-hazard-windows.ll
M llvm/test/CodeGen/AArch64/stack-hazard.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
A llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/bitop3.ll
A llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
A llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll
R llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
A llvm/test/CodeGen/Hexagon/addrmode-neg-offset.ll
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
A llvm/test/CodeGen/PowerPC/frameindex-negative-offset.ll
M llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
M llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll
A llvm/test/CodeGen/PowerPC/ssubo-32.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
A llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
A llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/branching/if-merging.ll
M llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll
M llvm/test/CodeGen/SPIRV/instructions/ret-type.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
A llvm/test/CodeGen/SPIRV/pointers/builtin-ret-reg-type.ll
A llvm/test/CodeGen/SPIRV/pointers/gep-types-1.ll
A llvm/test/CodeGen/SPIRV/pointers/gep-types-2.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
M llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-via-store-load-args-rev.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll
M llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll
M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-simple-while-identity.ll
M llvm/test/CodeGen/SPIRV/structurizer/return-early.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGenericCastToPtr.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
A llvm/test/CodeGen/SPIRV/validate/sycl-hier-par-basic.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
A llvm/test/CodeGen/Thumb/returnaddress.ll
A llvm/test/CodeGen/WinEH/wineh-scope-statenumbering.ll
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
A llvm/test/CodeGen/X86/extract-vselect-setcc.ll
M llvm/test/CodeGen/X86/fast-isel-expect.ll
A llvm/test/CodeGen/X86/gfni-lzcnt.ll
A llvm/test/CodeGen/X86/gfni-tzcnt.ll
M llvm/test/CodeGen/X86/load-partial.ll
M llvm/test/CodeGen/X86/mmx-cvt.ll
A llvm/test/CodeGen/X86/pr114360.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-masked.ll
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
A llvm/test/MC/RISCV/xqcia-invalid.s
A llvm/test/MC/RISCV/xqcia-valid.s
A llvm/test/MC/RISCV/xqcicsr-invalid.s
A llvm/test/MC/RISCV/xqcicsr-valid.s
A llvm/test/MC/RISCV/xqcisls-invalid.s
A llvm/test/MC/RISCV/xqcisls-valid.s
A llvm/test/Transforms/CodeGenPrepare/X86/pr118172.ll
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DeadStoreElimination/stores-of-existing-values.ll
A llvm/test/Transforms/GVN/setjmp.ll
A llvm/test/Transforms/IndVarSimplify/pr117133.ll
A llvm/test/Transforms/Inline/AArch64/memcpy-constant-size.ll
A llvm/test/Transforms/InstCombine/canonicalize-const-to-bop.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/saturating-add-sub.ll
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/unsigned_saturated_sub.ll
M llvm/test/Transforms/InstSimplify/compare.ll
A llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
R llvm/test/Transforms/LoopVectorize/AArch64/scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-alloca-in-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int-also-fusable-multiply.ll
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/memcpy-constant-size.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
A llvm/test/Transforms/SLPVectorizer/X86/ashr-node-with-poison.ll
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_GNU_template_name.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/DW_AT_GNU_template_name.ll
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
A llvm/test/tools/llvm-objcopy/MachO/dysymtab-zero-indirectsym.test
M llvm/test/tools/llvm-readobj/ELF/reloc-types-aarch64.test
M llvm/unittests/ADT/BitmaskEnumTest.cpp
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
A llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/unittests/Support/YAMLIOTest.cpp
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVPartialOrderingVisitorTests.cpp
A llvm/unittests/Target/SPIRV/SPIRVSortBlocksTests.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/IPO/CMakeLists.txt
A llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/IPO/BUILD.gn
A llvm/utils/merge-json.py
M mlir/CMakeLists.txt
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
A mlir/include/mlir/Conversion/MeshToMPI/MeshToMPI.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Matchers.h
M mlir/include/mlir/Interfaces/DestinationStyleOpInterface.td
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/lib/Dialect/Func/Transforms/FuncConversions.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MPI/IR/CMakeLists.txt
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.h
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
A mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Transforms/decompose-call-graph-types.mlir
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M offload/CMakeLists.txt
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/test/mapping/map_both_pointer_pointee.c
R offload/test/mapping/power_of_two_alignment.c
A offload/test/mapping/power_of_two_alignment.cpp
M runtimes/CMakeLists.txt
M runtimes/cmake/Modules/FindLibcCommonUtils.cmake
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/jperier/opt_eval_in_mem
Compare: https://github.com/llvm/llvm-project/compare/d68b5b265283...57693edffccf
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list