[all-commits] [llvm/llvm-project] 1a2cc2: [ELF] Exclude sizeof(InputSection) to _WIN32
Aiden Grossman via All-commits
all-commits at lists.llvm.org
Fri Nov 29 11:19:00 PST 2024
Branch: refs/heads/users/boomanaiden154/build-metrics-container
Home: https://github.com/llvm/llvm-project
Commit: 1a2cc2bce86448dfb1c9795a907d28ca2db6aaf5
https://github.com/llvm/llvm-project/commit/1a2cc2bce86448dfb1c9795a907d28ca2db6aaf5
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/InputSection.h
Log Message:
-----------
[ELF] Exclude sizeof(InputSection) to _WIN32
Structs with delicate packing are often larger in MSVC than Itanium.
099a52fd2f3723db6b0550c99a1adc12d2d8d909 did not make
sizeof(InputSection) smaller for MSVC. Just exclude MSVC.
Commit: ae01e3a7c66d68544c85dd6e2c5498d3c5896e29
https://github.com/llvm/llvm-project/commit/ae01e3a7c66d68544c85dd6e2c5498d3c5896e29
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[nfc][sancov] Remove unnecessary default argument (#117463)
Commit: 215f3dd5f6b82000bd61a5e8ff4a065baf8f4e3f
https://github.com/llvm/llvm-project/commit/215f3dd5f6b82000bd61a5e8ff4a065baf8f4e3f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[nfc][sancov] Remove unnecessary default argument (#117464)
Commit: 8d650736c19f2bd6a84dc29ec0becfceb357a739
https://github.com/llvm/llvm-project/commit/8d650736c19f2bd6a84dc29ec0becfceb357a739
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
Log Message:
-----------
[AMDGPU] Fix AMDGPUISD::TRAP description (#117453)
Glue operand is only present if there are variadic register operands,
which makes it optional.
Also, change the number of fixed operands to 1 (the trap ID).
Commit: c85c77c054f3e330c23501db115b1adc505b9805
https://github.com/llvm/llvm-project/commit/c85c77c054f3e330c23501db115b1adc505b9805
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
Log Message:
-----------
[AVR] Fix shift node descriptions (#117456)
Wide shift nodes produce two results, not one.
Reuse the added type profile to define the standard "shift parts" nodes.
Commit: 68a48ec90fb6609b964addcc99a55d16eee884a0
https://github.com/llvm/llvm-project/commit/68a48ec90fb6609b964addcc99a55d16eee884a0
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
Log Message:
-----------
[clang][analysis][NFC]place the comment to correct position (#117467)
Commit: eb4d2f24a7246ce05da789c9506201ce18638046
https://github.com/llvm/llvm-project/commit/eb4d2f24a7246ce05da789c9506201ce18638046
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/Common/ErrorHandler.cpp
M lld/ELF/Driver.cpp
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Simplify reportMissingFeature. NFC
Commit: 5fa0345d90d60a90a1cc0cf33bab997c3e26b84e
https://github.com/llvm/llvm-project/commit/5fa0345d90d60a90a1cc0cf33bab997c3e26b84e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
Log Message:
-----------
[tsan] Unwind for CHECK according to fast_unwind_on_fatal (#117470)
It's needed for #116409, which hangs with slow
unwind.
Commit: 4d4a353b8eddb0728d5b278befdccda4de484319
https://github.com/llvm/llvm-project/commit/4d4a353b8eddb0728d5b278befdccda4de484319
Author: gbMattN <146744444+gbMattN at users.noreply.github.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_deadlock_detector.h
A compiler-rt/test/tsan/many_held_mutex.cpp
Log Message:
-----------
[TSan] Increase the number of simultaneously locked mutexes that a thread can hold (#116409)
I've run into an issue where TSan can't be used on some code without
turning off deadlock detection because a thread tries to hold too many
mutexes. It would be preferable to be able to use deadlock detection as
that is a major benefit of TSan.
Its mentioned in https://github.com/google/sanitizers/issues/950 that
the 64 mutex limit was an arbitrary number. I've increased it to 128 and
all the tests still pass. Considering the increasing number of cores on
CPUs and how programs can now use more threads to take advantage of it,
I think raising the limit to 128 would be some good future proofing
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 2af6ddb8a2cdc2a9a8a84a6244905bf9158cca8b
https://github.com/llvm/llvm-project/commit/2af6ddb8a2cdc2a9a8a84a6244905bf9158cca8b
Author: Théo Degioanni <theo.degioanni.llvm.deluge062 at simplelogin.fr>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/test/IR/properties.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir][ods] Fix missing property elision for variadic segment properties (#115930)
This fixes a bug where variadic segment properties would not be elided
when printing `prop-dict`.
Commit: bd7d6c806608b150b8aab87012afdbd3bed38c29
https://github.com/llvm/llvm-project/commit/bd7d6c806608b150b8aab87012afdbd3bed38c29
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 776476c282bca71d5b856e80e0a88fbd6f3ccdd2
Commit: c4d656a4e992648f3490536336c230041c74dc38
https://github.com/llvm/llvm-project/commit/c4d656a4e992648f3490536336c230041c74dc38
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependencies for a0ef12c64284abf59bc092b2535cce1247d5f9a4
Commit: f942949a7cf16a082eb43943b2a4f93f9180556f
https://github.com/llvm/llvm-project/commit/f942949a7cf16a082eb43943b2a4f93f9180556f
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/SymbolTable.cpp
M lld/test/COFF/arm64ec.test
Log Message:
-----------
[LLD][COFF] Require explicit specification of ARM64EC target (#116281)
Inferring the ARM64EC target can lead to errors. The `-machine:arm64ec`
option may include x86_64 input files, and any valid ARM64EC input is
also valid for `-machine:arm64x`. MSVC requires an explicit `-machine`
argument with informative diagnostics; this patch adopts the same
behavior.
Commit: 0c21ed48f40b2a6e3aa7e5d1873cf2455e847786
https://github.com/llvm/llvm-project/commit/0c21ed48f40b2a6e3aa7e5d1873cf2455e847786
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tidy][NFC] fix release note order (#117484)
Commit: 7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
https://github.com/llvm/llvm-project/commit/7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
Author: Fabian Mora <6982088+fabianmcg at users.noreply.github.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h
A mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.td
A mlir/include/mlir/Conversion/GPUCommon/GPUToLLVM.h
A mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVM.h
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-target-attr.mlir
Log Message:
-----------
[mlir][LLVM] Add the `ConvertToLLVMAttrInterface` and `ConvertToLLVMOpInterface` interfaces (#99566)
This patch adds the `ConvertToLLVMAttrInterface` and
`ConvertToLLVMOpInterface` interfaces. It also modifies the
`convert-to-llvm` pass to use these interfaces when available.
The `ConvertToLLVMAttrInterface` interfaces allows attributes to
configure conversion to LLVM, including the conversion target, LLVM type
converter, and populating conversion patterns. See the `NVVMTargetAttr`
implementation of this interface for an example of how this interface
can be used to configure conversion to LLVM.
The `ConvertToLLVMOpInterface` interface collects all convert to LLVM
attributes stored in an operation.
Finally, the `convert-to-llvm` pass was modified to use these interfaces
when available. This allows applying `convert-to-llvm` to GPU modules
and letting the `NVVMTargetAttr` decide which patterns to populate.
Commit: 08bf901ed4a66d3afa8edbf167f658a2647147c5
https://github.com/llvm/llvm-project/commit/08bf901ed4a66d3afa8edbf167f658a2647147c5
Author: Xing Xue <xingxue at outlook.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
Log Message:
-----------
Revert "[AIX] Fix AIX BuildBot failure as AIX linker doesn't support version script." (#117444)
Commit
https://github.com/llvm/llvm-project/commit/eaa0a21d21962280dc2c03a09152510f6162a576
has fixed the build problem already so the change in
llvm/llvm-project#117342 does not make sense any more. I am reverting
it.
Commit: 63d9ef5e37539b8920eb6c93524e4be2c33a510c
https://github.com/llvm/llvm-project/commit/63d9ef5e37539b8920eb6c93524e4be2c33a510c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConcepts.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/AST/TemplateName.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#117469)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: aafe934c0c0c1d274099228e7e47669770235284
https://github.com/llvm/llvm-project/commit/aafe934c0c0c1d274099228e7e47669770235284
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
Log Message:
-----------
[hexagon] Require "asserts" build for widen-not-load test (#117414)
This test fails on the `clang-x64-windows-msvc` builder:
.---command stderr------------
|
C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\test\CodeGen\Hexagon\widen-not-load.ll:7:16:
error: CHECK-LABEL: expected string not found in input
| ; CHECK-LABEL: test1
| ^
| <stdin>:1:1: note: scanning from here
| llc.exe: Unknown command line argument
'-debug-only=hexagon-load-store-widening'. Try:
'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\llc.exe --help'
| ^
| <stdin>:1:35: note: possible intended match here
| llc.exe: Unknown command line argument
'-debug-only=hexagon-load-store-widening'. Try:
'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\llc.exe --help'
| ^
Commit: 6cfaddfd52d088c15a61b8149f39505019c73458
https://github.com/llvm/llvm-project/commit/6cfaddfd52d088c15a61b8149f39505019c73458
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
Log Message:
-----------
[X86] Split rr/rm CVT schedules on SNB/HSW/BDW (#117494)
The folded load variants almost never require Port5 for length changing conversions (just for SNB ymm cases), and don't typically use an extra uop for the load.
Confirmed with a mixture of Agner + uops.info comparisons.
Commit: 0a6d797c20f6ab53bc09fb66129f603ed6e4b524
https://github.com/llvm/llvm-project/commit/0a6d797c20f6ab53bc09fb66129f603ed6e4b524
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s
Log Message:
-----------
[X86] Improve F16C CVT schedules on SNB/HSW/BDW
Add complete IvyBridge schedule (which is included in the SandyBridge model, IvyBridge was the first to support F16C) - split rr/rm schedules as they usually have very different port usage.
Haswell/Broadwell use Port1 not Port0.
Confirmed with a mixture of Agner + uops.info comparisons.
Commit: ff97b283346273000a8140d6a3a8fcb5a1589946
https://github.com/llvm/llvm-project/commit/ff97b283346273000a8140d6a3a8fcb5a1589946
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/Common/ErrorHandler.cpp
M lld/ELF/Relocations.cpp
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Simplif reportUndefinedSymbol. NFC
Commit: c2ffb42893eb543f64169e32851e00352feaca69
https://github.com/llvm/llvm-project/commit/c2ffb42893eb543f64169e32851e00352feaca69
Author: Kazuki Sakamoto <sakamoto at splhack.org>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Fix TestLoadUnload.py (#117416)
ELF core debugging fix #117070 broke TestLoadUnload.py tests due to
GetModuleSpec call, ProcessGDBRemote fetches modules from remote. Revise
the original PR, renamed FindBuildId to FindModuleUUID.
Commit: 0dbdc6dc358bfe24d83c23ccc1c84c468ed24f30
https://github.com/llvm/llvm-project/commit/0dbdc6dc358bfe24d83c23ccc1c84c468ed24f30
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Simplify code to re-use existing basic blocks (NFCI).
Restructure and slightly simplify code to re-use existing basic blocks.
Commit: d8495ede01329e8636e43847517da1c9d80b896e
https://github.com/llvm/llvm-project/commit/d8495ede01329e8636e43847517da1c9d80b896e
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Relocations.cpp
Log Message:
-----------
[ELF] Change getLocation to use ELFSyncStream. NFC
Commit: 360718fb90cb60572c210ed4fa671128232cf3ba
https://github.com/llvm/llvm-project/commit/360718fb90cb60572c210ed4fa671128232cf3ba
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/test/ELF/linkerscript/symbol-location.s
Log Message:
-----------
[test] Improve symbol-location.s to check --defsym
Commit: c790d6f53f617b73c40d42a217c120023b9ab66f
https://github.com/llvm/llvm-project/commit/c790d6f53f617b73c40d42a217c120023b9ab66f
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/incompatible.s
Log Message:
-----------
[ELF] isCompatile: avoid a toStr and 2 ErrAlways
Commit: c4dc5ed8254e6b318200496d687b0a7b3163dc26
https://github.com/llvm/llvm-project/commit/c4dc5ed8254e6b318200496d687b0a7b3163dc26
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.h
Log Message:
-----------
[ELF] Avoid some toStr and ErrAlways
Commit: 1cd627562b8b66b5f9b0797fc45afcfa054daedd
https://github.com/llvm/llvm-project/commit/1cd627562b8b66b5f9b0797fc45afcfa054daedd
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Remove unneeded Twine in ELFSyncStream
Commit: 590f451b60d434b26c634a07125fb05baf461fa0
https://github.com/llvm/llvm-project/commit/590f451b60d434b26c634a07125fb05baf461fa0
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
Log Message:
-----------
[VPlan] Allow setting IR name for VPDerivedIVRecipe (NFCI).
Allow setting the name to use for the generated IR value of the derived
IV in preparations for https://github.com/llvm/llvm-project/pull/112145.
This is analogous to VPInstruction::Name.
Commit: 5ce4d4c77517f1bc9ad11b2637056b870f2bd156
https://github.com/llvm/llvm-project/commit/5ce4d4c77517f1bc9ad11b2637056b870f2bd156
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/test/Dialect/GPU/barrier-elimination.mlir
Log Message:
-----------
[mlir] fix memory effects in GPU barrier elimination (#117432)
Existing implementation may trigger infinite cycles when collecting
effects above or below the current block after wrapping around a
loop-like construct. Limit this case to only looking at the immediate
block (loop body). This is correct because wrap around is intended to
consider effects of different iterations of the same loop and shouldn't
be existing the loop block.
Reported-by: Fabian Mora <fmora.dev at gmail.com>
Co-authored-by: Fabian Mora <fmora.dev at gmail.com>
Commit: e3aafe407af36f580148d3ceccd1aa13a490f7c9
https://github.com/llvm/llvm-project/commit/e3aafe407af36f580148d3ceccd1aa13a490f7c9
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
Log Message:
-----------
[clang-tidy] fix false positive use-internal-linkage for func decl without body (#117490)
If in one TU, function only have declaration without body, this function
should be external linkage.
Fixed #117488
Commit: ae20dbdd63d97c342b89a72e9e839556d0deed07
https://github.com/llvm/llvm-project/commit/ae20dbdd63d97c342b89a72e9e839556d0deed07
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
Log Message:
-----------
[clang][analysis] refactor the unevaluated api (#117474)
It is hard to understand for `ExprMutationAnalyzer::isUnevaluated` to
accept 2 Stmt as parameters.
This patch wants to redesign the API to accept only 1 Stmt. Now it will
only check whether stmt is a sub-stmt of an unevaluated stmt.
Commit: 605b8dad5cb173ac86adb3541e9f70a824aff364
https://github.com/llvm/llvm-project/commit/605b8dad5cb173ac86adb3541e9f70a824aff364
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidConstOrRefDataMembersCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/avoid-const-or-ref-data-members.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in cppcoreguidelines-avoid-const-or-ref-data-members when detecting templated classes with inheritance (#115180)
`hasSimpleCopyConstructor` series of functions are not reliable when
these functions are not resolved. We need to manually resolve the status
of these functions from its base classes.
Fixes: #111985.
Commit: 3c344f92e62ac07faf5df68d73ad765b11f465f2
https://github.com/llvm/llvm-project/commit/3c344f92e62ac07faf5df68d73ad765b11f465f2
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[clang][tablegen][NFC]add static for internal linkage function (#117479)
Detected by misc-use-internal-linkage
Commit: cbdd14ee9de72c277d9f89a6aa57c54a495f5458
https://github.com/llvm/llvm-project/commit/cbdd14ee9de72c277d9f89a6aa57c54a495f5458
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[clang][NFC]add static for internal linkage function (#117482)
Detected by misc-use-internal-linkage
Commit: 2a5e3a67a0248db4a6981e343f0033a32ad4a577
https://github.com/llvm/llvm-project/commit/2a5e3a67a0248db4a6981e343f0033a32ad4a577
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/AST/APValue.cpp
Log Message:
-----------
[AST] Fix a warning
This patch fixes:
clang/lib/AST/APValue.cpp:1091:1: error: unused function
'setLValueUninit' [-Werror,-Wunused-function]
Commit: 095f489757ead08184dd340f14a7b6158db6b0a3
https://github.com/llvm/llvm-project/commit/095f489757ead08184dd340f14a7b6158db6b0a3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/test/tools/llvm-mca/X86/SapphireRapids/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-adx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-aes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalgvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cd.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cdvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifmavl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaesvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-fma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lea.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x87.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/zero-idioms.s
Log Message:
-----------
[X86] Swap ports 10 and 11 in SapphireRapids Scheduling Model (#117468)
Based on intel/perfmon#149, the documentation is incorrect and the pfm
counter names are actually correct. This patch adjusts the
SapphireRapids scheduling model to match the performance counter naming/
correct naming that will soon be reflected in the optimization manual.
This fixes part of #117360.
Commit: 512dc5cb32e65081f4481afc757beade9bd64d04
https://github.com/llvm/llvm-project/commit/512dc5cb32e65081f4481afc757beade9bd64d04
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
Log Message:
-----------
[X86] Swap ports 10 and 11 in Alder Lake Scheduling Model (#117466)
Based on https://github.com/intel/perfmon/issues/149, the documentation
is incorrect and the pfm counter names are actually correct. This patch
adjusts the Alder Lake scheduling model to match the performance counter
naming/ correct naming that will soon be reflected in the optimization
manual.
This fixes part of #117360.
Commit: 5ed09d552d51825e495aebf38988beba83dbbca9
https://github.com/llvm/llvm-project/commit/5ed09d552d51825e495aebf38988beba83dbbca9
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Support/Compression.cpp
Log Message:
-----------
[Support] Check zstd decompress result before msan unpoison (#117276)
We should check the zstd decompress result before doing the msan
unpoison. If the res is abnormal, then it would be a huge number, which
will cause undesired msan unpoison behavior and will run for a long
time.
Commit: 6aeffa18e9ac51b7090325ea50d1841248a876c6
https://github.com/llvm/llvm-project/commit/6aeffa18e9ac51b7090325ea50d1841248a876c6
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/DriverUtils.cpp
M lld/test/ELF/reproduce.s
Log Message:
-----------
[ELF] --reproduce: strip directories for --dependency-file=
CMake may generate build.ninja with DEP_FILE specifying a non-existent
directory in the reproduce tarball.
Commit: e70f9e20964161abd3518d77b9efc736c6b6255e
https://github.com/llvm/llvm-project/commit/e70f9e20964161abd3518d77b9efc736c6b6255e
Author: Weining Lu <luweining at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[LoongArch] Remove the added in #116762
Commit: 02408d6b28951b2e094d00a70a398883c6b0cb33
https://github.com/llvm/llvm-project/commit/02408d6b28951b2e094d00a70a398883c6b0cb33
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
Log Message:
-----------
[VP] Refactoring some functions in ExpandVectorPredication.NFC (#115840)
Building vp intrinsic functions using a unified interface for
expandPredicationToIntCall/expandPredicationToFPCall/expandPredicationToCastIntrinsic
functions.
Commit: 5f3eab9e453c0237ccfafb6775b5af55bf028c84
https://github.com/llvm/llvm-project/commit/5f3eab9e453c0237ccfafb6775b5af55bf028c84
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRISelLowering.cpp
Log Message:
-----------
[AVR] Remove extra ROL / ROR operands (#117510)
The nodes have one input, shift amount of 1 is implied.
Commit: bb5bbe523d4437d72287f89fbaa277aaa71c0bd2
https://github.com/llvm/llvm-project/commit/bb5bbe523d4437d72287f89fbaa277aaa71c0bd2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support s32/s64 G_FSUB/FDIV/FNEG without F/D extensions.
Use libcalls for G_FSUB/FDIV. Use integer operations for G_FNEG.
Copy most of the IR tests for arithmetic from SelectionDAG.
Commit: 345ca6a69203fe8ad17cf35da88e6a490679a2e7
https://github.com/llvm/llvm-project/commit/345ca6a69203fe8ad17cf35da88e6a490679a2e7
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: extra signature conversion check (#117471)
This commit adds an extra assertion to `applySignatureConversion` to
prevent incorrect API usage: The same block cannot be converted multiple
times. That would mess with the underlying conversion value mapping.
(Mappings would be overwritten.) This is similar to op replacements: The
same op cannot be replaced multiple times.
To simplify the check, `BlockTypeConversionRewrite::block` now stores
the original block. The new block is stored in an extra field. (It used
to be the other way around.)
This commit is in preparation of adding 1:N support to the conversion
value mapping. Before making any further changes to the mapping
infrastructure, I'd like to make sure that the code base around it (that
uses the mapping) is robust.
Commit: 0bfc9514715b3beb967f1a245e9db310d2aafa50
https://github.com/llvm/llvm-project/commit/0bfc9514715b3beb967f1a245e9db310d2aafa50
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
Log Message:
-----------
[lldb] Remove lldbutil.get_stack_frames (NFC) (#117505)
`SBThread.frames` can be used instead of `get_stack_frames`.
Commit: e26af0938c7a272cf0de11c92aa069485868e130
https://github.com/llvm/llvm-project/commit/e26af0938c7a272cf0de11c92aa069485868e130
Author: hev <wangrui at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
Log Message:
-----------
[llvm] Add `BasicTTIImpl::areInlineCompatible` for target feature subset checks (#117493)
This patch moves the `areInlineCompatible` implementation from multiple
subclasses (`AArch64TTIImpl`, `RISCVTTIImpl`, `WebAssemblyTTIImpl`) to
the base class `BasicTTIImpl`. The new implementation checks whether the
callee's target features are a subset of the caller's, enabling
consistent behavior across targets. Subclasses now simply delegate to
the base implementation, reducing code duplication and improving
maintainability.
Commit: 3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
https://github.com/llvm/llvm-project/commit/3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
Log Message:
-----------
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
This makes (fcopysign X, (fneg Y)) patterns work.
Commit: 2523439021dedbaee1ddfc49f59deab43cf6bb9b
https://github.com/llvm/llvm-project/commit/2523439021dedbaee1ddfc49f59deab43cf6bb9b
Author: hev <wangrui at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll
A llvm/test/Transforms/Inline/LoongArch/lit.local.cfg
Log Message:
-----------
[LoongArch] Add a test case for inline compatibility checks (#117144)
Commit: 7317a6e99026f65a343e2e69685445dc5bd83172
https://github.com/llvm/llvm-project/commit/7317a6e99026f65a343e2e69685445dc5bd83172
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
A llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
Log Message:
-----------
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)
For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.
This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.
Commit: 87cc4b48c08a627f330396f941b84671c5e591d5
https://github.com/llvm/llvm-project/commit/87cc4b48c08a627f330396f941b84671c5e591d5
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
Log Message:
-----------
[NFC] Fix buildbot fail by add riscv64-registered-target
Commit: 9e3215ac167b80dcf51d6693ecdd6275c4e89954
https://github.com/llvm/llvm-project/commit/9e3215ac167b80dcf51d6693ecdd6275c4e89954
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[memprof] Add an assert to InstrProfWriter::addMemProfData (#117426)
This patch adds a quick validity check to
InstrProfWriter::addMemProfData. Specifically, we check to see if we
have all (or none) of the MemProf profile components (frames, call
stacks, records).
The credit goes to Teresa Johnson for suggesting this assert.
Commit: ff7b42c194e0fa23e6a76f0a33a80c0c3af14e7d
https://github.com/llvm/llvm-project/commit/ff7b42c194e0fa23e6a76f0a33a80c0c3af14e7d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Speed up llvm-profdata (#117446)
CallStackRadixTreeBuilder::build takes the parameter
MemProfFrameIndexes by value, involving copies:
std::optional<const llvm::DenseMap<FrameIdTy, LinearFrameId>>
MemProfFrameIndexes
Then "build" makes another copy of MemProfFrameIndexe and passes it to
encodeCallStack for every call stack, which is painfully slow.
This patch changes the type to a pointer so that we don't have to make
a copy every time we pass the argument.
Without this patch, it takes 553 seconds to run "llvm-profdata merge"
on a large MemProf raw profile. This patch shortenes that down to 67
seconds.
Commit: 73bebf96bc21dcc01a8eccfb4ece200c1c665931
https://github.com/llvm/llvm-project/commit/73bebf96bc21dcc01a8eccfb4ece200c1c665931
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Update the position of some parameters in the vp intrinsic of abs/cttz/ctlz (#117519)
Commit: b9731a479cb053cd07cc5f460b097c5f2d5f396e
https://github.com/llvm/llvm-project/commit/b9731a479cb053cd07cc5f460b097c5f2d5f396e
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/docs/ClangFormat.rst
M clang/include/clang/Format/Format.h
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format][doc] Minor cleanup
Commit: 2568e52a733a9767014e0d8ccb685553479a3031
https://github.com/llvm/llvm-project/commit/2568e52a733a9767014e0d8ccb685553479a3031
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
Log Message:
-----------
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part II) (#108812)
This is a follow up of #96878 to support hoisting load/store from BBs
have the same predecessor, if load/store are the only instructions and
the branch is unpredictable, e.g.:
```
void test (int a, int *c, int *d) {
if (a)
*c = a;
else
*d = a;
}
```
Commit: b0bdbf4288a664179024eead871a5e7b7fae6dda
https://github.com/llvm/llvm-project/commit/b0bdbf4288a664179024eead871a5e7b7fae6dda
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
Commit: 2585b6e8faf68d1d10ce0f356c4fede5876da6d2
https://github.com/llvm/llvm-project/commit/2585b6e8faf68d1d10ce0f356c4fede5876da6d2
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix layering check failure.
Commit: df335b09eac8a48d9afc06d71a86646ff6b08131
https://github.com/llvm/llvm-project/commit/df335b09eac8a48d9afc06d71a86646ff6b08131
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
Log Message:
-----------
[Clang] Preserve partially substituted pack indexing type/expressions (#116782)
Substituting into pack indexing types/expressions can still result in
unexpanded types/expressions, such as `PackIndexingType` or
`PackIndexingExpr`. To handle these cases correctly, we should defer the
pack size checks to the next round of transformation, when the patterns
can be fully expanded.
To that end, the `FullySubstituted` flag is now necessary for computing
the dependencies of `PackIndexingExprs`. Conveniently, this flag can
also represent the prior `ExpandsToEmpty` status with an additional
emptiness check. Therefore, I converted all stored flags to use
`FullySubstituted`.
Fixes https://github.com/llvm/llvm-project/issues/116105
Commit: 404d0e9966a46c29e6539e20d9295adcbc8bf9bf
https://github.com/llvm/llvm-project/commit/404d0e9966a46c29e6539e20d9295adcbc8bf9bf
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Bindings/Python/IRAttributes.cpp
Log Message:
-----------
[mlir] Adjust code flagged by ClangTidyPerformance (NFC).
We can allocate the size of the vector in advance.
Commit: 0fe12a7db3f6663c9f2572ff0232e56f1bd411ae
https://github.com/llvm/llvm-project/commit/0fe12a7db3f6663c9f2572ff0232e56f1bd411ae
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
Log Message:
-----------
[clang-format][NFC] Remove a pointer in ContinuationIndenter
Commit: 815a1bb53a9bb753f9aea177135150b23012550f
https://github.com/llvm/llvm-project/commit/815a1bb53a9bb753f9aea177135150b23012550f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
Log Message:
-----------
[SystemZ] Use getSignedConstant() where necessary (#117181)
This will avoid assertion failures once we disable implicit truncation
in getConstant().
Inside adjustSubwordCmp() I ended up suppressing the issue with an
explicit cast, because this code deals with a mix of unsigned and signed
immediates.
Commit: 3317c9ceac0f362298a0871e9d2bc30ef0f1e1b5
https://github.com/llvm/llvm-project/commit/3317c9ceac0f362298a0871e9d2bc30ef0f1e1b5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
Log Message:
-----------
[AMDGPU] Use getSignedConstant() where necessary (#117328)
Create signed constant using getSignedConstant(), to avoid future
assertion failures when we disable implicit truncation in getConstant().
This also touches some generic legalization code, which apparently only
AMDGPU tests.
Commit: 55f5d68c2da1b9dda522fdd862ed53f18166fa44
https://github.com/llvm/llvm-project/commit/55f5d68c2da1b9dda522fdd862ed53f18166fa44
Author: Hans <hans at hanshq.net>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] Recognize mov QWORD PTR [rip + X], reg (#117335)
This comes up when intercepting clang-built `__sanitizer_cov` functions.
Commit: 6512e488f6a118fc781fc39ccb79766e11359048
https://github.com/llvm/llvm-project/commit/6512e488f6a118fc781fc39ccb79766e11359048
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lld/ELF/InputSection.cpp
A lld/test/ELF/arm-rwpi-debug-relocs.s
Log Message:
-----------
[LLD][ARM] Allow R_ARM_SBREL32 relocations in debug info (#116956)
The R_ARM_SBREL32 relocation is used in debug info for ARM RWPI
(read-write position independent) code. Compiler-generated DWARF info
will use an expression to add the relocated value to the actual value of
the static base (held in r9) at run-time, so it should be relocated as
if the static base is at address 0.
Commit: 1bc98957c898d7e7233746a7b284982d20539593
https://github.com/llvm/llvm-project/commit/1bc98957c898d7e7233746a7b284982d20539593
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
[lldb/DWARF] Remove duplicate type filtering (#116989)
In #108907, the index classes started filtering the DIEs according to
the full type query (instead of just the base name). This means that the
checks in SymbolFileDWARF are now redundant.
I've also moved the non-redundant checks so that now all checking is
done in the DWARFIndex class and the caller can expect to get the final
filtered list of types.
Commit: 866755f8da588ec2efbcac60679b9d9f5c4636a9
https://github.com/llvm/llvm-project/commit/866755f8da588ec2efbcac60679b9d9f5c4636a9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update backend maintainer (#116622)
We currently list Evan Cheng as the fallback maintainer for the LLVM
backend. However, their last contribution dates back to 2014.
I'd like to nominate arsenm instead, who is our most active backend
reviewer.
Commit: d35098bfa8e1e213f85a6b5035a5a7102f5da315
https://github.com/llvm/llvm-project/commit/d35098bfa8e1e213f85a6b5035a5a7102f5da315
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/IR/AttrTypeBase.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
Log Message:
-----------
[mlir][LLVM][NFC] Move `LLVMStructType` to ODS (#117485)
This PR extracts NFC changes out of
https://github.com/llvm/llvm-project/pull/116035 to reap as many of the
same benefits without any of the semantic changes.
More concretely, moving `LLVMStructType` to ODS has the benefits of
being able to generate much of the required boilerplate, such as
interface definitions, documentation and more, automatically.
Furthermore, `LLVMStructType` is then treated less special and its
definition can be found at the same place where all other complex type
definitions are found in the LLVM dialect.
Future changes could leverage more automatically generated code from
TableGen such as `assemblyFormat`. As these are not as trivial, they
have been left for future PRs.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: 2b5e2d74d38274e783ccf0de37aa106c76816f9e
https://github.com/llvm/llvm-project/commit/2b5e2d74d38274e783ccf0de37aa106c76816f9e
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
Log Message:
-----------
[AArch64][GlobalISel] Extend arm64-vshift.ll test coverage. NFC
Commit: 7d8d51ed3409cae96fb975281deca2babf4f9994
https://github.com/llvm/llvm-project/commit/7d8d51ed3409cae96fb975281deca2babf4f9994
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-target-version-unsupported.c
Log Message:
-----------
Recommit "[TargetVersion] Only enable on RISC-V and AArch64" (#117110)" (#117128)
Remain InheritableAttr to avoid the warning `TypePrinter.cpp:1953:10:
warning: enumeration value ‘TargetVersion’ not handled in switch`
origin messenge
[TargetVersion] Only enable on RISC-V and AArch64 (#115991) Address
#115000.
This patch constrains the target_version feature to work only on RISC-V
and AArch64 to prevent crashes in Clang.
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: e5faeb69fbb87722ee315884eeef2089b10b0cee
https://github.com/llvm/llvm-project/commit/e5faeb69fbb87722ee315884eeef2089b10b0cee
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
Log Message:
-----------
[InstCombine] Support reassoc for foldLogicOfFCmps (#116065)
We currently support simple reassociation for foldAndOrOfICmps().
Support the same for foldLogicOfFCmps() by going through the common
foldBooleanAndOr() helper.
This will also resolve the regression on #112704, which is also due to
missing reassoc support.
I had to adjust one fold to add support for FMF flag preservation,
otherwise there would be test regressions. There is a separate fold
(reassociateFCmps) handling reassociation for *just* that specific case
and it preserves FMF. Unfortunately it's not rendered entirely redundant
by this patch, because it handles one more level of reassociation as
well.
Commit: 22ec44f509ff266b581dbb490d7b040473b7c31a
https://github.com/llvm/llvm-project/commit/22ec44f509ff266b581dbb490d7b040473b7c31a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
A llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)
For IR like this:
%icmp = icmp ult <4 x i32> %a, splat (i32 5)
%res = extractelement <4 x i1> %icmp, i32 1
where there is only one use of %icmp we can take a similar approach
to what we already do for binary ops such add, sub, etc. and convert
this into
%ext = extractelement <4 x i32> %a, i32 1
%res = icmp ult i32 %ext, 5
For AArch64 targets at least the scalar boolean result will almost
certainly need to be in a GPR anyway, since it will probably be
used by branches for control flow. I've tried to reuse existing code
in scalarizeExtractedBinop to also work for setcc.
NOTE: The optimisations don't apply for tests such as
extract_icmp_v4i32_splat_rhs in the file
CodeGen/AArch64/extract-vector-cmp.ll
because scalarizeExtractedBinOp only works if one of the input
operands is a constant.
Commit: 321fe747957703ec1d17b59b5e3ed96f58cfdb12
https://github.com/llvm/llvm-project/commit/321fe747957703ec1d17b59b5e3ed96f58cfdb12
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
Log Message:
-----------
[InstCombine] Add extra test for eq of parts fold (NFC)
To guard against regression from #112704.
Commit: db140104054d5af588e26c36ad5faadbb599de1e
https://github.com/llvm/llvm-project/commit/db140104054d5af588e26c36ad5faadbb599de1e
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/abs.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement cost of intrinsic abs with LMUL (#115813)
Commit: 84fec7757ea330bbaf82b46ed081ccc45b120e45
https://github.com/llvm/llvm-project/commit/84fec7757ea330bbaf82b46ed081ccc45b120e45
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lldb/docs/use/aarch64-linux.md
Log Message:
-----------
[lldb][docs] Clarify unit for SVE P register size
Commit: c537c752787e9da8bd8762dd5298a152f546861b
https://github.com/llvm/llvm-project/commit/c537c752787e9da8bd8762dd5298a152f546861b
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Log Message:
-----------
[AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
As with other operations we scalarize any vectors with larger types to let the
scalare legalization kick in.
Commit: f81f47e3ff29598fdf58cde94ccf2c7d4be53df5
https://github.com/llvm/llvm-project/commit/f81f47e3ff29598fdf58cde94ccf2c7d4be53df5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/fptrunc.ll
Log Message:
-----------
[InstCombine] Add fptrunc of max test (NFC)
To guard against regression from #117182.
Commit: 15fadeb2aa8b9f27a5a45f15832e73ef79cfe407
https://github.com/llvm/llvm-project/commit/15fadeb2aa8b9f27a5a45f15832e73ef79cfe407
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost for @llvm.experimental.vp.splat (#117313)
This is split off from #115274. There doesn't seem to be an easy way to
share this with getShuffleCost since that requires passing in a real
insert_element operand to get it to recognise it's a scalar splat.
For i1 vectors we can't currently lower them so it returns an invalid
cost.
---------
Co-authored-by: Shih-Po Hung <shihpo.hung at sifive.com>
Commit: 48ec59c234ce267a0454b15e9a79a326e21a4a97
https://github.com/llvm/llvm-project/commit/48ec59c234ce267a0454b15e9a79a326e21a4a97
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
Log Message:
-----------
[llvm][AMDGPU] Fold `llvm.amdgcn.wavefrontsize` early (#114481)
Fold `llvm.amdgcn.wavefrontsize` early, during InstCombine, so that it's
concrete value is used throughout subsequent optimisation passes.
Commit: 612f8ec7ac5dcddd16fb027aad64e2e353faa528
https://github.com/llvm/llvm-project/commit/612f8ec7ac5dcddd16fb027aad64e2e353faa528
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/flush_ast_print.cpp
M clang/test/OpenMP/flush_codegen.cpp
M clang/test/OpenMP/flush_messages.cpp
A flang/test/Lower/OpenMP/Todo/flush-seq-cst.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/flush02.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
seq_cst is allowed in Flush since OpenMP 5.1. (#114072)
This PR adds support seq_cst (sequential consistency) clause for the
flush directive in OpenMP. The seq_cst clause enforces a stricter memory
ordering, ensuring that all threads observe the memory effects of the
flush in the same order, improving consistency in memory operations
across threads.
---------
Co-authored-by: Shashwathi N <nshashwa at pe28vega.hpc.amslabs.hpecorp.net>
Co-authored-by: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Commit: e477989a055f92f6ca63fc8f76929cde81d33e44
https://github.com/llvm/llvm-project/commit/e477989a055f92f6ca63fc8f76929cde81d33e44
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
Log Message:
-----------
[InstCombine] Handle trunc i1 pattern in eq-of-parts fold (#112704)
Equality/inequality of the low bit can be represented by `(trunc (xor x,
y) to i1)`, possibly with an extra not. We have to handle this in the
eq-of-parts fold now that we no longer canonicalize this to a masked
icmp.
Proofs: https://alive2.llvm.org/ce/z/qidkzq
Fixes https://github.com/llvm/llvm-project/issues/110919.
Commit: ceaf6e912a846b88f19df682c6bdbe9516be04e9
https://github.com/llvm/llvm-project/commit/ceaf6e912a846b88f19df682c6bdbe9516be04e9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Support ImplicitValueInitExpr for multi-dim arrays (#117312)
The attached test case from
https://github.com/llvm/llvm-project/issues/117294 used to cause an
assertion because we called classifPrim() on an array type.
The new result doesn't crash but isn't exactly perfect either. Since the
problem arises when evaluating an ImplicitValueInitExpr, we have no
proper source location to point to. Point to the caller instead.
Commit: 535247841d8635bc998ec0ec4871ea22f27caba6
https://github.com/llvm/llvm-project/commit/535247841d8635bc998ec0ec4871ea22f27caba6
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Remove comments from generated validateOperandClass (#117352)
This generated comments like:
// 'BoolReg' class
case MCK_BoolReg: {
which seem redundant because the name is always repeated on the next
line as part of the MCK_ enumerator.
Commit: 8c5a3a97c0d061880d6705db8f000aa964c3e32d
https://github.com/llvm/llvm-project/commit/8c5a3a97c0d061880d6705db8f000aa964c3e32d
Author: Jefferson Le Quellec <jefferson.lequellec at codeplay.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/docs/PatternRewriter.md
Log Message:
-----------
[mlir][docs] Update MLIR's PatternRewriter documentation (#116183)
This PR adds the missing `const override` to the `rewrite` and
`matchAndRewrite` declaration in the Pattern Rewriter documentation as
described here:
https://github.com/llvm/llvm-project/blob/5cfa8baef33636827e5aa8dd76888c724433b53e/mlir/include/mlir/IR/PatternMatch.h#L237-L265
Commit: b5a11d378db4b39ceb085ebd59c941e9369d9596
https://github.com/llvm/llvm-project/commit/b5a11d378db4b39ceb085ebd59c941e9369d9596
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
[SelectOpt] Refactor to prepare for support more select-like operations (#115745)
* Enables conversion of several select-like instructions within one
group
* Any number of auxiliary instructions depending on the same condition
can be in between select-like instructions
* After splitting the basic block, move select-like instructions into
the relevant basic blocks and optimise them
* Make it easier to add support shift-base select-like instructions and
also any mixture of zext/sext/not instructions
Commit: 4b71b3782d217db0138b701c4514bd2168ca1659
https://github.com/llvm/llvm-project/commit/4b71b3782d217db0138b701c4514bd2168ca1659
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
A bolt/unittests/Core/MemoryMaps.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
Log Message:
-----------
[BOLT] DataAggregator support for binaries with multiple text segments (#92815)
When a binary has multiple text segments, the Size is computed as the
difference of the last address of these segments from the BaseAddress.
The base addresses of all text segments must be the same.
Introduces flag 'perf-script-events' for testing. It allows passing perf events
without BOLT having to parse them using 'perf script'. The flag is used to
pass a mock perf profile that has two memory mappings for a mock binary
that has two text segments. The size of the mapping is updated as this
change `parseMMapEvents` processes all text segments.
Commit: 957c2ac4f17ab5cc1e4a13c99ed968dcaac1dd91
https://github.com/llvm/llvm-project/commit/957c2ac4f17ab5cc1e4a13c99ed968dcaac1dd91
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M bolt/utils/bughunter.sh
Log Message:
-----------
[BOLT] Fix for bughunter.sh in offline mode (#116649)
In offline mode, the script sets 'PASS' variable and does not use it.
Surrounding code suggests using 'FAIL' variable instead.
Commit: b4d49fb52e2068cdf4944dc0783c3ef691c946c4
https://github.com/llvm/llvm-project/commit/b4d49fb52e2068cdf4944dc0783c3ef691c946c4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Remove RPC server API and use the header directly (#117075)
Summary:
This patch removes much of the `llvmlibc_rpc_server` interface. This
pretty much deletes all of this code and just replaces it with including
`rpc.h` directly. We still maintain the file to let `libc` handle the
opcodes, since those depend on the `printf` impelmentation.
This will need to be cleaned up more, but I don't want to put too much
into a single patch.
Commit: 0ccc3895126aaa94ae3fe890fcca0ad69658bbab
https://github.com/llvm/llvm-project/commit/0ccc3895126aaa94ae3fe890fcca0ad69658bbab
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc_util.h
Log Message:
-----------
[libc] Make RPC header work with GCC9
Commit: 52755ac2531529369f1f29b9d0b29645f304f389
https://github.com/llvm/llvm-project/commit/52755ac2531529369f1f29b9d0b29645f304f389
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/OpenMP/Todo/map-mapper.f90
M flang/test/Parser/OpenMP/from-clause.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
M flang/test/Parser/OpenMP/target-update-to-clause.f90
M flang/test/Semantics/OpenMP/combined-constructs.f90
M flang/test/Semantics/OpenMP/defaultmap-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/map-clause.f90
M flang/test/Semantics/OpenMP/map-modifiers.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
Log Message:
-----------
[flang][OpenMP] Use new modifier infrastructure for MAP/FROM/TO clauses (#117447)
This removes the specialized parsers and helper classes for these
clauses, namely ConcatSeparated, MapModifiers, and MotionModifiers. Map
and the motion clauses are now handled in the same way as all other
clauses with modifiers, with one exception: the commas separating their
modifiers are optional. This syntax is deprecated in OpenMP 5.2.
Implement version checks for modifiers: for a given modifier on a given
clause, check if that modifier is allowed on this clause in the
specified OpenMP version. This replaced several individual checks.
Add a testcase for handling map modifiers in a different order, and for
diagnosing an ultimate modifier out of position.
Commit: 506ca19dc9d6a9f0ad47b82e71525743bbe8cf85
https://github.com/llvm/llvm-project/commit/506ca19dc9d6a9f0ad47b82e71525743bbe8cf85
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/DeviceRTL/src/Mapping.cpp
M offload/test/offloading/ompx_bare_ballot_sync.c
M offload/test/offloading/ompx_bare_shfl_down_sync.cpp
Log Message:
-----------
[OpenMP] Remove use of '__AMDGCN_WAVEFRONT_SIZE' (#113156)
Summary:
This is going to be deprecated in
https://github.com/llvm/llvm-project/pull/112849. This patch ports it to
use the builtin instead. This isn't a compile constant, so it could
slightly negatively affect codegen. There really should be an IR pass to
turn it into a constant if the function has known attributes.
Using the builtin is correct when we just do it for knowing the size
like we do here. Obviously guarding w32/w64 code with this check would
be broken.
Commit: 4715dec8c0200d2c57176e08ce3d7ce88776828d
https://github.com/llvm/llvm-project/commit/4715dec8c0200d2c57176e08ce3d7ce88776828d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Log Message:
-----------
[XTensa] Use getSignedConstant() for negative values
Commit: 3699931dee058c02f52818529b4e6b53613a2dc2
https://github.com/llvm/llvm-project/commit/3699931dee058c02f52818529b4e6b53613a2dc2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
Log Message:
-----------
[M68k] Use getSignedConstant() where necessary
Commit: 18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
https://github.com/llvm/llvm-project/commit/18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Log Message:
-----------
[PatternMatch] Introduce m_c_Select (#114328)
This matches m_Select(m_Value(), L, R) or m_Select(m_Value(), R, L).
Commit: 9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
https://github.com/llvm/llvm-project/commit/9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
R llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
Revert "[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)" (#117556)
This reverts commit 22ec44f509ff266b581dbb490d7b040473b7c31a.
Commit: 6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
https://github.com/llvm/llvm-project/commit/6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/c23.c
Log Message:
-----------
[clang][bytecode] Use bitcasts to cast from integer to vector (#117547)
In C, a cast from an integer to a vector is a CK_BitCast. Implement this
using the same code we use for __builtin_bit_cast.
Commit: 2d62daab497bfe1991869dc090c7d20a71108360
https://github.com/llvm/llvm-project/commit/2d62daab497bfe1991869dc090c7d20a71108360
Author: David Truby <david.truby at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Fir/struct-return-aarch64.fir
Log Message:
-----------
[flang] AArch64 support for BIND(C) derived return types (#114051)
This patch adds support for BIND(C) derived types as return values
matching the AArch64 Procedure Call Standard for C.
Support for BIND(C) derived types as value parameters will be in a
separate patch.
Commit: 809c5ac3b0d78f504d93717ac4c0a02816cf47bb
https://github.com/llvm/llvm-project/commit/809c5ac3b0d78f504d93717ac4c0a02816cf47bb
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
[X86] Modify tests for constrained rounding functions (#116951)
The existing tests for constrained functions often use constant
arguments. If constant evaluation is enhanced, such tests will not check
code generation of the tested functions. To avoid it, the tests are
modified to use loaded value instead of constants. Now only the tests
for rounding functions are changed.
Commit: 06cb5c9d2c24e7560fcafd911fb145b96e96a675
https://github.com/llvm/llvm-project/commit/06cb5c9d2c24e7560fcafd911fb145b96e96a675
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update ARM maintainers (#117002)
Move rengolin and asl to former maintainers, and add davemgreen,
ostannard, nasherm, smithp35 and stuji from ARM as current
maintainers (with a focus area for some).
Commit: 4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
https://github.com/llvm/llvm-project/commit/4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
Revert "[SelectOpt] Refactor to prepare for support more select-like operations (#115745)"
This reverts commit b5a11d378db4b39ceb085ebd59c941e9369d9596.
Commit: a5506a39e0ae8de77136334659b526e5f224850d
https://github.com/llvm/llvm-project/commit/a5506a39e0ae8de77136334659b526e5f224850d
Author: Yadong Chen <cyd.matt at qq.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp assembly (#116943)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.
Changes:
updates the PtrAccessChainOp and InBoundPtrAccessChainOp defined in
SPIRVMemoryOps.td to use assemblyFormat. Removes part print/parse from
MemoryOps.cpp which is now generated by assemblyFormat
Updates tests to updated format
Issue: #73359
Commit: 6de97e9a679aaf3148d467e4d4e1ea99ba55d555
https://github.com/llvm/llvm-project/commit/6de97e9a679aaf3148d467e4d4e1ea99ba55d555
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/cmake/modules/prepare_libc_gpu_build.cmake
Log Message:
-----------
[libc] Allow NVPTX targets to build in debug mode
Summary:
This previously did not work, but recent improvements to the NVPTX
backend allow this to work now.
Commit: 387be04dde0a2618d2baf37a4652a076c003b4a2
https://github.com/llvm/llvm-project/commit/387be04dde0a2618d2baf37a4652a076c003b4a2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc.h
Log Message:
-----------
[libc][NFC] Add const to RPC header members
Summary:
Make sure that these don't get modified.
Commit: 7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
https://github.com/llvm/llvm-project/commit/7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
Author: thetruestblue <bblueconway at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/SanitizerCoverage.rst
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[SanitizerCoverage] Add gated tracing callbacks support to trace-cmp (#113227)
The option -sanitizer-coverage-gated-trace-callbacks gates the
invocation of the trace-pc-guard callbacks based on the value of a
global variable, which is stored in a specific section.
In this commit, we extend this feature to trace-cmp and gate the cmp
callbacks to the same variable used for trace-pc-guard.
Update SanitizerCoverage doc with this flag.
rdar://135404160
Patch by: Andrea Fioraldi
Commit: f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
https://github.com/llvm/llvm-project/commit/f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
Log Message:
-----------
[ADT] Add convenience function `filter_to_vector` (#117460)
This materializes a filter range as a small vector.
Similar to `map_to_vector`, this new utility function lives in the
`SmallVectorExtras.h` header.
Commit: 7e3187e12a2cef8b2552e08ce9423aca9c09d813
https://github.com/llvm/llvm-project/commit/7e3187e12a2cef8b2552e08ce9423aca9c09d813
Author: ddubov100 <155631080+ddubov100 at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Interfaces/TilingInterface.td
Log Message:
-----------
Adding mlir prefix for missing places in TilingInterface.td (#117495)
Commit: 57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
https://github.com/llvm/llvm-project/commit/57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
Log Message:
-----------
[SLP]Relax assertion in mask combine for non-power-of-2 number of elements
The nodes may contain non-power-of-2 number of elements. Need to relax
the assertion to avoid possible compiler crash
Fixes #117517
Commit: 1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
https://github.com/llvm/llvm-project/commit/1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
Log Message:
-----------
[X86] vector-interleaved-load-i16-stride-2.ll - regenerate with AVX512 common prefix
Commit: 4d8eb009d8ae4500940d77a64d914eed9a13b92c
https://github.com/llvm/llvm-project/commit/4d8eb009d8ae4500940d77a64d914eed9a13b92c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Remove SPF guard for trunc transforms (#117535)
This shouldn't be necessary anymore now that SPF patterns are
canonicalized to intrinsics.
Commit: 3de21477c49172081e502b47d608e729915f0914
https://github.com/llvm/llvm-project/commit/3de21477c49172081e502b47d608e729915f0914
Author: Viktoriia Bakalova <115406782+VitaNuo at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[clang][codegen] Mention the invariant that LLVM demangler should be … (#117346)
…able to handle mangled names generated by clang.
https://discourse.llvm.org/t/rfc-clang-diagnostic-for-demangling-failures/82835/8
Since we're putting the work on the above RFC on hold, let's leave a
comment in the source code pointing to prior efforts and the suggestion
of further steps.
Commit: f953b5eb72df77fc301aac210eab31c6270ff771
https://github.com/llvm/llvm-project/commit/f953b5eb72df77fc301aac210eab31c6270ff771
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
Log Message:
-----------
[SLP]Relax assertion about subvectors mask size
SubVectorsMask might be less than CommonMask, if the vectors with larger
number of elements are permuted or reused elements are used. Need to
consider this when estimation/building the vector to avoid compiler
crash
Fixes #117518
Commit: b872c4c9939999d8c588ca4e149e2b0b40773ebf
https://github.com/llvm/llvm-project/commit/b872c4c9939999d8c588ca4e149e2b0b40773ebf
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/test/Driver/print-supported-cpus.f90
Log Message:
-----------
[flang][Driver] Fix incorrect condition in test
The conditions in a test did not match the target that was being
requested. This resulted in a test failure when building with
-DTARGETS_TO_BUILD=X86. This is now fixed.
Commit: c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
https://github.com/llvm/llvm-project/commit/c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir] Improve doc in `OpFormatGen.cpp` (NFC) (#117564)
The comment is misleading because attributes do not have
`elidePrintingDefaultValue` bit. It appears that
`elidePrintingDefaultValue` was never merged upstream (see:
https://reviews.llvm.org/D135398 ), but the comment was likely
introduced by mistake in a later revision
(https://reviews.llvm.org/D135993.).
Commit: 99fd1c5536547ed4fc360b16e7fa2e06278707a8
https://github.com/llvm/llvm-project/commit/99fd1c5536547ed4fc360b16e7fa2e06278707a8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libcxx/include/__chrono/duration.h
Log Message:
-----------
[libc++][NFC] Don't add legacy transitive includes in <__chrono/duration.h>
Commit: 20bd029a40faa2ae5383dd742b8a3595b1fe7c31
https://github.com/llvm/llvm-project/commit/20bd029a40faa2ae5383dd742b8a3595b1fe7c31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote fldexp with Zfh. (#117396)
The default expansion tries to create i16 operations after type
legalization.
Fixes #117349
Commit: 3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
https://github.com/llvm/llvm-project/commit/3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)
The 2-pass XDL write VGPR, read by non-XDL SGEMM/DGEMM case
was 1 wait state overly conservative. Previously, for gfx940,
the XDL/non-XDL cases happened to have the same number of cycles
in all cases. Now the XDL consumer case has an additional state for
2 pass sources.
Commit: c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
https://github.com/llvm/llvm-project/commit/c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
Log Message:
-----------
AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)
Confusingly, this is a different hazard to the one on gfx10
with a subtarget feature.
Commit: 27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
https://github.com/llvm/llvm-project/commit/27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
Log Message:
-----------
AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)
Commit: 8a2311c4bf9993230e37dc20b57973dc917f2338
https://github.com/llvm/llvm-project/commit/8a2311c4bf9993230e37dc20b57973dc917f2338
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
[Offload] Introduce offload-tblgen and initial new API implementation (#108413)
Introduce `offload-tblgen` and an initial implementation of a subset of
the new API. The tablegen files are intended to be the single source of
truth for the new API, with the header files, documentation, and others
bits of source all automatically generated.
**TODO** (based on review feedback so far):
- [x] Check in the generated headers
- [x] Add an `offload-generate` target to trigger the generation rather
than building them every time
- [x] Decide how error handling should work
- [x] Finish up new error handling implementation
- [x] Decide naming convention
- [x] Add testing for the new API
- [x] Add tablegen specific testing
- [x] clang-tidy and use llvm:: types when possible
- [x] Add optional code location arguments
- [x] Avoid multiple returns from one function
### offload-tblgen
See the included
[README](https://github.com/callumfare/llvm-project/blob/d80db06491d85444bb6f7e59d8068a22cef3a6b4/offload/new-api/API/README.md)
for more information on how the API definition and generation works. I'm
happy to answer any questions about it and plan to walk through it in a
future LLVM Offload call.
It should be noted that struct definitions have not been fully
implemented/tested as they aren't used by the initial API definitions,
but finishing that off in the future shouldn't be too much work.
The tablegen tooling has been designed to be easily extended with new
backends, using the classes in `RecordTypes.hpp` to abstract over the
tablegen records.
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
$ git clone -b offload_adapter https://github.com/callumfare/unified-runtime.git
$ cd unified-runtime
$ mkdir build
$ cd build
$ cmake .. -GNinja -DUR_BUILD_ADAPTER_OFFLOAD=ON \
-DUR_OFFLOAD_INSTALL_DIR=<offload build dir containing liboffload_new.so> \
-DUR_OFFLOAD_INCLUDE_DIR=<offload build dir containing 'offload' headers directory>
$ ninja urinfo
export LD_LIBRARY_PATH=<offload build dir containing offload plugin libraries>
$ UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
[cuda:gpu][cuda:0] CUDA, NVIDIA GeForce GT 1030 [12030]
# Demo with tracing
$ OFFLOAD_TRACE=1 UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
---> offloadPlatformGet(.NumEntries = 0, .phPlatforms = {}, .pNumPlatforms = 0x7ffd05e4d6e0 (2))-> OFFLOAD_RESULT_SUCCESS
---> offloadPlatformGet(.NumEntries = 2, .phPlatforms = {0x564bf4040220, 0x564bf4040240}, .pNumPlatforms = nullptr)-> OFFLOAD_RESULT_SUCCESS
...
```
### Open questions and future work
* The new API is implemented in a separate library
(`liboffload_new.so`). It could just as easily be part of the existing
`libomptarget` library - I have no strong feelings on which is better.
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: 9cc2502c048b1403ba8ba5cc5a655d867c329d12
https://github.com/llvm/llvm-project/commit/9cc2502c048b1403ba8ba5cc5a655d867c329d12
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-linux.c
Log Message:
-----------
[clang] hexagon: fix link order for libc/builtins (#117057)
When linking programs with `eld`, we get a link error like below:
Error:
/inst/clang+llvm-19.1.0-cross-hexagon-unknown-linux-musl/x86_64-linux-gnu/bin/../target/hexagon-unknown-linux-musl//usr/lib/libc.a(scalbn.lo)(.text.scalbn+0x3c):
undefined reference to `__hexagon_muldf3'
libc has references to the clang_rt builtins library, so the order of
the libraries should be reversed.
Commit: d88ed9357a0e4a49ce908c538ef21c1702c34638
https://github.com/llvm/llvm-project/commit/d88ed9357a0e4a49ce908c538ef21c1702c34638
Author: Raphael Moreira Zinsly <6718397+rzinsly at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
Log Message:
-----------
[NFC][RISCV] Refactor allocation of the stack space (#116625)
Separates the stack allocations from prologue in preparation for the
stack clash protection support.
Commit: e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
https://github.com/llvm/llvm-project/commit/e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
Log Message:
-----------
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
This patch support for intrinsics in clang, as well as assembly
instructions in the backend.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
https://github.com/llvm/llvm-project/commit/6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8ea78002c2637faf56ed5c0c88582fdd4f0ac701
https://github.com/llvm/llvm-project/commit/8ea78002c2637faf56ed5c0c88582fdd4f0ac701
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Add test case for RVV CSRs with cm.push.
The cfi_offset is incorrect for the RVV registers when cm.push
is used.
Commit: 7ad1084b521ea191245c47b4e63e4f97035e3786
https://github.com/llvm/llvm-project/commit/7ad1084b521ea191245c47b4e63e4f97035e3786
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (#117380)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 91af15b7648a10c3edcd9792b3f3487be399233b
https://github.com/llvm/llvm-project/commit/91af15b7648a10c3edcd9792b3f3487be399233b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (#117381)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8997bf8e4636592ca0e4f31747adc02904d47b0c
https://github.com/llvm/llvm-project/commit/8997bf8e4636592ca0e4f31747adc02904d47b0c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (#117382)
OPSEL[3] selects low/high 16 bits of dest write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 70fef78329eb4da338ef8345b5059f9a57ff21a5
https://github.com/llvm/llvm-project/commit/70fef78329eb4da338ef8345b5059f9a57ff21a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (#117383)
OPSEL[0] selects srcword to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 362d8fb2416ca3393b960eb158301d6f06dc5324
https://github.com/llvm/llvm-project/commit/362d8fb2416ca3393b960eb158301d6f06dc5324
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (#117384)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 00770489e4299fe6ab99b1772127d84dfe222ffc
https://github.com/llvm/llvm-project/commit/00770489e4299fe6ab99b1772127d84dfe222ffc
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/InitPreprocessor.cpp
A clang/test/C/C23/n2412.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
Log Message:
-----------
[C23] Fixed the value of BOOL_WIDTH (#117364)
The standard mandates that this returns the width of the type, which is
the number of bits in the value. For bool, that's required to be `1`
explicitly.
Fixes #117348
Commit: 0a140c4248b5eae5c044de4f394852ee7339a5e8
https://github.com/llvm/llvm-project/commit/0a140c4248b5eae5c044de4f394852ee7339a5e8
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
Log Message:
-----------
[AMDGPU] Adds pre-commit test for fmul-select combine (#111107)
This adds the f32/f64/f16/bf16 test cases for below pattern :
`fmul x, select(y, A, B)`
with just one use of select Inst above.
It acts as pre-commit tests for dagCombining above pattern into cheaper
ldexp in case of non-inlline 32 bit-constants. (#111109)
Commit: 29828b26fac3ee744c8f7dcb33cc082dc7c00a02
https://github.com/llvm/llvm-project/commit/29828b26fac3ee744c8f7dcb33cc082dc7c00a02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_offset for RVV CSRs. (#117408)
getCalleeSavedStackSize() already contains RVPushStackSize. Don't
subtract it again.
Commit: d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
https://github.com/llvm/llvm-project/commit/d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
A libc/shared/rpc_opcodes.h
M libc/src/__support/RPC/rpc_client.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc][NFC] Move RPC opcodes to the 'shared/' directory as well
Commit: 1a86d44c80d2a0c603f67ed8bdcccaed830719a3
https://github.com/llvm/llvm-project/commit/1a86d44c80d2a0c603f67ed8bdcccaed830719a3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (#117417)
OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d]
where, c & d i.e. OPSEL[3 : 2] selects which dst_byte to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 3cb28522ba4c2b80fbaf0840377aab4fce985110
https://github.com/llvm/llvm-project/commit/3cb28522ba4c2b80fbaf0840377aab4fce985110
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Reapply "[runtimes] Allow building against an installed LLVM tree"
This relands #86209 which was reverted because ./bin/llvm no longer
accepted test paths in the source tree instead of the build tree. This was
happening because `add_subdirectory(${LLVM_MAIN_SRC_DIR}/utils/llvm-lit`
was called before all tsst suites were registered, and therefore it was
missing the source->build dir mappings.
Original commit message:
I am currently trying to test the LLVM runtimes (including compiler-rt)
against an installed LLVM tree rather than a build tree (since that is
no longer available). Currently, the runtimes build of compiler-rt assumes
that LLVM_BINARY_DIR is writable since it uses configure_file() to write
there during the CMake configure stage. Instead, generate this file inside
CMAKE_CURRENT_BINARY_DIR, which will match LLVM_BINARY_DIR when invoked
from llvm/runtimes/CMakeLists.txt.
I also needed to make a minor change to the hwasan tests: hwasan_symbolize
was previously found in the LLVM_BINARY_DIR, but since it is generated as
part of the compiler-rt build it is now inside the CMake build directory
instead. I fixed this by passing the output directory to lit as
config.compiler_rt_bindir and using llvm_config.add_tool_substitutions().
For testing that we no longer write to the LLVM install directory as
part of testing or configuration, I created a read-only bind mount and
configured the runtimes builds as follows:
```
$ sudo mount --bind --read-only ~/llvm-install /tmp/upstream-llvm-readonly
$ cmake -DCMAKE_BUILD_TYPE=Debug \
-DCMAKE_C_COMPILER=/tmp/upstream-llvm-readonly/bin/clang \
-DCMAKE_CXX_COMPILER=/tmp/upstream-llvm-readonly/bin/clang++ \
-DLLVM_INCLUDE_TESTS=TRUE -DLLVM_ENABLE_ASSERTIONS=TRUE \
-DCOMPILER_RT_INCLUDE_TESTS=TRUE -DCOMPILER_RT_DEBUG=OFF \
-DLLVM_ENABLE_RUNTIMES=compiler-rt \
-DCMAKE_DISABLE_FIND_PACKAGE_LLVM=TRUE \
-DCMAKE_DISABLE_FIND_PACKAGE_Clang=TRUE \
-G Ninja -S ~/upstream-llvm-project/runtimes \
-B ~/upstream-llvm-project/runtimes/cmake-build-debug-llvm-git
```
Pull Request: https://github.com/llvm/llvm-project/pull/114307
Commit: d047bee496e07748f0dd70f52c3b309c66fedab3
https://github.com/llvm/llvm-project/commit/d047bee496e07748f0dd70f52c3b309c66fedab3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "[Offload] Introduce offload-tblgen and initial new API implementation (#108413)"
This reverts commit 8a2311c4bf9993230e37dc20b57973dc917f2338.
Commit: a5dd6463608bb09404e8a898ed337ef0b4a292c4
https://github.com/llvm/llvm-project/commit/a5dd6463608bb09404e8a898ed337ef0b4a292c4
Author: B I Mohammed Abbas <bimohammadabbas at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
Log Message:
-----------
Add extendhfxf2 into compiler rt (#113897)
Retry of pr #109090 and #111099.
Co-authored-by: Alexander Richardson <alexrichardson at google.com>
Commit: ed6749a4055c8b1500b39ebd4a8b981bf25250e8
https://github.com/llvm/llvm-project/commit/ed6749a4055c8b1500b39ebd4a8b981bf25250e8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote frexp with Zfh.
The default expansion tries to create an illegal integer type after
legalization.
Commit: b0bc4674b761a71974e561184d055ac8159fd578
https://github.com/llvm/llvm-project/commit/b0bc4674b761a71974e561184d055ac8159fd578
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
Log Message:
-----------
[X86] Fix bad instregex in VPMOVSX/ZX znver4 512-bit patterns.
The Z size was optional, meaning it matched with the 128-bit SSE instructions as well.
Noticed while triaging the strange perf numbers on #110308
Commit: bb88fd171a6be892cec36969860a9034b48b8656
https://github.com/llvm/llvm-project/commit/bb88fd171a6be892cec36969860a9034b48b8656
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A clang/test/CodeGenHLSL/resource-bindings.hlsl
M llvm/docs/DirectX/DXILResources.rst
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
Log Message:
-----------
[DirectX] Calculate resource binding offsets using the lower bound (#117303)
In the DXIL CreateHandle and CreateHandleFromBinding ops, resource
bindings are
indexed from the beginning of the binding space, not from the binding
itself.
Translate from an index into the binding to one from the beginning of
the space
when lowering to these operations.
Commit: fdf1f69c57ac3667d27c35e097040284edb1f574
https://github.com/llvm/llvm-project/commit/fdf1f69c57ac3667d27c35e097040284edb1f574
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/Generic/cgdata-merge-local.ll
A llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
[CGData][GMF] Skip No Params (#116548)
This update follows up on change #112671 and is mostly a NFC, with the following exceptions:
- Introduced `-global-merging-skip-no-params` to bypass merging when no parameters are required.
- Parameter count is now calculated based on the unique hash count.
- Added `-global-merging-inst-overhead` to adjust the instruction overhead, reflecting the machine instruction size.
- Costs and benefits are now computed using the double data type. Since the finalization process occurs offline, this should not significantly impact build time.
- Moved a sorting operation outside of the loop.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: b0ca543532d13fde8907853f6c9909ad7e68cd9f
https://github.com/llvm/llvm-project/commit/b0ca543532d13fde8907853f6c9909ad7e68cd9f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove dead code in MemProfReader (NFC) (#117607)
The only constructor in current use is the one that takes
IndexedMemProfData. Likewise, the only accessor in current use is
takeMemProfData.
Commit: fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
https://github.com/llvm/llvm-project/commit/fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
R llvm/test/CodeGen/Generic/cgdata-merge-local.ll
R llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
Revert "[CGData][GMF] Skip No Params (#116548)"
This reverts commit fdf1f69c57ac3667d27c35e097040284edb1f574.
Commit: c94d715867ef73d57f6bbe2bd7fbda3328ab1d1d
https://github.com/llvm/llvm-project/commit/c94d715867ef73d57f6bbe2bd7fbda3328ab1d1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
Log Message:
-----------
[RISCV] Add coverage for immediate sinking in switch vs branch cases
This come up in the context of pr 108889. We always end up sinking
the value in the phi if we dispatched via a switch, but not if we'd
dispatched via a branch. This is purely an artifact of current
lowering.
Commit: d733fa1c90e36aa39b111fab6a573eaab62d960b
https://github.com/llvm/llvm-project/commit/d733fa1c90e36aa39b111fab6a573eaab62d960b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)
We can move the logic from adjustStackForRVV into adjustReg, which
results in the remaining logic being trivially inlined to the two
callers and allows a duplicate copy of the same logic in
eliminateFrameIndex to be pruned.
Commit: 5001f1605893f21b1ae9defd82ee02999164f996
https://github.com/llvm/llvm-project/commit/5001f1605893f21b1ae9defd82ee02999164f996
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (#117418)
OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8e510b8472580388272a0621f79ec0346d9909af
https://github.com/llvm/llvm-project/commit/8e510b8472580388272a0621f79ec0346d9909af
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Fix a warning
This patch fixes:
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:476:25: error: unused
variable 'ST' [-Werror,-Wunused-variable]
Commit: deab4e9ab26d6e2c095c04821d17c68cca43a174
https://github.com/llvm/llvm-project/commit/deab4e9ab26d6e2c095c04821d17c68cca43a174
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocatable.h
Log Message:
-----------
[flang][cuda][NFC] Add missing default values (#117610)
Make it homogenous with other runtime entry points.
Commit: 96547decd5f12c4357b104d107350c8a14b47650
https://github.com/llvm/llvm-project/commit/96547decd5f12c4357b104d107350c8a14b47650
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
A llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions-obj-test.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/doubles.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/no_flags.ll
Log Message:
-----------
[DirectX] Infrastructure to collect shader flags for each function (#112967)
Currently, ShaderFlagsAnalysis pass represents various module-level
properties as well as function-level properties of a DXIL Module using a
single mask. However, one mask per function is needed for accurate
computation of shader flags mask, such as for entry function metadata
creation.
This change introduces a structure that wraps a sorted vector of
function-shader flag mask pairs that represent function properties
instead of a single shader flag mask that represents module properties
and properties of all functions. The result type of ShaderFlagsAnalysis
pass is changed to newly-defined structure type instead of a single
shader flags mask.
This allows accurate computation of shader flags of an entry function
(and all functions in a library shader) for use during its metadata
generation (DXILTranslateMetadata pass) and its feature flags in DX
container globals construction (DXContainerGlobals pass) based on the
shader flags mask of functions. However, note that the change to
implement propagation of such callee-based shader flags mask computation
is planned in a follow-on PR. Consequently, this PR changes shader flag
mask computation in DXILTranslateMetadata and DXContainerGlobals passes
to simply be a union of module flags and shader flags of all functions,
thereby retaining the existing effect of using a single shader flag
mask.
Commit: 466ff3ed70e50343c9617de318e1b40efa03529d
https://github.com/llvm/llvm-project/commit/466ff3ed70e50343c9617de318e1b40efa03529d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark VPIRInstruction::getInstruction) as const (NFCI).
Split off from https://github.com/llvm/llvm-project/pull/114292.
Commit: 30af6fb163add17a6be515200881afdff91d213a
https://github.com/llvm/llvm-project/commit/30af6fb163add17a6be515200881afdff91d213a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Group together helpers for retrieving various VPBlocks (NFCI).
Group together functions to retrieve various blocks of a VPlan, as
suggested in https://github.com/llvm/llvm-project/pull/114292.
Commit: 9de73b20404f0b2db1cbf70d164cfe0789d5bb94
https://github.com/llvm/llvm-project/commit/9de73b20404f0b2db1cbf70d164cfe0789d5bb94
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-string.test
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
Log Message:
-----------
[DWARF] Fix DWARTTypePrinter unable to print qualified name for DW_TAG_typedef DIE (#117239)
Fix a bug introduced in
https://github.com/llvm/llvm-project/pull/117071.
Ideally the DWARTTypePrinter test should go to
`llvm/unittests/DebugInfo/DWARF/DWARTTypePrinterTest.cpp`.
Commit: fe69a20cc1e46bf8473aaef1be8a1805c80fc9d4
https://github.com/llvm/llvm-project/commit/fe69a20cc1e46bf8473aaef1be8a1805c80fc9d4
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/AArch64/cgdata-merge-crash.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-local.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-no-params.ll
R llvm/test/CodeGen/Generic/cgdata-merge-crash.ll
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
Reland [CGData][GMF] Skip No Params (#116548)
This update follows up on change #112671 and is mostly a NFC, with the following exceptions:
- Introduced `-global-merging-skip-no-params` to bypass merging when no parameters are required.
- Parameter count is now calculated based on the unique hash count.
- Added `-global-merging-inst-overhead` to adjust the instruction overhead, reflecting the machine instruction size.
- Costs and benefits are now computed using the double data type. Since the finalization process occurs offline, this should not significantly impact build time.
- Moved a sorting operation outside of the loop.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: 1df34f12421317a365db96de9b713342c32c13b7
https://github.com/llvm/llvm-project/commit/1df34f12421317a365db96de9b713342c32c13b7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
Log Message:
-----------
[MCA][X86] Add avx512 test coverage for VPMOV truncation instructions
We only had partial VPMOVWB test coverage
Commit: 0988bf8d75de2f55484db02391db5165e7b7d37d
https://github.com/llvm/llvm-project/commit/0988bf8d75de2f55484db02391db5165e7b7d37d
Author: Robert Barinov <robert.barinov at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/tools/llvm-reduce/distinct-dimetadata-nullptr.ll
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
Log Message:
-----------
[LLVM-Reduce] - Null pointer handling during distinct metadata reduction (#117570)
Some distinct metadata nodes, e.g DICompileUnit, have implicit nullptrs
inside them. Iterating over them with dyn_cast leads to a crash, change
the behavior so that the nullptr operands are skipped.
Add the test distinct-metadata-nullptr.ll which will crash if null
pointers are not handled correctly.
Commit: 935da49a4d02316cbd0458d09d5913b6d1cabddc
https://github.com/llvm/llvm-project/commit/935da49a4d02316cbd0458d09d5913b6d1cabddc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Log Message:
-----------
AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)
I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.
Commit: ece4e1276e2140d84b05b8c430a0e547a1f23210
https://github.com/llvm/llvm-project/commit/ece4e1276e2140d84b05b8c430a0e547a1f23210
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[mlir][Affine] Split off delinearize parts that depend on last component (#117015)
If we have
%0 = affine.linearize_index disjoint [%a, %b] by (A, B)
%1:3 = affine.delinearize_index %0 into (A, B1, B2)
where B = B1 * B2 (or some mor complex product), we can simplify this to
%0 = affine.linearize_index disjoint [%a] by (A)
%1a:1 = affine.delinearize_index %0 into (A)
%1b:2 = affine.delinearize_index %b into (B1, B2)
This, and more complex cases, prevent us from adding terms together only
to divide them away from each other.
---------
Co-authored-by: Abhishek Varma <abhvarma at amd.com>
Commit: 76f0ff8210d56a050d2679926a2fdddd3a8c16d6
https://github.com/llvm/llvm-project/commit/76f0ff8210d56a050d2679926a2fdddd3a8c16d6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Add an extra check to avoid infinite vectorization attempts
Added extra check for the cost of the buildvector if the -slp-threshold
option is used. Prevents infinite vectorization attempts.
Commit: ab4e06667dbd777f32061ac3fff69328dc787fce
https://github.com/llvm/llvm-project/commit/ab4e06667dbd777f32061ac3fff69328dc787fce
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/test/MC/ELF/relocation.s
Log Message:
-----------
[X86][MC] Add R_X86_64_CODE_6_GOTTPOFF (#117277)
For
add %reg1, name at GOTTPOFF(%rip), %reg2
add name at GOTTPOFF(%rip), %reg1, %reg2
{nf} add %reg1, name at GOTTPOFF(%rip), %reg2
{nf} add name at GOTTPOFF(%rip), %reg1, %reg2
{nf} add name at GOTTPOFF(%rip), %reg
add
`R_X86_64_CODE_6_GOTTPOFF` = 50
if the instruction starts at 6 bytes before the relocation offset. It's
similar to R_X86_64_GOTTPOFF.
Linker can treat `R_X86_64_CODE_6_GOTTPOFF` as `R_X86_64_GOTTPOFF` or
convert the instructions above to
add $name at tpoff, %reg1, %reg2
add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg
if the first byte of the instruction at the relocation `offset - 6` is
`0xd5` (namely, encoded w/REX2 prefix) when possible.
Binutils patch:
https://github.com/bminor/binutils-gdb/commit/5bc71c2a6b8efb27089baa1fecded82be4f550a7
Binutils mailthread:
https://sourceware.org/pipermail/binutils/2024-February/132351.html
ABI discussion:
https://groups.google.com/g/x86-64-abi/c/FhEZjCtDLFw/m/VHDjN4orAgAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: 4c91662a519705c2d0b6e002214a3e307f09b373
https://github.com/llvm/llvm-project/commit/4c91662a519705c2d0b6e002214a3e307f09b373
Author: Caslyn Tonelli <6718161+Caslyn at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/src/__support/common.h
Log Message:
-----------
[libc] Resolve multi-line comment error (#117636)
gcc interprets a backslash '\\' as the last char before a new line as a
line continuation character, even in a comment context. This can produce
an "error: multi-line comment [-Werror=comment]".
This removes the line continuation so that the comment can compile with
gcc.
Commit: 1973270fc66680e6894c3ae9395a7e07e7b4d43c
https://github.com/llvm/llvm-project/commit/1973270fc66680e6894c3ae9395a7e07e7b4d43c
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/src/string/memory_utils/op_x86.h
Log Message:
-----------
[libc] suppress string warning in case intrinsics are defined as macros (#117640)
Commit: 32432a6a02fe41fa83fef6605489744957dc1b0a
https://github.com/llvm/llvm-project/commit/32432a6a02fe41fa83fef6605489744957dc1b0a
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
Log Message:
-----------
[libc] suppress math library warnings on windows (#117638)
Commit: 1ea7ced7eebf26aba1938d84ba99e2e6421c503c
https://github.com/llvm/llvm-project/commit/1ea7ced7eebf26aba1938d84ba99e2e6421c503c
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/python/mlir/_mlir_libs/__init__.py
Log Message:
-----------
[mlir][py] Enable disabling loading all registered (#117643)
There is a pending todo about always eagerly loading or not. Make this
behavior optional and give the control to the user in a backwards
compatible manner. This is made optional as there were arguments for
both forms, kept it in form that is backwards compatible.
Commit: 97fe5fa54c2e99dc0fe14fff1940b31bf697eff2
https://github.com/llvm/llvm-project/commit/97fe5fa54c2e99dc0fe14fff1940b31bf697eff2
Author: Kai Luo <gluokai at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/Driver/cuda-no-threadsafe-statics.cu
Log Message:
-----------
[Driver] Pass `--cuda-path` to test (#117415)
My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0 (inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-path' to specify a different CUDA install, pass a different GPU arch with '--cuda-gpu-arch', or pass '--no-cuda-version-check'
```
Fix it by passing `--cuda-path`. Hope this doesn't affect the original
intention of the test.
Commit: cac978331f533c53b3f909dde673bb2d7b2ccede
https://github.com/llvm/llvm-project/commit/cac978331f533c53b3f909dde673bb2d7b2ccede
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
A clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
R llvm/test/CodeGen/DirectX/updateCounter.ll
Log Message:
-----------
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffers (#117608)
Introduces `__builtin_hlsl_buffer_update_counter` clang buildin that is
used to implement the `IncrementCounter` and `DecrementCounter` methods
on `RWStructuredBuffer` and `RasterizerOrderedStructuredBuffer` (see
Note).
The builtin is translated to LLVM intrisic `llvm.dx.bufferUpdateCounter`
or `llvm.spv.bufferUpdateCounter`.
Introduces `BuiltinTypeMethodBuilder` helper in `HLSLExternalSemaSource`
that enables adding methods to builtin types using builder pattern like
this:
```
BuiltinTypeMethodBuilder(Sema, RecordBuilder, "MethodName", ReturnType)
.addParam("param_name", Type, InOutModifier)
.callBuiltin("buildin_name", { BuiltinParams })
.finalizeMethod();
```
Fixes #113513
[First version](llvm/llvm-project#114148) of this PR was reverted
because of build break.
Commit: c2bb056482212a6afa91f6d52274fe0a74b91720
https://github.com/llvm/llvm-project/commit/c2bb056482212a6afa91f6d52274fe0a74b91720
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
Log Message:
-----------
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
A special case in type legalization wasn't accounting for different
operand numbering between FLDEXP and STRICT_FLDEXP.
AArch64 already asked STRICT_FLDEXP to be promoted, but had no test for
it.
Commit: 2ab84a60ff88279884ca1b2a1655bd9f119bc803
https://github.com/llvm/llvm-project/commit/2ab84a60ff88279884ca1b2a1655bd9f119bc803
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/Analysis/CostModel/X86/fptoi_sat.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/pr114520.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
M llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
Log Message:
-----------
[X86][FP16][BF16] Improve vectorization of fcmp (#116153)
Commit: c1a3960abe5ca316e9a26e87cdc3a7f94e420dc6
https://github.com/llvm/llvm-project/commit/c1a3960abe5ca316e9a26e87cdc3a7f94e420dc6
Author: Daniel Zabawa <daniel.zabawa at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrPredicates.td
A llvm/test/CodeGen/X86/apx/imulzu.ll
Log Message:
-----------
[X86] Add APX imulzu support. (#116806)
Add patterns to select 16b imulzu with -mapx-feature=zu, including
folding of zero-extends of the result. IsDesirableToPromoteOp is changed
to leave 16b multiplies by constant un-promoted, as imulzu will not
cause partial-write stalls.
Commit: 2ed8c5de585491182486f392a5a570cc5c4474df
https://github.com/llvm/llvm-project/commit/2ed8c5de585491182486f392a5a570cc5c4474df
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
A flang/test/Transforms/OpenMP/lower-workshare-nested.mlir
Log Message:
-----------
[flang][OpenMP] Fix handling of nested loop wrappers in LowerWorkshare (#117275)
Commit: ebcaa577158de095f0093025ae1127d211a2a535
https://github.com/llvm/llvm-project/commit/ebcaa577158de095f0093025ae1127d211a2a535
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Log Message:
-----------
[GISel] #undef macros when they are no longer needed. NFC (#117652)
These macros are created inside a function. They should be undefined
before the end of the function.
Commit: bf07a569b73b5f8634cad30fa21c03a1e3d63e0b
https://github.com/llvm/llvm-project/commit/bf07a569b73b5f8634cad30fa21c03a1e3d63e0b
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Remove extra commas of llvm.vp.ctlz (#117542)
Commit: dd7aabf7c041f094ef2124bb5b8fe9434490d266
https://github.com/llvm/llvm-project/commit/dd7aabf7c041f094ef2124bb5b8fe9434490d266
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[TTI][RISCV] Deduplicate type-based VP costing of vpcmp/vpcast (#117520)
Refered to: https://github.com/llvm/llvm-project/pull/115983
Commit: 6633916ef5ab17bae9b2214a9e3327295ce56b5a
https://github.com/llvm/llvm-project/commit/6633916ef5ab17bae9b2214a9e3327295ce56b5a
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Remove getPostRAMutations (#117527)
We are using `PostMachineScheduler` instead of `PostRAScheduler`
since #68696.
The hook `getPostRAMutations` is only used in `PostRAScheduler` so
it is actually dead code for RISC-V now.
Commit: 6657d4bd70523e6852f07f64711fb15bdf7b347a
https://github.com/llvm/llvm-project/commit/6657d4bd70523e6852f07f64711fb15bdf7b347a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
Log Message:
-----------
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
This looks like a rather weird change, so let me explain why this isn't
as unreasonable as it looks. Let's start with the problem it's solving.
```
define signext i32 @overlap_live_ranges(ptr %arg, i32 signext %arg1) { bb:
%i = icmp eq i32 %arg1, 1
br i1 %i, label %bb2, label %bb5
bb2: ; preds = %bb
%i3 = getelementptr inbounds nuw i8, ptr %arg, i64 4
%i4 = load i32, ptr %i3, align 4
br label %bb5
bb5: ; preds = %bb2, %bb
%i6 = phi i32 [ %i4, %bb2 ], [ 13, %bb ]
ret i32 %i6
}
```
Right now, we codegen this as:
```
li a3, 1
li a2, 13
bne a1, a3, .LBB0_2
lw a2, 4(a0)
.LBB0_2:
mv a0, a2
ret
```
In this example, we have two values which must be assigned to a0 per the
ABI (%arg, and the return value). SelectionDAG ensures that all values
used in a successor phi are defined before exit the predecessor block.
This creates an ADDI to materialize the immediate in the entry block.
Currently, this ADDI is not sunk into the tail block because we'd have
to split a critical edges to do so. Note that if our immediate was
anything large enough to require two instructions we *would* split this
critical edge.
Looking at other targets, we notice that they don't seem to have this
problem. They perform the sinking, and tail duplication that we don't.
Why? Well, it turns out for AArch64 that this is entirely an accident of
the existance of the gpr32all register class. The immediate is
materialized into the gpr32 class, and then copied into the gpr32all
register class. The existance of that copy puts us right back into the
two instruction case noted above.
This change essentially just bypasses this emergent behavior aspect of
the aarch64 behavior, and implements the same "always sink immediates"
behavior for RISCV as well.
Commit: 5dd48c4901c60f2a38aa4e78160cc72eafcbbc5b
https://github.com/llvm/llvm-project/commit/5dd48c4901c60f2a38aa4e78160cc72eafcbbc5b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 658db918fe47efc0a3ba0556d58d607f0919f1e3
https://github.com/llvm/llvm-project/commit/658db918fe47efc0a3ba0556d58d607f0919f1e3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 of gfx950. (#117591)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 22503a9df16e8bf320c81ffbd3b4c70de45f8053
https://github.com/llvm/llvm-project/commit/22503a9df16e8bf320c81ffbd3b4c70de45f8053
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c767570eb1d8d11d42b831ac64eae44786782827
https://github.com/llvm/llvm-project/commit/c767570eb1d8d11d42b831ac64eae44786782827
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 of gfx950. (#117593)
OPSEL[0] selects src_word to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: d727b6f7778d98a3c506c6150a5d4f68056c1cee
https://github.com/llvm/llvm-project/commit/d727b6f7778d98a3c506c6150a5d4f68056c1cee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_fp4_{f|bf}16 on gfx950. (#117594)
These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c3377af4c3646e84f33d4e50846645b1c17f6403
https://github.com/llvm/llvm-project/commit/c3377af4c3646e84f33d4e50846645b1c17f6403
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
Log Message:
-----------
[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515)
Commit: a87d484a97f6ddc7404a2970a764158a5b27e3e5
https://github.com/llvm/llvm-project/commit/a87d484a97f6ddc7404a2970a764158a5b27e3e5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Support v_cvt_scalef32_2xpk16_{bf|fp}6_f32 for gfx950. (#117595)
Scale packed 16-component single-precision float vectors from
two source inputs using the exponent provided by the third
single-precision float input, then convert the values to a packed
32-component FP6 float value.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 5d650a62a35c2f38b112f5ee930654e678bcd5bb
https://github.com/llvm/llvm-project/commit/5d650a62a35c2f38b112f5ee930654e678bcd5bb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_ashr_pk_i8/u8_i32 instructions for gfx950 (#117596)
This patch adds assembly and builtin support for v_ashr_pk_i8/u8_i32
instructions.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: aa7eb5723cb4499f35ed1c5455f668ccc078e7c2
https://github.com/llvm/llvm-project/commit/aa7eb5723cb4499f35ed1c5455f668ccc078e7c2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
A llvm/test/MC/AMDGPU/gfx950_dlops.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_dot2_f32_bf16 instruction for gfx950 (#117597)
v_dot2_f32_bf16 was added in gfx11 along with v_dot2_f16_f16 and v_dot2_bf16_bf16.
All three instructions were part of Dot9 instructions in the compiler.
This patch will split existing dot9 (v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16)
into new dot9 (v_dot2_f16_f16 and v_dot2_bf16_bf16), and dot12 (v_dot2_f32_bf16).
All necessary changes to gfx11 and gfx12 are updated to reflect this change.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 716364ebd6649aeca8658680ebb8b0424d028006
https://github.com/llvm/llvm-project/commit/716364ebd6649aeca8658680ebb8b0424d028006
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
A llvm/test/MC/AMDGPU/gfx950_xdlops.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_xdlops.txt
Log Message:
-----------
AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)
The encoding of v_dot2c_f32_bf16 opcode is same as v_mac_f32 in gfx90a,
both from gfx9 series. This required a new decoderNameSpace GFX950_DOT.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 7fc71f79099b1556a57c9e96f7d62064dcff44d4
https://github.com/llvm/llvm-project/commit/7fc71f79099b1556a57c9e96f7d62064dcff44d4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
Log Message:
-----------
AMDGPU: Support buffer_atomic_pk_add_bf16 for gfx950 (#117599)
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: a5174de8c2244b2651568095e3136dd90df1c869
https://github.com/llvm/llvm-project/commit/a5174de8c2244b2651568095e3136dd90df1c869
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add encodings for minimum3/maximum3 f32 for gfx950 (#117600)
Commit: ae719f07562a2eb74f620b1f6d798d6507760514
https://github.com/llvm/llvm-project/commit/ae719f07562a2eb74f620b1f6d798d6507760514
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add minimum3/maximum3 pkf16 for gfx950 encodings (#117601)
Commit: eb5cda480d2ad81230b2aa3e134e2b603ff90a1c
https://github.com/llvm/llvm-project/commit/eb5cda480d2ad81230b2aa3e134e2b603ff90a1c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocatable.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/allocatable.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] cuf.allocate: Carry over stream to the runtime call (#117631)
- Update the runtime entry points to accept a stream information
- Update the conversion of `cuf.allocate` to pass correctly the stream
information when present.
Note that the stream is not currently used in the runtime. This will be
done in a separate patch as a design/solution needs to be down together
with the allocators.
Commit: ca184cfc088a843e545e5f04b48813e6f9bfba77
https://github.com/llvm/llvm-project/commit/ca184cfc088a843e545e5f04b48813e6f9bfba77
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/ClangdLSPServer.h
M clang-tools-extra/clangd/ClangdServer.cpp
M clang-tools-extra/clangd/ClangdServer.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/XRefs.h
M clang-tools-extra/clangd/index/Index.cpp
M clang-tools-extra/clangd/index/Index.h
M clang-tools-extra/clangd/index/MemIndex.cpp
M clang-tools-extra/clangd/index/MemIndex.h
M clang-tools-extra/clangd/index/Merge.cpp
M clang-tools-extra/clangd/index/Merge.h
M clang-tools-extra/clangd/index/ProjectAware.cpp
M clang-tools-extra/clangd/index/Ref.h
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/index/SymbolCollector.h
M clang-tools-extra/clangd/index/dex/Dex.cpp
M clang-tools-extra/clangd/index/dex/Dex.h
M clang-tools-extra/clangd/test/type-hierarchy-ext.test
M clang-tools-extra/clangd/test/type-hierarchy.test
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/RenameTests.cpp
Log Message:
-----------
[clangd] Support outgoing calls in call hierarchy (#77556)
Co-authored-by: Quentin Chateau <quentin.chateau at gmail.com>
Commit: d77cab823fc03f6933c3375baaddaae1477bb1d2
https://github.com/llvm/llvm-project/commit/d77cab823fc03f6933c3375baaddaae1477bb1d2
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/ClangdLSPServer.h
M clang-tools-extra/clangd/ClangdServer.cpp
M clang-tools-extra/clangd/ClangdServer.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/XRefs.h
M clang-tools-extra/clangd/index/Index.cpp
M clang-tools-extra/clangd/index/Index.h
M clang-tools-extra/clangd/index/MemIndex.cpp
M clang-tools-extra/clangd/index/MemIndex.h
M clang-tools-extra/clangd/index/Merge.cpp
M clang-tools-extra/clangd/index/Merge.h
M clang-tools-extra/clangd/index/ProjectAware.cpp
M clang-tools-extra/clangd/index/Ref.h
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/index/SymbolCollector.h
M clang-tools-extra/clangd/index/dex/Dex.cpp
M clang-tools-extra/clangd/index/dex/Dex.h
M clang-tools-extra/clangd/test/type-hierarchy-ext.test
M clang-tools-extra/clangd/test/type-hierarchy.test
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/RenameTests.cpp
Log Message:
-----------
Revert "[clangd] Support outgoing calls in call hierarchy (#77556)" (#117668)
This reverts commit ca184cfc088a843e545e5f04b48813e6f9bfba77.
Commit: 6e57186c0c14702055984f9cfa59be02f0f72356
https://github.com/llvm/llvm-project/commit/6e57186c0c14702055984f9cfa59be02f0f72356
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Format/Format.cpp
Log Message:
-----------
[clang-format][NFC] Clean up RemoveBraces, RemoveSemi, etc.
Commit: bc282605dfe341add6f7ee8234fed2cd55f5656b
https://github.com/llvm/llvm-project/commit/bc282605dfe341add6f7ee8234fed2cd55f5656b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a TargetConstant. (#117639)
Fix all the places I could find that did't do this. We were already
mostly correct for FP_ROUND after
9a976f36615dbe15e76c12b22f711b2e597a8e51, but not STRICT_FP_ROUND.
Commit: 90f5c8b790d8a57eab49320e77d6ce11c6c2d36f
https://github.com/llvm/llvm-project/commit/90f5c8b790d8a57eab49320e77d6ce11c6c2d36f
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
Log Message:
-----------
[LV][NFC] Auto-generate the test cases related to FindLastIV idioms. (#117560)
Pre-commit for #67812
Commit: 5e3f6150b1d490090faf945777985b18db73ea3f
https://github.com/llvm/llvm-project/commit/5e3f6150b1d490090faf945777985b18db73ea3f
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
Log Message:
-----------
[lldb/NativePDB] Don't create parentless blocks (#117581)
In case of an error GetBlock would return a reference to a Block without
adding it to a parent. This doesn't seem like a good idea, and none of
the other plugins do that.
This patch fixes that by propagating errors (well, null pointers...) up
the stack.
I don't know of any specific problem that this solves, but given that
this occurs only when something goes very wrong (e.g. a corrupted PDB
file), it's quite possible noone has run into this situation, so we
can't say the code is correct either. It also gets in the way of a
refactor I'm contemplating.
Commit: 56eb559b1d49ec6fa2d75753078e5b57f4b606c2
https://github.com/llvm/llvm-project/commit/56eb559b1d49ec6fa2d75753078e5b57f4b606c2
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/attr-cpuspecific.c
Log Message:
-----------
[clang][FMV] Fix crash with cpu_specific attribute. (#115762)
When dealing with cpu_specific GlobalDecl,
GetOrCreateMultiVersionResolver should immediately return the already
created llvm function if it exists.
Fixes https://github.com/llvm/llvm-project/issues/115299.
Commit: 1b2c8f104f9c6f26500ab608060bbc6b7f40f5e1
https://github.com/llvm/llvm-project/commit/1b2c8f104f9c6f26500ab608060bbc6b7f40f5e1
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Conversion/TensorToLinalg/TensorToLinalg.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
A mlir/test/Dialect/Linalg/decompose-pad-tensor.mlir
R mlir/test/Dialect/Linalg/generalize-pad-tensor.mlir
M mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
Log Message:
-----------
[mlir][linalg] Extract `GeneralizePadOpPattern` into a standalone transformation (#117329)
Currently, `GeneralizePadOpPattern` is grouped under
`populatePadOpVectorizationPatterns`. However, as noted in #111349, this
transformation "decomposes" rather than "vectorizes" `tensor.pad`. As
such, it functions as:
* a vectorization _pre-processing_ transformation, not
* a vectorization transformation itself.
To clarify its purpose, this PR turns `GeneralizePadOpPattern` into a
standalone transformation by:
* introducing a dedicated `populateDecomposePadPatterns` method,
* adding a `apply_patterns.linalg.decompose_pad` Transform Dialect Op,
* removing it from `populatePadOpVectorizationPatterns`.
In addition, to better reflect its role, it is renamed as "decomposition"
rather then "generalization". This is in line with the recent renaming
of similar ops, i.e. tensor.pack/tensor.unpack Ops in #116439.
Commit: bb8bf858e865ec3119352bdef43c09adb4c93b31
https://github.com/llvm/llvm-project/commit/bb8bf858e865ec3119352bdef43c09adb4c93b31
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/HLFIR/assumed-rank-internal-proc.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
Log Message:
-----------
[flang] add internal_assoc flag to mark variable captured in internal procedure (#117161)
This patch adds a flag to mark hlfir.declare of host variables that are
captured in some internal procedure.
It enables implementing a simple fir.call handling in
fir::AliasAnalysis::getModRef leveraging Fortran language specifications
and without a data flow analysis.
This will allow implementing an optimization for "array =
array_function()" where array storage is passed directly into the hidden
result argument to "array_function" when it can be proven that
arraY_function does not reference "array".
Captured host variables are very tricky because they may be accessed
indirectly in any calls if the internal procedure address was captured
via some global procedure pointer. Without flagging them, there is no
way around doing a complex inter procedural data flow analysis:
- checking that the call is not made to an internal procedure is not
enough because of the possibility of indirect calls made to internal
procedures inside the callee.
- checking that the current func.func has no internal procedure is not
enough because this would be invalid with inlining when an procedure
with internal procedures is inlined inside a procedure without internal
procedure.
Commit: a96ec01e1a269b663ccc1dadc2f4429fd0df887d
https://github.com/llvm/llvm-project/commit/a96ec01e1a269b663ccc1dadc2f4429fd0df887d
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
Log Message:
-----------
[AMDGPU] Optimize out s_barrier_signal/_wait (#116993)
Extend the optimization that converts s_barrier to wave_barrier (nop)
when the number of work items is not larger than wave size.
This handles the "split barrier" form of s_barrier where the barrier
is represented by separate intrinsics (s_barrier_signal/s_barrier_wait).
Note: the version where s_barrier is used in gfx12 (and later split)
has the optimization already, but some front-ends may prefer to use
split intrinsics and this is being addressed by the patch.
Commit: 9acd8e381091765a932d54bc22359cdafa9e75c6
https://github.com/llvm/llvm-project/commit/9acd8e381091765a932d54bc22359cdafa9e75c6
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
Log Message:
-----------
[clangd] Drop requirement for named template parameters (#117565)
... in DefineOutline tweak for function templates. As opposed to class
templates, the name is not required for writing an out-of-line
definition.
Commit: 93caee17add0c7bc6770365b1d3cae93f258d866
https://github.com/llvm/llvm-project/commit/93caee17add0c7bc6770365b1d3cae93f258d866
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fveclib.c
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/IR/VFABIDemangler.h
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/IR/VFABIDemangler.cpp
A llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
A llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)
SLEEF math vector library now supports RISC-V target.
Commit: https://github.com/shibatch/sleef/pull/477
This patch enables the use of auto-vectorization with
subsequent replacement by the corresponding SLEEF function.
Commit: 29062329f3cf0ac8f1ae626e758ca64f82294fbf
https://github.com/llvm/llvm-project/commit/29062329f3cf0ac8f1ae626e758ca64f82294fbf
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
[RISCV] Implement tail call optimization in machine outliner (#115297)
Following up issue #89822, this patch adds opportunity to use tail call
in machine outliner pass.
Also it enables outline patterns with X5(T0) register.
Commit: 3e1b55cafc95d4ef46f302d0fcd695461e376958
https://github.com/llvm/llvm-project/commit/3e1b55cafc95d4ef46f302d0fcd695461e376958
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SDAG] Don't allow implicit trunc in getConstant() (#117558)
Assert that the passed value is a valid unsigned integer value for the
specified type.
For signed values getSignedConstant() / getSignedTargetConstant() should
be used instead.
Commit: 231e63d8162a1c78a973c6e546bea39d04fefd67
https://github.com/llvm/llvm-project/commit/231e63d8162a1c78a973c6e546bea39d04fefd67
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Refactor insertConditions. NFC. (#115476)
This just makes it more obvious that having Parent as the single
predecessor is a special case, instead of checking for it in the middle
of a loop that finds the nearest common dominator of multiple
predecessors.
Commit: 79f59afff966c3abff541535431862885dc0a833
https://github.com/llvm/llvm-project/commit/79f59afff966c3abff541535431862885dc0a833
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
Log Message:
-----------
[mlir][linalg][nfc] Update "pack-dynamic-inner-tile.mlir" (#117533)
Builds on:
* #117329: "Extract GeneralizePadOpPattern into a standalone
transformation".
* #116373: "Update pack-dynamic-inner-tile.mlir".
This update adds vectorization to the "pack-dynamic-inner-tile.mlir"
pipeline.
The pipeline first decomposes `tensor.pack` into `tensor.pad` and then
into `linalg.fill` (https://github.com/llvm/llvm-project/pull/117329).
Next, `linalg.fill` is vectorized, with vector sizes matching the inner
tile sizes of the original `tensor.pack`.
Commit: 36b1811da496a0527aab0de76bd3687ff4880bfa
https://github.com/llvm/llvm-project/commit/36b1811da496a0527aab0de76bd3687ff4880bfa
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/interception_win.h
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] Add a test skeleton for function GetInstructionSize. (#116948)
Was first part of PR #113085.
Commit: 3414993eaffcfa2cb4ff723c8468434d56dff213
https://github.com/llvm/llvm-project/commit/3414993eaffcfa2cb4ff723c8468434d56dff213
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[AMDGPU][SplitModule] Fix potential divide by zero (#117602)
A static analysis tool found that ModuleCost could be zero, so would
perform divide by zero when being printed. Perhaps this is unreachable
in practice, but the fix is straightforward enough and unlikely to be a
performance concern.
Commit: cf602b95d14532fdb97679806bc5ba9d55631875
https://github.com/llvm/llvm-project/commit/cf602b95d14532fdb97679806bc5ba9d55631875
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
A flang/test/Analysis/AliasAnalysis/gen_mod_ref_test.py
A flang/test/Analysis/AliasAnalysis/modref-call-after-inlining.fir
A flang/test/Analysis/AliasAnalysis/modref-call-args.f90
A flang/test/Analysis/AliasAnalysis/modref-call-dummies.f90
A flang/test/Analysis/AliasAnalysis/modref-call-equivalence.f90
A flang/test/Analysis/AliasAnalysis/modref-call-globals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-internal-proc.f90
A flang/test/Analysis/AliasAnalysis/modref-call-locals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-not-fortran.fir
Log Message:
-----------
[flang] handle fir.call in AliasAnalysis::getModRef (#117164)
fir.call side effects are hard to describe in a useful way using
`MemoryEffectOpInterface` because it is impossible to list which memory
location a user procedure read/write without doing a data flow analysis
of its body (even PURE procedures may read from any module variable,
Fortran SIMPLE procedure from F2023 will allow that, but they are far
from common at that point).
Fortran language specifications allow the compiler to deduce
that a procedure call cannot access a variable in many cases
This patch leverages this to extend `fir::AliasAnalysis::getModRef` to
deal with fir.call.
This will allow implementing "array = array_function()" optimization in
a future patch.
Commit: ad7bb652d61e2e8021df03018ea05750abf66b0e
https://github.com/llvm/llvm-project/commit/ad7bb652d61e2e8021df03018ea05750abf66b0e
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/docs/Intrinsics.md
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/len_trim.f90
Log Message:
-----------
[flang] Implement non-standard LNBLNK intrinsic (#117589)
This is defined here
https://gcc.gnu.org/onlinedocs/gfortran/LNBLNK.html. It is just an alias
to LEN_TRIM.
This was requested by a user:
https://discourse.llvm.org/t/unresolved-externals-with-appendend-underscore/83305
Commit: c0192a008c4a2b8afdc2b63526c0483632d81c07
https://github.com/llvm/llvm-project/commit/c0192a008c4a2b8afdc2b63526c0483632d81c07
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/system.f90
Log Message:
-----------
[flang] implement function form of SYSTEM intrinsic (#117585)
SYSTEM is a gfortran extension which we already supported in subroutine
form. Gfortran also allows it to be called as a function, which was
requested by a user
https://discourse.llvm.org/t/unresolved-externals-with-appendend-underscore/83305/4
Commit: b9e3a769b99e9dafa3e5205dbbef9fae8573e4e2
https://github.com/llvm/llvm-project/commit/b9e3a769b99e9dafa3e5205dbbef9fae8573e4e2
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/task_mergeable.f90
M flang/test/Lower/OpenMP/task.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[flang][mlir][llvm][OpenMP] Add lowering and translation support for mergeable clause on task (#114662)
Add FIR generation and LLVMIR translation support for mergeable clause
on task construct. If mergeable clause is present on a task, the
relevant flag in `ompt_task_flag_t` is set and passed to
`__kmpc_omp_task_alloc`.
Commit: d471c85e654ad0111cdffe588b2b958b62eca29f
https://github.com/llvm/llvm-project/commit/d471c85e654ad0111cdffe588b2b958b62eca29f
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
M mlir/test/Dialect/Arith/int-range-interface.mlir
Log Message:
-----------
[mlir][int-range] Update int range inference for `arith.xori` (#117272)
Previous impl was getting incorrect results for widths > i1 and was
disabled.
While same algorithm can be used for `andi` and `ori` too, without
additional modifications it will produce less precise result.
Commit: 45fdb7755737f10822003a3dd1870ac5a5c0b8eb
https://github.com/llvm/llvm-project/commit/45fdb7755737f10822003a3dd1870ac5a5c0b8eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
Log Message:
-----------
[MCA][X86] Cleanup znver4 instregex patterns for (V)PMOV extension/truncation instructions
Split extension/truncation patterns to simplify matching.
Fix patterns to consistently match SSE/AVX1/AVX2 variants as well.
Add some missing src/dst type variants - there should be no difference in scheduling, its purely based on dst reg width.
Confirmed with Agner/uops.info
Noticed while triaging #110308
Commit: 4a7b56e6e7dd0f83c379ad06b6e81450bc691ba6
https://github.com/llvm/llvm-project/commit/4a7b56e6e7dd0f83c379ad06b6e81450bc691ba6
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
M mlir/include/mlir/IR/Matchers.h
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/CAPI/ir.c
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
Log Message:
-----------
[MLIR][Arith] Add denormal attribute to binary/unary operations (#112700)
Add support for denormal in the Arith dialect (binary and unary
operations).
Denormal are attached to every operation, and they can be of three
different
kinds:
1) ieee, denormal are preserved and processed as defined by IEEE 754
rules.
2) preserve sign, a mode where denormal numbers are flushed to zero, but
the
sign of the zero (+0 or -0) is preserved.
3) positive zero, a mode where all denormal numbers are flushed to
positive zero
(+0), ignoring the sign of the original number.
Denormal refers to both the operands and the result. Currently only
lowering for
ieee is supported.
Commit: 486644723038555a224fd09d462bb5099e64809e
https://github.com/llvm/llvm-project/commit/486644723038555a224fd09d462bb5099e64809e
Author: Vladislav Belov <vladislav.belov at syntacore.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CXXInheritance.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Fix name lookup for dependent bases (#114978)
Currently the following example is a compilation failure:
```cpp
template<typename T> struct A {
typedef int M;
struct B {
typedef void M;
struct C;
};
};
template<typename T> struct A<T>::B::C : A<T> {
M m; // void or int ?
};
```
According to the point 13.8.3.2
```
A dependent base class is a base class that is a dependent type and is not the current instantiation.
Note 2 : A base class can be the current instantiation in the case of a nested class naming an enclosing class as a base.
```
The base class `A` is the current instantiation, because `C` is a nested
class for an enclosing class `A<T>`, it's is the not-dependent base
class and we need to search the names through its scope.
This patch makes this example compile
Commit: ec4c47d9490c90a98f2dda3fc9ff7c51782678f8
https://github.com/llvm/llvm-project/commit/ec4c47d9490c90a98f2dda3fc9ff7c51782678f8
Author: ykiko <ykikoykikoykiko at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
A clang/test/CodeCompletion/keywords-cxx20.cpp
Log Message:
-----------
Add code completion for C++20 keywords. (#107982)
This commit adds code completion for C++20 keywords, fix
https://github.com/llvm/llvm-project/issues/107868.
1. complete `concept` in template context
- [x] `template<typename T> conce^` -> `concept`
- [ ] `conce^`
2. complete `requires`
- [x] constraints in template context: `template<typename T> requi^` ->
`requires`
- [x] requires expression: `int x = requ^` -> `requires (parameters) {
requirements }`
- [x] nested requirement: `requires { requ^ }` -> `requires expression
;`
3. complete coroutine keywords
- [x] `co_await^` in expression: `co_aw^` -> `co_await expression;`
- [x] `co_yield` in function body: `co_yi^` -> `co_yield expression;`
- [x] `co_return` in function body: `co_re^` -> `co_return expression;`
4. specifiers: `char8_t`, `consteval`, `constinit`
Commit: 90df66455b2ff6a3b3754a56afafc05935a05e15
https://github.com/llvm/llvm-project/commit/90df66455b2ff6a3b3754a56afafc05935a05e15
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
Log Message:
-----------
[MCA][X86] Fix throughput of (V)PMOV extension/truncation 512-bit instructions
znver4 512-bit instructions are half rate of 128/256-bit variants (still 1uop though)
Confirmed with Agner/uops.info
Noticed while triaging #110308 and #117579
Commit: 827ebf84e9af7c93a30daf4ed17e99ccef4cf94a
https://github.com/llvm/llvm-project/commit/827ebf84e9af7c93a30daf4ed17e99ccef4cf94a
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang] constexpr built-in elementwise popcount function. (#117473)
Part of #51787.
This patch adds constexpr support for the built-in elementwise popcount
function.
Commit: f94bd3c933076500b9291009d8cb5e1139c52a06
https://github.com/llvm/llvm-project/commit/f94bd3c933076500b9291009d8cb5e1139c52a06
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
R llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
R llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
Revert "[RISCV] Implement tail call optimization in machine outliner" (#117710)
Reverts llvm/llvm-project#115297
Bots are broken
Commit: 6f5e5b630559f2d17bdccfab5dff3a97ac0f8c66
https://github.com/llvm/llvm-project/commit/6f5e5b630559f2d17bdccfab5dff3a97ac0f8c66
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/unittests/IR/AffineMapTest.cpp
Log Message:
-----------
[mlir][unittest][nfc] Simplify `getInversePermutation` (#117698)
Commit: 5322415f92fe44a9dac29c95da5ed434efbbba7e
https://github.com/llvm/llvm-project/commit/5322415f92fe44a9dac29c95da5ed434efbbba7e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Use getSignedConstant() in SelectOptimalAddrMode()
All of these immediates are signed, as the surrounding comments
indicate. This fixes an assertion failure in
CodeGen/Generic/dag-combine-ossfuzz-crash.ll when run with a
powerpc-aix triple.
Commit: eb5d69c9ab5e817aaff967d06c8f358c0844b6b8
https://github.com/llvm/llvm-project/commit/eb5d69c9ab5e817aaff967d06c8f358c0844b6b8
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
A clang/test/AST/ast-dump-cxx2b-deducing-this.cpp
Log Message:
-----------
[Clang] use begin member expr location for call expr with deducing this (#117345)
Fixes #116928
Commit: 65c36179be68dda0d1cc5d7e5c5b312a6b52cc0e
https://github.com/llvm/llvm-project/commit/65c36179be68dda0d1cc5d7e5c5b312a6b52cc0e
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Arena.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/IntervalPartition.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
Log Message:
-----------
[clang][analysis][NFC]add static for internal linkage function (#117481)
Detected by misc-use-internal-linkage
Commit: 46fcdbbc78717767551594d5d9174db0bac1b375
https://github.com/llvm/llvm-project/commit/46fcdbbc78717767551594d5d9174db0bac1b375
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add alias.scope & noalias metadata to test.
Commit: f4379db49683a6b1d3d63b577985312556373c6f
https://github.com/llvm/llvm-project/commit/f4379db49683a6b1d3d63b577985312556373c6f
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mdiv32.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
A llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
Log Message:
-----------
[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instructions with inputs not signed-extended. (#116764)
Two options for clang
-mdiv32: Use div.w[u] and mod.w[u] instructions with input not
sign-extended.
-mno-div32: Do not use div.w[u] and mod.w[u] instructions with input not
sign-extended.
The default is -mno-div32.
Commit: 537343dea4e65ddb837473c9349884e856664ad8
https://github.com/llvm/llvm-project/commit/537343dea4e65ddb837473c9349884e856664ad8
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
R bolt/unittests/Core/MemoryMaps.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
Log Message:
-----------
Revert "[BOLT] DataAggregator support for binaries with multiple text segments (#92815)"
This caused test failures, see comment on the PR:
Failed Tests (2):
BOLT-Unit :: Core/./CoreTests/AArch64/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0
BOLT-Unit :: Core/./CoreTests/X86/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0
> When a binary has multiple text segments, the Size is computed as the
> difference of the last address of these segments from the BaseAddress.
> The base addresses of all text segments must be the same.
>
> Introduces flag 'perf-script-events' for testing. It allows passing perf events
> without BOLT having to parse them using 'perf script'. The flag is used to
> pass a mock perf profile that has two memory mappings for a mock binary
> that has two text segments. The size of the mapping is updated as this
> change `parseMMapEvents` processes all text segments.
This reverts commit 4b71b3782d217db0138b701c4514bd2168ca1659.
Commit: ead3a2f5980e1a713c8d4e18a4c825e1012b3701
https://github.com/llvm/llvm-project/commit/ead3a2f5980e1a713c8d4e18a4c825e1012b3701
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-117393.ll
Log Message:
-----------
[SLP][REVEC] getScalarizationOverhead should not be used when ScalarTy is FixedVectorType. (#117536)
Commit: 59b3630e032d7e92079667891e7cf585c7fe313d
https://github.com/llvm/llvm-project/commit/59b3630e032d7e92079667891e7cf585c7fe313d
Author: Victor Perez <victor.perez at codeplay.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
M mlir/test/Target/SPIRV/intel-ext-ops.mlir
Log Message:
-----------
[MLIR][SPIR-V] Drop commas from split barrier operations ASM format (#116673)
Drop commas from split barrier operations assembly format.
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Depends on #116648, review ec8d35471602cd88aa2ebaf239b698ef3ba353bd
only.
---------
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Commit: 619e4b7154606f315572ba54c0fe6c1f6c8848a0
https://github.com/llvm/llvm-project/commit/619e4b7154606f315572ba54c0fe6c1f6c8848a0
Author: 7FM <chill_dein_leben at gmx.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[MLIR][Arith] SelectOp fix invalid folding (#117555)
The pattern `select %x, true, false => %x` is only valid in case that
the return type is identical to the type of `%x` (i.e., i1). Hence, the
check `isInteger(1)` was replaced with `isSignlessInteger(1)`.
Fixes: https://github.com/llvm/llvm-project/issues/117554
Commit: f4d758634305304c0deb49a4ed3f99180a2488ea
https://github.com/llvm/llvm-project/commit/f4d758634305304c0deb49a4ed3f99180a2488ea
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/TypeUtilities.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/tools/mlir-tblgen/BytecodeDialectGen.cpp
Log Message:
-----------
[mlir] Use `llvm::filter_to_vector`. NFC. (#117655)
This got recently added to SmallVectorExtras:
https://github.com/llvm/llvm-project/pull/117460.
Commit: 4028bb10c3a396023b877d025c5776d207f29f91
https://github.com/llvm/llvm-project/commit/4028bb10c3a396023b877d025c5776d207f29f91
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/Utils/Local.cpp
A llvm/test/Transforms/EarlyCSE/noalias-addrspace.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
Log Message:
-----------
Local: Handle noalias_addrspace in combineMetadata (#103938)
This should act like range.
Previously ConstantRangeList assumed a 64-bit range. Now query from the
actual entries. This also means that the empty range has no bitwidth, so
move asserts to avoid checking the bitwidth of empty ranges.
Commit: ab6677e7d64b4612d6c92877cb1d529f922268d2
https://github.com/llvm/llvm-project/commit/ab6677e7d64b4612d6c92877cb1d529f922268d2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-metadata.ll
M llvm/test/Transforms/LICM/hoisting-preheader-debugloc.ll
Log Message:
-----------
[LICM] Only set AA metadata on hoisted load if it executes. (#117204)
https://github.com/llvm/llvm-project/pull/116220 clarified that
violations of aliasing metadata are UB.
Only set the AA metadata after hoisting a log, if it is guaranteed to
execute in the original loop.
PR: https://github.com/llvm/llvm-project/pull/117204
Commit: 9efdebc5f15e284dc7c58d327057ec8af9eed342
https://github.com/llvm/llvm-project/commit/9efdebc5f15e284dc7c58d327057ec8af9eed342
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExprMember.cpp
M clang/test/SemaCXX/warn-unused-private-field.cpp
Log Message:
-----------
[Clang] Only ignore special methods for unused private fields in BuildFieldReferenceExpr (#116965)
The original code assumed that only special methods might be defined as
defaulted. Since C++20 comparison operators might be defaulted too, and
we *do* want to consider those as using the fields of the class.
Fixes: #116961
Commit: 624e52b1e310c349e21cc0b4f67452b0fa9d1f96
https://github.com/llvm/llvm-project/commit/624e52b1e310c349e21cc0b4f67452b0fa9d1f96
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
Log Message:
-----------
[DebugInfo] Handle trailing empty blocks when seeking prologue_end spot (#117320)
The optimiser will produce empty blocks that are unconditionally
executed according to the CFG -- while it may not be meaningful code,
and won't get a prologue_end position, we need to not crash on this
input.
The fault comes from assuming that there's always a next block with some
instructions in it, that will eventually produce some meaningful control
flow to stop at -- in the given reproducer in issue #117206 this isn't
true, because the function terminates with `unreachable`. Thus, I've
refactored the "get next instruction logic" into a helper that'll step
through all blocks and terminate if there aren't any more.
Reproducer from aeubanks
Commit: db6f627f3fd4072fe1814805653a352694527a91
https://github.com/llvm/llvm-project/commit/db6f627f3fd4072fe1814805653a352694527a91
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AArch64.cpp
A clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
Log Message:
-----------
[clang][SME] Ignore flatten/clang::always_inline statements for callees with mismatched streaming attributes (#116391)
If `__attribute__((flatten))` is used on a function, or
`[[clang::always_inline]]` on a statement, don't inline any callees with
incompatible streaming attributes. Without this check, clang may produce
incorrect code when these attributes are used in code with streaming
functions.
Note: The docs for flatten say it can be ignored when inlining is
impossible: "causes calls within the attributed function to be inlined
unless it is impossible to do so".
Similarly, the (clang-only) `[[clang::always_inline]]` statement
attribute is more relaxed than the GNU `__attribute__((always_inline))`
(which says it should error it if it can't inline), saying only "If a
statement is marked [[clang::always_inline]] and contains calls, the
compiler attempts to inline those calls.". The docs also go on to show
an example of where `[[clang::always_inline]]` has no effect.
Commit: b214ca82daeece1568268ebc0fbcc2eaa649425b
https://github.com/llvm/llvm-project/commit/b214ca82daeece1568268ebc0fbcc2eaa649425b
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir][vector] Rename vector type TD definitions (nfc) (#117150)
Currently, the Vector dialect TD file includes the following "vector"
type definitions:
```mlir
def AnyVector : VectorOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVector : FixedVectorOf<[AnyType]>;
def AnyScalableVector : ScalableVectorOf<[AnyType]>;
```
In short:
* `AnyVector` _excludes_ 0-D vectors.
* `AnyVectorOfAnyRank`, `AnyFixedVector`, and `AnyScalableVector`
_include_ 0-D vectors.
The naming for "groups" that include 0-D vectors is inconsistent and can
be misleading, and `AnyVector` implies that 0-D vectors are included,
which is not the case.
This patch renames these definitions for clarity:
```mlir
def AnyVectorOfNonZeroRank : VectorOfNonZeroRankOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVectorOfAnyRank : FixedVectorOfAnyRank<[AnyType]>;
def AnyScalableVectorOfAnyRank : ScalableVectorOfAnyRank<[AnyType]>;
```
Rationale:
* The updated names are more explicit about 0-D vector support.
* It becomes clearer that scalable vectors currently allow 0-D vectors -
this might warrant a revisit.
* The renaming paves the way for adding a new group for "fixed-width
vectors excluding 0-D vectors" (e.g., AnyFixedVector), which I plan to
introduce in a follow-up patch.
Commit: 7577284c4f3cb81a8ac648683bd3af292827391f
https://github.com/llvm/llvm-project/commit/7577284c4f3cb81a8ac648683bd3af292827391f
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/SemaOpenACC/compute-construct-varlist-ast.cpp
Log Message:
-----------
[OpenACC][NFC] Update varlist-ast test to check serialization
I noticed while working on another test that I never used the PCH
trickery to get this to validate that serialization/deserialization
works correctly. It DOES, but we weren't testing it with this test like
the others.
Commit: 80df56e03b0455382cec51557bfc9f099d5c0a6f
https://github.com/llvm/llvm-project/commit/80df56e03b0455382cec51557bfc9f099d5c0a6f
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
This MR fixes failed test `CodeGen/RISCV/compress-opt-select.ll`.
It was failed due to previously merged commit `[TTI][RISCV]
Unconditionally break critical edges to sink ADDI (PR #108889)`.
So, regenerated `compress-opt-select` test.
Commit: f7dc1d0ac83b7c6b691167d8d02561ba0837b631
https://github.com/llvm/llvm-project/commit/f7dc1d0ac83b7c6b691167d8d02561ba0837b631
Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CXXInheritance.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
Revert "[Clang] Fix name lookup for dependent bases (#114978)" (#117727)
This reverts commit 486644723038555a224fd09d462bb5099e64809e as
requested by the commit author.
Buildbots fail:
* https://lab.llvm.org/buildbot/#/builders/164/builds/4945
* https://lab.llvm.org/buildbot/#/builders/52/builds/4021
Commit: 86f7f089ee6bcf01bf082ca802220b1143a3ade9
https://github.com/llvm/llvm-project/commit/86f7f089ee6bcf01bf082ca802220b1143a3ade9
Author: Miro Bucko <mbucko at meta.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Core/PluginManager.cpp
Log Message:
-----------
Fix return value of 'PluginManager::RegisterPlugin()'. (#114120)
Commit: 88cff867a58247d0c1da19e537eb8801a54ed38e
https://github.com/llvm/llvm-project/commit/88cff867a58247d0c1da19e537eb8801a54ed38e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
Log Message:
-----------
[InstCombine] Add tests for #113301 (NFC)
Commit: ced2fc7819d5ddea616ec330f18e08ff284c1868
https://github.com/llvm/llvm-project/commit/ced2fc7819d5ddea616ec330f18e08ff284c1868
Author: Christopher Bate <cbate at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/docs/Bufferization.md
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Arith/bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-analysis.mlir
A mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-partial.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-force-copy-before-write.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/Bufferization/ops.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
M mlir/test/Dialect/Linalg/bufferize.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/MemRef/normalize-memrefs.mlir
M mlir/test/Dialect/SCF/bufferize.mlir
A mlir/test/Dialect/SCF/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Shape/bufferize.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul24_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matvec_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sampled_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sddmm_lib.mlir
M mlir/test/Dialect/SparseTensor/constant_index_map.mlir
M mlir/test/Dialect/SparseTensor/dense.mlir
M mlir/test/Dialect/SparseTensor/fuse_sparse_pad_with_consumer.mlir
M mlir/test/Dialect/SparseTensor/sorted_coo.mlir
M mlir/test/Dialect/SparseTensor/sparse_1d.mlir
M mlir/test/Dialect/SparseTensor/sparse_2d.mlir
M mlir/test/Dialect/SparseTensor/sparse_3d.mlir
M mlir/test/Dialect/SparseTensor/sparse_affine.mlir
M mlir/test/Dialect/SparseTensor/sparse_batch.mlir
M mlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_fusion.mlir
M mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels_to_iterator.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
M mlir/test/Dialect/SparseTensor/sparse_nd.mlir
M mlir/test/Dialect/SparseTensor/sparse_outbuf.mlir
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
M mlir/test/Dialect/SparseTensor/sparse_parallel_reduce.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_scalars.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm_org.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_index.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
M mlir/test/Dialect/SparseTensor/unused-tensor.mlir
M mlir/test/Dialect/SparseTensor/vectorize_reduction.mlir
M mlir/test/Dialect/Tensor/bufferize.mlir
A mlir/test/Dialect/Tensor/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/bufferize.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
M mlir/test/Integration/Dialect/Tosa/CPU/test-maxpool-dynamic.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/mulf-full.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/muli-full.mlir
Log Message:
-----------
[mlir][bufferization] Fix OneShotBufferize when `defaultMemorySpaceFn` is used (#91524)
As described in issue llvm/llvm-project#91518, a previous PR
llvm/llvm-project#78484 introduced the `defaultMemorySpaceFn` into
bufferization options, allowing one to inform OneShotBufferize that it
should use a specified function to derive the memory space attribute
from the encoding attribute attached to tensor types.
However, introducing this feature exposed unhandled edge cases,
examples of which are introduced by this change in the new test under
`test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir`.
Fixing the inconsistencies introduced by `defaultMemorySpaceFn` is
pretty simple. This change:
- Updates the `bufferization.to_memref` and `bufferization.to_tensor`
operations to explicitly include operand and destination types,
whereas previously they relied on type inference to deduce the
tensor types. Since the type inference cannot recover the correct
tensor encoding/memory space, the operand and result types must be
explicitly included. This is a small assembly format change, but it
touches a large number of test files.
- Makes minor updates to other bufferization functions to handle the
changes in building the above ops.
- Updates bufferization of `tensor.from_elements` to handle memory
space.
Integration/upgrade guide:
In downstream projects, if you have tests or MLIR files that explicitly
use
`bufferization.to_tensor` or `bufferization.to_memref`, then update
them to the new assembly format as follows:
```
%1 = bufferization.to_memref %0 : memref<10xf32>
%2 = bufferization.to_tensor %1 : memref<10xf32>
```
becomes
```
%1 = bufferization.to_memref %0 : tensor<10xf32> to memref<10xf32>
%2 = bufferization.to_tensor %0 : memref<10xf32> to tensor<10xf32>
```
Commit: 2a0162c0193a73ef16aee67dbe66abb9d2e4717c
https://github.com/llvm/llvm-project/commit/2a0162c0193a73ef16aee67dbe66abb9d2e4717c
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll
Log Message:
-----------
[AArch64][SVE] Change the immediate argument in svextq (#115340)
In order to align with `svext` and NEON `vext`/`vextq`, this patch
changes immediate argument in `svextq` such that it refers to elements
of the size of those of the source vector, rather than bytes. The [spec
for this
intrinsic](https://github.com/ARM-software/acle/blob/main/main/acle.md#extq)
is ambiguous about the meaning of this argument, this issue was raised
after there was a differing interpretation for it from the implementers
of the ACLE in GCC.
For example (with our current implementation):
`svextq_f64(zn_f64, zm_f64, 1)` would, for each 128-bit segment of
`zn_f64,` concatenate the highest 15 bytes of this segment with the
first byte of the corresponding segment of `zm_f64`.
After this patch, the behavior of `svextq_f64(zn_f64, zm_f64, 1)` would
be, for each 128-bit vector segment of `zn_f64`, to concatenate the
higher doubleword of this segment with the lower doubleword of the
corresponding segment of `zm_f64`.
The range of the immediate argument in `svextq` would be modified such
that it is:
- [0,15] for `svextq_{s8,u8}`
- [0,7] for `svextq_{s16,u16,f16,bf16}`
- [0,3] for `svextq_{s32,u32,f32}`
- [0,1] for `svextq_{s64,u64,f64}`
Commit: bf440f75b485e4ea7f809dc37df74cac140069fd
https://github.com/llvm/llvm-project/commit/bf440f75b485e4ea7f809dc37df74cac140069fd
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[Clang][NFC] Remove trailing whitespace from Attr{,Docs}.td
Commit: b1a34b80b83156540519110cc798969dcfe1aec9
https://github.com/llvm/llvm-project/commit/b1a34b80b83156540519110cc798969dcfe1aec9
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/PowerPC/gcov_ctr_ref_init.ll
Log Message:
-----------
[NFC][Test] Fix PowerPC test gcov_ctr_ref_init.ll (#117577)
Commit: c55a080c080ed76a9aabe6dcd1966fedc0ecda5a
https://github.com/llvm/llvm-project/commit/c55a080c080ed76a9aabe6dcd1966fedc0ecda5a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Add shuffle coverage for compress, decompress, and repeat idioms
compress is intented to match vcompress from the ISA manual. Note that
deinterleave is a subset of this, and is already tested elsewhere.
decompress is the synthetic pattern defined in same - though we can often
do better than the mentioned iota/vrgather. Note that some of these
can also be expressed as interleave with at least one undef source,
and is already tested elsewhere.
repeat repeats each input element N times in the output. It can be
described as as a interleave operations, but we can sometimes do
better lowering wise.
Commit: 5a3299a684d7d8c40f48d732e5b80a8bd29aa882
https://github.com/llvm/llvm-project/commit/5a3299a684d7d8c40f48d732e5b80a8bd29aa882
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
Log Message:
-----------
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
We should leave these for EXPENSIVE_CHECKS builds. Some of these
were near the top of slowest tests.
Commit: 4ab298b5fbc8f48387062b2dd99ea07127c02e6b
https://github.com/llvm/llvm-project/commit/4ab298b5fbc8f48387062b2dd99ea07127c02e6b
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.h
Log Message:
-----------
[LLDB][ThreadELFCore] Set all the properties of ELFLinuxSigInfo to a non build dependent size (#117604)
On #110065 the changes to LinuxSigInfo Struct introduced some variables
that will differ in size on 32b or 64b. I've rectified this by setting
them all to build independent types.
Commit: 5fd4f32f985f83414d82a1c2c55741e363693352
https://github.com/llvm/llvm-project/commit/5fd4f32f985f83414d82a1c2c55741e363693352
Author: Zhengxing li <zhengxingli at microsoft.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/invalid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
Log Message:
-----------
[HLSL] Implement SV_GroupID semantic (#115911)
Support SV_GroupID attribute.
Translate it into dx.group.id in clang codeGen.
Fixes: #70120
Commit: 78c7024640a5b511685c445f554b7d985a7cf286
https://github.com/llvm/llvm-project/commit/78c7024640a5b511685c445f554b7d985a7cf286
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-default-clause.c
A clang/test/SemaOpenACC/combined-construct-present-ast.cpp
A clang/test/SemaOpenACC/combined-construct-present-clause.c
A clang/test/SemaOpenACC/combined-construct-present-clause.cpp
Log Message:
-----------
[OpenACC] Implement 'present' for combined constructs.
This is another clause where the parsing does all the required
enforcement besides the construct it appertains to, so this patch
removes the restriction and adds sufficient test coverage for combined
constructs.
Commit: 5683fc5cc043d1f43294bc57e04a901ad8cafcf5
https://github.com/llvm/llvm-project/commit/5683fc5cc043d1f43294bc57e04a901ad8cafcf5
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Log Message:
-----------
[gn] port a5dd6463608b
Commit: 752ef93392b2d049064dc77087bf414d69283cfc
https://github.com/llvm/llvm-project/commit/752ef93392b2d049064dc77087bf414d69283cfc
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/MC/AArch64/local-bounds-single-trap.ll
Log Message:
-----------
[NFC][clang] Fix header comment in llvm/test/MC/AArch64/local-bounds-single-trap.ll (#117642)
llvm/test/MC/AArch64/local-bounds-single-trap.ll was introduced in
https://github.com/llvm/llvm-project/pull/65972 to demonstrate that
nomerge did not work properly, which is documented in the header
comment.
https://github.com/llvm/llvm-project/pull/101549 fixed nomerge for trap
builtins and
https://github.com/llvm/llvm-project/commit/ae6dc64ec670891cb15049277e43133d4df7fb4b
updated the test assertions, but not the header comment. This patch
updates the header comment accordingly.
Commit: 5bdcaf1a0804799106bc864215ba03af4b762966
https://github.com/llvm/llvm-project/commit/5bdcaf1a0804799106bc864215ba03af4b762966
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/docs/GitHub.rst
Log Message:
-----------
[github] Document the process for requesting the CI/CD role (#115321)
See https://discourse.llvm.org/t/rfc-proposing-a-new-ci-cd-admin-for-the-project
Commit: 44ef12b020c07d195519d0613d21f3b8ab29a22d
https://github.com/llvm/llvm-project/commit/44ef12b020c07d195519d0613d21f3b8ab29a22d
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A libcxx/test/std/containers/sequences/vector/addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_copy.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_size_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.special/swap.addressof.compile.pass.cpp
Log Message:
-----------
[libc++] Refactor tests for hijacked address operator in vector (#117457)
This reduces the amount of boilerplate needed to implement the tests.
Commit: e57b327be27bd185595a3383dfac90ec6651c123
https://github.com/llvm/llvm-project/commit/e57b327be27bd185595a3383dfac90ec6651c123
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
Log Message:
-----------
AMDGPU: Legalize fminimum and fmaximum f32 for gfx950 (#117634)
Select to minimum3/maximum3. Leave f16/v2f16 for later
since it's complicated by only having the vector version.
Commit: f5e92eb04b5d9b708d38e3616df998ecdf9afc20
https://github.com/llvm/llvm-project/commit/f5e92eb04b5d9b708d38e3616df998ecdf9afc20
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
Log Message:
-----------
AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (#117737)
Commit: 7221bc74bc6b038b40c00d5111555ea87b326bf3
https://github.com/llvm/llvm-project/commit/7221bc74bc6b038b40c00d5111555ea87b326bf3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
Log Message:
-----------
AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (#117738)
Commit: 815069c701d62b58b8dbb6e902931f9eb5185db4
https://github.com/llvm/llvm-project/commit/815069c701d62b58b8dbb6e902931f9eb5185db4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (#117739)
OPSEL[1:0] collectively decide which byte to read
from src input.
Builtin takes additional imm argument which
represents index (with valid values:[0:3]) of src
byte read. Out of bounds checks will added in next
patch.
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Inst{13} i.e. OPSEL[2] is ignored in
asm syntax and opsel[z] is meaningless
for v_cvt_scalef32_f32_{fp|bf}8
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 803bd812b16d1454b8fc0d6d66d7da793408b34d
https://github.com/llvm/llvm-project/commit/803bd812b16d1454b8fc0d6d66d7da793408b34d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (#117740)
OPSEL[3] determines low/high 16 bits of word to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c9562b181cafafba104cccd7334ace1fd6aee5ac
https://github.com/llvm/llvm-project/commit/c9562b181cafafba104cccd7334ace1fd6aee5ac
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
Log Message:
-----------
[gn] port 3cb28522ba4c
Commit: c71418574f1bb9e4678428901775c8b633cded09
https://github.com/llvm/llvm-project/commit/c71418574f1bb9e4678428901775c8b633cded09
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/complex/generic/CMakeLists.txt
M libc/src/pthread/CMakeLists.txt
M libc/src/setjmp/riscv/CMakeLists.txt
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/stdfix/CMakeLists.txt
M libc/src/string/CMakeLists.txt
M libc/src/threads/CMakeLists.txt
M libc/test/src/math/smoke/LdExpTest.h
Log Message:
-----------
[libc] suppress more clang-cl warnings (#117718)
- migrate more `-O3` to `${libc_opt_high_flag}`
- workaround a issue with `LLP64` in test. The overflow testing is
guarded by a constexpr but the literal overflow itself will still
trigger warnings.
Notice that for math smoke test, for some reasons, the
`${libc_opt_high_flag}` will be passed into `lld-link` which confuses
the linker so there are still some warnings leftover there. I can
investigate more when I have time.
Commit: 0719b6d936d628c4c1765a9e700387ddd77759b9
https://github.com/llvm/llvm-project/commit/0719b6d936d628c4c1765a9e700387ddd77759b9
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
R clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RWBuffer-AST.hlsl
R clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
A clang/test/AST/HLSL/TypedBuffers-AST.hlsl
Log Message:
-----------
[HLSL][NFC] Refactor resource buffers AST tests (#117659)
This is a test-only change. This PR merges 5 tests for structured
buffers ASTs into one file with multiple run lines and check prefixes
because these tests have a lot of common output. It also renames
RWBuffer-AST.hlsl to TypedBuffers-AST.hlsl and makes it ready to include
testing of other typed buffers as well.
Fixes #115412
Commit: 46a08579f2b86e39b367b83ff4ca0e92302d2168
https://github.com/llvm/llvm-project/commit/46a08579f2b86e39b367b83ff4ca0e92302d2168
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/GVN/noalias.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-loads.ll
M llvm/test/Transforms/NewGVN/noalias.ll
Log Message:
-----------
[Local] Only intersect alias.scope,noalias & parallel_loop if inst moves (#117716)
Preserve !alias.scope, !noalias and !mem.parallel_loop_access metadata
on the replacement instruction, if it does not move. In that case, the
program would be UB, if the aliasing property encoded in the metadata
does not hold. This makes use of the clarification re aliasing metadata
implying UB if the property does not hold: #116220
Same as #115868, but for !alias.scope, !noalias and
!mem.parallel_loop_access.
PR: https://github.com/llvm/llvm-project/pull/117716
Commit: cefc1b0c211fcc3f5528b72d5883f0c390d63e71
https://github.com/llvm/llvm-project/commit/cefc1b0c211fcc3f5528b72d5883f0c390d63e71
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/aa-recursion-assertion-failure.ll
M llvm/test/Transforms/MergedLoadStoreMotion/st_sink_debuginvariant.ll
M llvm/test/Transforms/NewGVN/2010-03-31-RedundantPHIs.ll
M llvm/test/Transforms/NewGVN/2010-05-08-OneBit.ll
M llvm/test/Transforms/NewGVN/2011-04-27-phioperands.ll
M llvm/test/Transforms/NewGVN/2012-05-22-PreCrash.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/completeness.ll
M llvm/test/Transforms/NewGVN/crash.ll
M llvm/test/Transforms/NewGVN/deadstore.ll
M llvm/test/Transforms/NewGVN/eliminate-ssacopy.ll
M llvm/test/Transforms/NewGVN/metadata-nonnull.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-move-block.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
M llvm/test/Transforms/NewGVN/pr25440.ll
M llvm/test/Transforms/NewGVN/pr31594.ll
M llvm/test/Transforms/NewGVN/pr31613.ll
M llvm/test/Transforms/NewGVN/pr31682.ll
M llvm/test/Transforms/NewGVN/pr32403.ll
M llvm/test/Transforms/NewGVN/pr32838.ll
M llvm/test/Transforms/NewGVN/pr32845.ll
M llvm/test/Transforms/NewGVN/pr32897.ll
M llvm/test/Transforms/NewGVN/pr32934.ll
M llvm/test/Transforms/NewGVN/pr33014.ll
M llvm/test/Transforms/NewGVN/pr33086.ll
M llvm/test/Transforms/NewGVN/pr33116.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33204.ll
M llvm/test/Transforms/NewGVN/pr33432.ll
M llvm/test/Transforms/NewGVN/pr33720.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr35074.ll
M llvm/test/Transforms/NewGVN/pr42422-phi-of-ops.ll
M llvm/test/Transforms/NewGVN/pr43441.ll
M llvm/test/Transforms/NewGVN/pre-new-inst-xfail.ll
M llvm/test/Transforms/NewGVN/predicates.ll
M llvm/test/Transforms/NewGVN/refine-stores.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` from some regression tests [NFC] (#117292)
This PR removes tests with `br i1 undef` under
`llvm/tests/Transforms/MemCpyOpt, MergedLoadStoreMotion, NewGVN`.
Commit: 5ce981e76da4094efd055ded54d1f756b1286f18
https://github.com/llvm/llvm-project/commit/5ce981e76da4094efd055ded54d1f756b1286f18
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__vector/vector.h
M libcxx/test/std/containers/sequences/vector/vector.cons/exceptions.pass.cpp
Log Message:
-----------
[libc++] Refactor vector move constructor with allocator (#116449)
This PR simplifies the implementation of std::vector's move constructor
with an alternative allocator by invoking __init_with_size() instead of
calling assign(), which ultimately calls __assign_with_size(). The
advantage of using __init_with_size() lies in its internal use of
an exception guard, which simplifies the code. Furthermore, from a
semantic standpoint, it is more intuitive for a constructor to call
an initialization function than an assignment function.
Commit: 9118d3a564f271006b0d8aed0983f7ba025e77a0
https://github.com/llvm/llvm-project/commit/9118d3a564f271006b0d8aed0983f7ba025e77a0
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
Log Message:
-----------
gn build: Fix port of 3cb28522ba4c
COMPILER_RT_EXEC_OUTPUT_DIR is expected to be the path where
hwasan_symbolize is installed, i.e. the bin subdirectory of the
build directory, but we were incorrectly setting it to the install
location of the runtime libraries. Fix it.
Commit: 105b7803ea22823a2fca2a82ee843d0884e9cbf3
https://github.com/llvm/llvm-project/commit/105b7803ea22823a2fca2a82ee843d0884e9cbf3
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port f9dca5bdbb0f
Commit: 8458bbe5947db75041579c7c1a0f7f79c8e992d9
https://github.com/llvm/llvm-project/commit/8458bbe5947db75041579c7c1a0f7f79c8e992d9
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__split_buffer
Log Message:
-----------
[libc++] Fix capacity increase issue with `shrink_to_fit` for `__split_buffer` (#117720)
This PR fixes the issue where `__split_buffer::shrink_to_fit` may
unexpectedly increase the capacity, similar to the issue for
`std::vector` in #97895. The fix follows the same approach
used in #97895 for `std::vector`.
Commit: 003b48e0cbbb69a9a1ca9ff1a6d3bda30d0c6121
https://github.com/llvm/llvm-project/commit/003b48e0cbbb69a9a1ca9ff1a6d3bda30d0c6121
Author: Raul Tambre <raul at tambre.ee>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/test/AArch64/data-at-0-offset.c
M bolt/test/AArch64/double_jump.cpp
M bolt/test/R_ABS.pic.lld.cpp
M bolt/test/X86/double-jump.test
M bolt/test/X86/dwarf5-df-inlined-subroutine-gc-sections-range.test
M bolt/test/X86/jmp-optimization.test
M bolt/test/X86/match-functions-with-call-graph.test
M bolt/test/pie.test
M bolt/test/runtime/X86/instrumentation-indirect.c
M bolt/test/runtime/bolt-reserved.cpp
Log Message:
-----------
[BOLT][test] enable GNU extensions, use C++ compiler, remove unnecessary target (#117043)
1. With a Clang that doesn't default to GNU extensions they need to be enabled explicitly.
2. The X86 directory lit config sets it already, there's no reason for this test to do it by itself.
3. The C frontend executable will fail if there's for example a Clang resource file for the C++ mode that sets C++-specific options:
```
+ /home/tambre/dev/llvm/build/bin/clang --target=x86_64-unknown-linux-gnu -fPIE -fuse-ld=lld -Wl,--unresolved-symbols=ignore-all -pie -fPIC -shared /home/tambre/dev/llvm/bolt/test/R_ABS.pic.lld.cpp -o /home/tambre/dev/llvm/build/tools/bolt/test/Output/R_ABS.pic.lld.cpp.tmp.so -Wl,-q -fuse-ld=lld
clang: warning: argument unused during compilation: '-pie' [-Wunused-command-line-argument]
error: invalid argument '-std=c23' not allowed with 'C++'
```
Commit: 2d90af59084d842a343f9acf6ae7c1e61991873c
https://github.com/llvm/llvm-project/commit/2d90af59084d842a343f9acf6ae7c1e61991873c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Parser/unparse.cpp
A flang/test/Parser/OpenMP/bind-clause.f90
Log Message:
-----------
[flang][OpenMP] Add unparsing of BIND clause argument (#117776)
Currently the argument of the BIND clause is not printed. This is likely
an omission in the original implementation.
Commit: 1b68b33ac0b3c2c8bd2ab89fec4f516f622cebdf
https://github.com/llvm/llvm-project/commit/1b68b33ac0b3c2c8bd2ab89fec4f516f622cebdf
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge (#117649)
This test (copied from https://github.com/llvm/llvm-project/pull/83470)
demonstrates that UBSan does not add the nomerge annotation. This is
significant because it can result in them being merged by the backend,
even when -ubsan-unique-traps is enabled.
N.B. https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011.
https://github.com/llvm/llvm-project/pull/101549 fixed that limitation
("It sets nomerge flag for the node if the instruction has nomerge
arrtibute."); planned upcoming work
(https://github.com/llvm/llvm-project/pull/117651) will add nomerge for
ubsan.
Commit: dde7f4d024d071d883cfb7812f31866e767b6ab9
https://github.com/llvm/llvm-project/commit/dde7f4d024d071d883cfb7812f31866e767b6ab9
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/ubsan-trap-merge.ll
A llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
Log Message:
-----------
[NFC][clang] Add ubsan-trap-merge.ll test to show absence of nomerge considered harmful (#117657)
These testcases demonstrate that ubsan intrinsics are merged in the
backend iff nomerge is missing from ubsantrap intrinsics.
This is based on the observation and testcase by Vitaly Buka in
https://github.com/llvm/llvm-project/pull/83470.
Commit: 81349b84eb0fd2d64f836ddbf3e28638d4a254b8
https://github.com/llvm/llvm-project/commit/81349b84eb0fd2d64f836ddbf3e28638d4a254b8
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
Log Message:
-----------
[sanitizer] Use /tmp/ not /tmp/dir/ in tests (#117759)
Tests fail if the user doesn't own /tmp/dir/. On hosts with multiple
users running the test suite, who owns /tmp/dir/ can become a race.
Commit: c8bdb31ff66e8934060c60816c57925fdec42a2c
https://github.com/llvm/llvm-project/commit/c8bdb31ff66e8934060c60816c57925fdec42a2c
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
R clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
Revert "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge" (#117804)
Reverts llvm/llvm-project#117649
Reason: buildbot breakage:
https://lab.llvm.org/buildbot/#/builders/144/builds/12581
Commit: 8ffe63fb556915c041e8e9bc2d1bf4325f12ba26
https://github.com/llvm/llvm-project/commit/8ffe63fb556915c041e8e9bc2d1bf4325f12ba26
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[nfc][asan] Fix typo in comment
Commit: 5add295fd77e29f090515668f95d362d98583856
https://github.com/llvm/llvm-project/commit/5add295fd77e29f090515668f95d362d98583856
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use IndexedMemProfRecord in MemProfReader (NFC) (#117613)
IndexedMemProfRecord contains a complete package of the MemProf
profile, including frames, call stacks, and records. This patch
replaces the three member variables of MemProfReader with
IndexedMemProfRecord.
This transition significantly simplies both the constructor and the
final "take" method:
MemProfReader(IndexedMemProfData MemProfData)
: MemProfData(std::move(MemProfData)) {}
IndexedMemProfData takeMemProfData() { return std::move(MemProfData); }
Commit: 36a46d85e75e3be35c6b62002717f531b86d8368
https://github.com/llvm/llvm-project/commit/36a46d85e75e3be35c6b62002717f531b86d8368
Author: Omar Hossam <moar.ahmed at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] Implement process_mrelease. (#117503)
This PR addresses #110124.
Commit: 9fde1a498f2dc97a737a3564cb427c6f2a7bfe6c
https://github.com/llvm/llvm-project/commit/9fde1a498f2dc97a737a3564cb427c6f2a7bfe6c
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
Log Message:
-----------
[HLSL] Forward arguments in BuiltinTypeMethodBuilder::callBuiltin. NFC (#117789)
Introduce BuiltinTypeMethodBuilder::PlaceHolder values and use them in
the callBuiltin method in order to specify how we want to forward
arguments and pass the resource handle to builtins.
Commit: 09e7477c0f1f192d3e5bb9735301c2deec9a3d96
https://github.com/llvm/llvm-project/commit/09e7477c0f1f192d3e5bb9735301c2deec9a3d96
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
Log Message:
-----------
[memprof] Add a default constructor to Frame (#117790)
This patch adds a default constructor to Frame along with a use in
FrameIdConverter.
The real intent is to facilitate deserialization of YAML-based MemProf
format. Note that the YAML parser default-constructs a struct and
then populates one field at a time.
Commit: 7ae61a36f94679370b9c1b4b1a13999d23d38a0c
https://github.com/llvm/llvm-project/commit/7ae61a36f94679370b9c1b4b1a13999d23d38a0c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/detected_or.h
M libcxx/include/module.modulemap
Log Message:
-----------
[libc++] Add __detected_or_t and use it to implement some of the allocator traits aliases (#115654)
This simplifies the implementation a bit, since we don't need a lot of
the `__has_x` classes anymore. We just need two template aliases to
implement the `allocator_traits` aliases now.
Commit: 39601a6e5484de183bf525b7d0624e7890ccd8ab
https://github.com/llvm/llvm-project/commit/39601a6e5484de183bf525b7d0624e7890ccd8ab
Author: AdityaK <hiraditya at msn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/SimplifyCFG/switch-branch-fold-indirectbr-102351.ll
Log Message:
-----------
Bail out jump threading on indirect branches only (#117778)
Remove check for PHI in pred as pointed out in #103688
Reduced the testcase to remove redundant phi in pred
Fixes: #102351
Commit: 47dbf359041299c5f19f82e7204c6c9675b6e69a
https://github.com/llvm/llvm-project/commit/47dbf359041299c5f19f82e7204c6c9675b6e69a
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
Reapply "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge" (#117804) (#117805)
This reverts commit c8bdb31ff66e8934060c60816c57925fdec42a2c.
It was reverted because I forgot to update the auto-generated assertions
after adding the target triple.
Original commit message:
This test (copied from https://github.com/llvm/llvm-project/pull/83470)
demonstrates that UBSan does not add the nomerge annotation. This is
significant because it can result in them being merged by the backend,
even when -ubsan-unique-traps is enabled.
N.B. https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011.
https://github.com/llvm/llvm-project/pull/101549 fixed that limitation
("It sets nomerge flag for the node if the instruction has nomerge
arrtibute."); planned upcoming work
(https://github.com/llvm/llvm-project/pull/117651) will add nomerge for
ubsan.
Commit: e1af76cad265694f1799d46de455f18c931ae2b7
https://github.com/llvm/llvm-project/commit/e1af76cad265694f1799d46de455f18c931ae2b7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 7ae61a36f946
Commit: 3372303188df0f7f8ac26e7ab610cf8b0f716d42
https://github.com/llvm/llvm-project/commit/3372303188df0f7f8ac26e7ab610cf8b0f716d42
Author: lntue <lntue at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
R libc/src/sys/mman/linux/process_mrelease.cpp
R libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
R libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
Revert "[libc] Implement process_mrelease." (#117807)
Reverts llvm/llvm-project#117503
Commit: 3a8b28f69837f8502c7bce798509f8dadb314dcc
https://github.com/llvm/llvm-project/commit/3a8b28f69837f8502c7bce798509f8dadb314dcc
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan] Add ioctl interceptor (#117569)
Commit: 3359806817d5d3a600e3f0bdae60ac3df1c85e7f
https://github.com/llvm/llvm-project/commit/3359806817d5d3a600e3f0bdae60ac3df1c85e7f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
Log Message:
-----------
[mlir][LLVM][MemRef] Lower assume_alignment with operand bundles (#117800)
Now that LLVM allows a operand bundle on assume calls to directly
specify alignment assumptions, change the lowering of
memref.assume_alignment to use that feature instead of the ptrtoint
method.
This makes LLVM's job easier and prevents issues when dealing with
cases where ptrtoint isn't a desired operation (like those with poiner
provenance)
Commit: e84614833e52ce9a7bebfa8d0d1af3298b6977b9
https://github.com/llvm/llvm-project/commit/e84614833e52ce9a7bebfa8d0d1af3298b6977b9
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/div.ll
Log Message:
-----------
[LLVM][NVPTX] Add support for div.full instruction (#116482)
This commit adds NVPTX support for div.full PTX instruction with test
under div.ll. [For more information, see PTX
ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-div)
Commit: 06d24da1312aa5c0c615a3b6c4dffe1c104e0cf3
https://github.com/llvm/llvm-project/commit/06d24da1312aa5c0c615a3b6c4dffe1c104e0cf3
Author: B I Mohammed Abbas <bimohammadabbas at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/test/builtins/Unit/extendhfxf2_test.c
M compiler-rt/test/builtins/Unit/fp_test.h
Log Message:
-----------
Fix extendhfxf2 test (#117665)
Fix changes in #113897
Co-authored-by: Alex Richardson <alexrichardson at google.com>
Commit: a94cec521202b00d18eaa55d9a5a4616097f5abf
https://github.com/llvm/llvm-project/commit/a94cec521202b00d18eaa55d9a5a4616097f5abf
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
Revert "[libc++] Remove workaround which allows setting _LIBCPP_OVERRIDABLE_FUNC_VIS externally (#113139)" (#117779)
This reverts commit 2e686d6d17c4cc7608510a856055e6ca79fcb917.
See https://github.com/llvm/llvm-project/issues/117571
Commit: 43b6b78771e9ab4da912b574664e713758c43110
https://github.com/llvm/llvm-project/commit/43b6b78771e9ab4da912b574664e713758c43110
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
Log Message:
-----------
[RISCV][GISel] Use libcalls for f32/f64 G_FCMP without F/D extensions. (#117660)
LegalizerHelp only supported f128 libcalls and incorrectly assumed that
the destination register for the G_FCMP was s32.
Commit: 06514c550105b3111c23751421265c318bd69ac6
https://github.com/llvm/llvm-project/commit/06514c550105b3111c23751421265c318bd69ac6
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/IR/AffineMap.h
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/test/Dialect/Linalg/fusion-elementwise.mlir
Log Message:
-----------
[MLIR][Linalg] Fix linalg crash during elementwise op fusion (#117667)
`isOpOperandCanBeDroppedAfterFusedLinalgs` crashes when `indexingMaps`
is empty. This can occur when `producer` only has DPS init operands and
`consumer ` only has a single DPS input operand (all operands are
ignored and nothing gets added to `indexingMaps`). This is because
`concatAffineMaps` wasn't handling the maps being empty properly.
Similar to `canOpOperandsBeDroppedImpl`, I added an early return when
the maps are of size zero. Additionally, `concatAffineMaps`'s
declaration comment says it returns an empty map when `maps` is empty
but it has no way to get the `MLIRContext` needed to construct the empty
affine map when the array is empty. So, I changed this to take the
context.
__NOTE: concatAffineMaps now takes an MLIRContext to be able to
construct an empty map in the case where `maps` is empty.__
---------
Signed-off-by: Ian Wood <ianwood2024 at u.northwestern.edu>
Co-authored-by: Quinn Dawkins <quinn.dawkins at gmail.com>
Commit: 5147e5941d40ae89b6ecab89aa36f8f5def28f1e
https://github.com/llvm/llvm-project/commit/5147e5941d40ae89b6ecab89aa36f8f5def28f1e
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/lib/DebugInfo/GSYM/CMakeLists.txt
A llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-dsym.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-exe.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-obj.test
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
Log Message:
-----------
[GSYM] Callsites: Add data format support and loading from YAML (#109781)
This PR adds support in the gSYM format for call site information and
adds support for loading call sites from a YAML file. The support for
YAML input is mostly for testing purposes - so we have a way to test the
functionality.
Note that this data is not currently used in the gSYM tooling - the
logic to use call sites will be added in a later PR.
The reason why we need call site information in gSYM files is so that we
can support better call stack function disambiguation in the case where
multiple functions have been merged due to optimization (linker ICF).
When resolving a merged function on the callstack, we can use the call
site information of the calling function to narrow down the actual
function that is being called, from the set of all merged functions.
See [this
RFC](https://discourse.llvm.org/t/rfc-extending-gsym-format-with-call-site-information-for-merged-function-disambiguation/80682)
for more details on this change.
Commit: 62584f32eb786e4c455092e653a58182e8ffe4dc
https://github.com/llvm/llvm-project/commit/62584f32eb786e4c455092e653a58182e8ffe4dc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (#117741)
OPSEL[0] determines low/high 16 bits of src0 to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 4527894143a2749d826769e78ab4e0f50782b188
https://github.com/llvm/llvm-project/commit/4527894143a2749d826769e78ab4e0f50782b188
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (#117742)
OPSEL[3] determines low/high 16 bits of word to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 2b9e947d4346ad03328a31f90b9056837c042d1b
https://github.com/llvm/llvm-project/commit/2b9e947d4346ad03328a31f90b9056837c042d1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (#117743)
OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d]
where, c & d i.e. OPSEL[3 : 2] selects which dst_byte to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: eeb76880f3489f1e7e6224a26ec4abc7f6da4e34
https://github.com/llvm/llvm-project/commit/eeb76880f3489f1e7e6224a26ec4abc7f6da4e34
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (#117744)
OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 0f4fcca546a489f50535086a313f8c054ea41791
https://github.com/llvm/llvm-project/commit/0f4fcca546a489f50535086a313f8c054ea41791
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (#117745)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 991dcbc468763953f4b4e65fa3448e147cba5bba
https://github.com/llvm/llvm-project/commit/991dcbc468763953f4b4e65fa3448e147cba5bba
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (#117747)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 065dc93d9626930b48f8e88b1e0a18c746951ce0
https://github.com/llvm/llvm-project/commit/065dc93d9626930b48f8e88b1e0a18c746951ce0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (#117793)
OPSEL[0] selects src_word to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c8ee1ee0571c5e49bee42983a8b9d8db0243c001
https://github.com/llvm/llvm-project/commit/c8ee1ee0571c5e49bee42983a8b9d8db0243c001
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (#117794)
These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
OPSEL ASM OPSEL Syntax: opsel:[a,b,c,d]
a & b are meaningless, c & d together decides byte to write in dst reg.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 175e0dd4223b7678f660519a9342282e8b226093
https://github.com/llvm/llvm-project/commit/175e0dd4223b7678f660519a9342282e8b226093
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
Log Message:
-----------
[MachineLateInstrsCleanup] Minor fixing (NFC). (#117816)
With cb57b7a7, MachineLateInstrsCleanup switched to using a map to keep
track of kill flags to remedy compile time regressions seen with huge
functions. It seems that the comment above clearKillsForDef() became stale with
that commit, and also that one of the arguments to it became unused,
both of which this patch fixes.
Commit: d3c103b80e6e8b001c2a22bd2f7afbdcf1f7b70a
https://github.com/llvm/llvm-project/commit/d3c103b80e6e8b001c2a22bd2f7afbdcf1f7b70a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (#117795)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: e335563806e0466f33ecce80a9fd5a39a3aead47
https://github.com/llvm/llvm-project/commit/e335563806e0466f33ecce80a9fd5a39a3aead47
Author: David Truby <david.truby at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M flang/unittests/Runtime/CMakeLists.txt
M flang/unittests/Runtime/CommandTest.cpp
Log Message:
-----------
[NFC][flang] Fix execute_command_line test for odd environments (#117714)
One of the execute_command_line tests currently runs `cat` on an invalid
file and checks its return value, but since we don't control `cat` or
the user's path, the return value might not be reliably stable on a
per-platform basis. For example, if `git` is installed on Windows in
certain configurations it adds a directory to the path containing a
`cat` with a different set of error codes to the default Windows one.
This patch changes the test to use the `not` binary built by LLVM for
testing purposes, which should always return 1 on any platform
regardless of the user's environment.
Commit: 34a8bb0da33ce95aa4dec61ad24fbf4049176189
https://github.com/llvm/llvm-project/commit/34a8bb0da33ce95aa4dec61ad24fbf4049176189
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (#117796)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: f87cabea26c3bcfdf9315c3ade2bf830692ddb3d
https://github.com/llvm/llvm-project/commit/f87cabea26c3bcfdf9315c3ade2bf830692ddb3d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (#117797)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 2ff2e871f5e632ea493efaf4f2192f8b18a54ab1
https://github.com/llvm/llvm-project/commit/2ff2e871f5e632ea493efaf4f2192f8b18a54ab1
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
Log Message:
-----------
[mlir][bufferization] Remove remaining dialect conversion-based infra parts (#114155)
This commit removes the last remaining components of the dialect
conversion-based bufferization passes.
Note for LLVM integration: If you depend on these components, migrate to
One-Shot Bufferize or copy them to your codebase.
Commit: 76715787f4c1e23a618bccdb81049456526f7b42
https://github.com/llvm/llvm-project/commit/76715787f4c1e23a618bccdb81049456526f7b42
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (#117798)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: f2129ca94c47875b5f915abc9d7dfb02a7445fe6
https://github.com/llvm/llvm-project/commit/f2129ca94c47875b5f915abc9d7dfb02a7445fe6
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
Log Message:
-----------
[lldb][NFC] Whitespace fix for mis-indented block
This mis-indented block makes a FC change I'm about
to propose look larger than it is when clang-formatted.
Commit: 4d2bc0adc63cf90111d849911ccdddaa0d886e60
https://github.com/llvm/llvm-project/commit/4d2bc0adc63cf90111d849911ccdddaa0d886e60
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
Log Message:
-----------
[BOLT] Extract comparator for sorting functions by index into helper function (#116217)
This change extracts the comparator for sorting functions by index into
a helper function `compareBinaryFunctionByIndex()`
Not sure why the comparator used in
`BinaryContext::getSortedFunctions()` is not same as the other two
places. I think they should use the same comparator, so I also change
`BinaryContext::getSortedFunctions()` to use
`compareBinaryFunctionByIndex()` for sorting functions.
Commit: 3433e4140d18865fe784061a3cd029c5980f4e2f
https://github.com/llvm/llvm-project/commit/3433e4140d18865fe784061a3cd029c5980f4e2f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Detect constant on the rhs of data transfer (#117806)
When the rhs expression has some constants and a device symbol, an
implicit data transfer needs to be generated for the device symbol and
the computation with the constant is done on the host.
Commit: 0f0c0c36e3e90b4cb04004ed9c930f3863a36422
https://github.com/llvm/llvm-project/commit/0f0c0c36e3e90b4cb04004ed9c930f3863a36422
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/and-implied-by-operands.ll
M llvm/test/Transforms/ConstraintElimination/or.ll
Log Message:
-----------
[ConstraintElim] Extend `checkOrAndOpImpliedByOther` to handle and/or expr trees. (#117123)
This patch extends `checkOrAndOpImpliedByOther` to handle and/or trees.
Limitation: At least one of the operands of root and/or instruction
should be an icmp. That is, this patch doesn't support expressions like
`(cmp1 & cmp2) & (cmp3 & cmp4)`.
Closes https://github.com/llvm/llvm-project/issues/117107.
Compile-time impact:
http://llvm-compile-time-tracker.com/compare.php?from=69cc3f096ccbdef526bbd5a065a25c95122e87ee&to=919416d2c4c71e3b9fe533af2c168a36c7893be5&stat=instructions%3Au
Commit: ea58410d0fd75c9dc6d395bba15e939ed7c35cb1
https://github.com/llvm/llvm-project/commit/ea58410d0fd75c9dc6d395bba15e939ed7c35cb1
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/CodeGen/builtins-wasm.c
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
A llvm/test/CodeGen/WebAssembly/thread_pointer.ll
Log Message:
-----------
[WebAssembly] Implement %llvm.thread.pointer intrinsic (#117817)
We can simply use the `__tls_base` global for this which is guaranteed
to be non-zero and unique per thread.
Fixes: #117433
Commit: dd4844722d98a97edd180e20abd4e65e1e2dd9d7
https://github.com/llvm/llvm-project/commit/dd4844722d98a97edd180e20abd4e65e1e2dd9d7
Author: antangelo <contact at antangelo.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/IntrinsicLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
Log Message:
-----------
[SelectionDAG] Add generic implementation for @llvm.expect.with.probability when optimizations are disabled (#117459)
Handle \@llvm.expect.with.probability in SelectionDAGBuilder, FastISel,
and IntrinsicLowering in the same way \@llvm.expect is handled, where
the value is passed through as-is. This can be reached if the intrinsic
is used without optimizations, where it would otherwise be properly
transformed out.
Fixes #115411 for SelectionDAG. A similar patch is likely needed for
GlobalISel.
Commit: 73d1abb018fdd60664b49c3418572c2e04e18d41
https://github.com/llvm/llvm-project/commit/73d1abb018fdd60664b49c3418572c2e04e18d41
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/test/ELF/pack-dyn-relocs-tls-x86-64.s
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
Log Message:
-----------
[X86][LLD] Handle R_X86_64_CODE_4_GOTTPOFF relocation type (#116634)
For
mov name at GOTTPOFF(%rip), %reg
add name at GOTTPOFF(%rip), %reg
add
`R_X86_64_CODE_4_GOTTPOFF` = 44
in #116633.
Linker can treat `R_X86_64_CODE_4_GOTTPOFF` as `R_X86_64_GOTTPOFF` or
convert the instructions above to
mov $name, %reg
add $name, %reg
if the first byte of the instruction at the relocation `offset - 4` is
`0xd5` (namely, encoded w/REX2 prefix) when possible.
Binutils patch: https://github.com/bminor/binutils-gdb/commit/a533c8df598b5ef99c54a13e2b137c98b34b043c
Binutils mailthread: https://sourceware.org/pipermail/binutils/2023-December/131463.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/ACwD-UQXVDs/m/vrgTenKyFwAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: fad5ed6e908aafe03e47032611a6e836bbcc4d5a
https://github.com/llvm/llvm-project/commit/fad5ed6e908aafe03e47032611a6e836bbcc4d5a
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/test/ELF/invalid/x86-64-tlsdesc-gd.s
M lld/test/ELF/x86-64-tlsdesc-gd.s
Log Message:
-----------
[X86][LLD] Handle R_X86_64_CODE_4_GOTPC32_TLSDESC relocation type (#116909)
For
lea name at tlsdesc(%rip), %reg
add
R_X86_64_CODE_4_GOTPC32_TLSDESC = 45
in #116908.
Linker can treat R_X86_64_CODE_4_GOTPC32_TLSDESC as
R_X86_64_GOTPC32_TLSDESC or convert the instruction above to
mov $name at tpoff, %reg
if the first byte of the instruction at the relocation offset - 4 is
0xd5 (namely, encoded w/REX2 prefix) when possible.
Binutils patch: https://github.com/bminor/binutils-gdb/commit/a533c8df598b5ef99c54a13e2b137c98b34b043c
Binutils mailthread: https://sourceware.org/pipermail/binutils/2023-December/131463.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/ACwD-UQXVDs/m/vrgTenKyFwAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: b5825963f0f0d5e3fb8a0c0914bc5a27aa16440e
https://github.com/llvm/llvm-project/commit/b5825963f0f0d5e3fb8a0c0914bc5a27aa16440e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Materialize box when needed (#117810)
Materialize the box when the src comes from a embox or rebox operation.
This was done in the case of transfer to a descriptor but not when
transferring from a descriptor.
Commit: f9a39dfd18a1d428b5ec2ce38ad3b50ec6988e70
https://github.com/llvm/llvm-project/commit/f9a39dfd18a1d428b5ec2ce38ad3b50ec6988e70
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
Log Message:
-----------
[ORC] Fix typo in comment: instruction is ldr literal, not adr. NFC.
Commit: cc113102c6ea3d9d3d016c0804fee0c154f98ce1
https://github.com/llvm/llvm-project/commit/cc113102c6ea3d9d3d016c0804fee0c154f98ce1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/GSYM/BUILD.gn
Log Message:
-----------
[gn build] Port 5147e5941d40
Commit: 508448280a4fc8d1e29c5ccf883836aac0f11ec9
https://github.com/llvm/llvm-project/commit/508448280a4fc8d1e29c5ccf883836aac0f11ec9
Author: Helmut Januschka <helmut at januschka.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy] Enhance modernize-use-starts-ends-with to handle substr patterns (#116033)
Enhances the modernize-use-starts-ends-with check to detect additional patterns
using substr that can be replaced with starts_with() (C++20).
This enhancement improves code readability and can be more efficient by avoiding
temporary string creation.
Commit: 38a3cce90a2cc54ea9ad6bbdd63ccd61c32cfac9
https://github.com/llvm/llvm-project/commit/38a3cce90a2cc54ea9ad6bbdd63ccd61c32cfac9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
Log Message:
-----------
[RISCV][GISel] Copy fneg test cases from SelectionDAG into float/double-arith.ll. NFC
The test cases use fcmp which was not fully supported before
43b6b78771e9ab4da912b574664e713758c43110.
Commit: 90a776fbdb35ef6ac6f28a19937e88abd2e4611b
https://github.com/llvm/llvm-project/commit/90a776fbdb35ef6ac6f28a19937e88abd2e4611b
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
Log Message:
-----------
[clang][RISCV] __riscv_v_intrinsic macro doesn't need zve32x (#117356)
This macro is used to check if compiler supports RVV intrinsics, so it
should be defined no matter vector is enabled or not.
Resolved https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/376
Commit: 74449ab86b8bc8d7388ede0cc7fc3a679da0c567
https://github.com/llvm/llvm-project/commit/74449ab86b8bc8d7388ede0cc7fc3a679da0c567
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/lib/Serialization/ASTReader.cpp
M clang/test/Modules/explicit-build-missing-files.cpp
M clang/test/Modules/load_failure.c
M clang/test/Modules/mismatch-diagnostics.cpp
M clang/test/Modules/module-feature.m
M clang/test/Modules/pr62359.cppm
M clang/test/Modules/prebuilt-implicit-modules.m
M clang/test/PCH/arc.m
M clang/test/PCH/no-validate-pch.cl
M clang/test/PCH/pch-dir.c
Log Message:
-----------
[Serialization] Downgrade inconsistent flags from erros to warnings (#115416)
There were many many "voices" about the too strict flags checking in
modules. Although they rarely challenge this, maybe due to they respect
to the compiler implementation details. But from my point of view, there
are cases it is "fine" to have different flags. Especially we're too
conservative to mark almost language options in
`clang/include/clang/Basic/LangOptions.def` as incompatible options (see
the comments in the front of the file).
In my understanding, this should come from PCH initially since it is
natural to ask your headers to be compiled with the same flags with your
TU. And then, when Apple and Google goes to implement clang module, they
don't challenge it too since they have a closed world where they have a
strong control over the ecosystem so that they can make it consistent.
Yes, consistency is great and ODR violation are awful. But this is the
world we're living today. This is the C++'s ecosystem in the open ended
world. Image a situation that we're using a third party module and we
add a new option to our library, then the build bails out! THIS IS SUPER
ANNOYING. And makes it non practical to make a modular C++ ecosystem.
(
This was discussed many times in SG15. And the consensus is, the build
systems should generate different BMI based on different flags. But this
manner can't avoid ODR violation completely and it would add the times
of module files that need to be built, which may kill the benefit of
faster compilation of modules.
However, I think the build systems may need to do the similar things in
the end of the day. Considering libc++'s hardening mechanism
(https://libcxx.llvm.org/Hardening.html). So the conclusion of the
paragraph is, although this seems related to build systems, I think they
are actually unrelated story.
)
I think we should give our users a chance to disable such checks. It is
theoretically unsafe. But we've done our job to tell the users that it
**MAY** be bad. Then I feel it is C++-ish to give users more freedom
even if they may shoot their foot.
This shouldn't change any thing. Users who want previous behavior can
get it easily by `-Werror=`.
Commit: 4a7dbede6badd27ce2ad07984134d5d25a2bbada
https://github.com/llvm/llvm-project/commit/4a7dbede6badd27ce2ad07984134d5d25a2bbada
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Support `svukte` extension (#115657)
This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564,
https://lf-riscv.atlassian.net/browse/RVS-2977
The spec states that the `svukte` depends on `sv39`, but we don't have
`sv39` yet, so I didn't add it to the implied list.
Commit: 99de065b850b6e1c5461325998a40c6925d7ee9e
https://github.com/llvm/llvm-project/commit/99de065b850b6e1c5461325998a40c6925d7ee9e
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/lib/Serialization/ASTReader.cpp
M clang/test/Modules/explicit-build-missing-files.cpp
M clang/test/Modules/load_failure.c
M clang/test/Modules/mismatch-diagnostics.cpp
M clang/test/Modules/module-feature.m
M clang/test/Modules/pr62359.cppm
M clang/test/Modules/prebuilt-implicit-modules.m
M clang/test/PCH/arc.m
M clang/test/PCH/no-validate-pch.cl
M clang/test/PCH/pch-dir.c
Log Message:
-----------
Revert "[Serialization] Downgrade inconsistent flags from erros to warnings (#115416)"
This reverts commit 74449ab86b8bc8d7388ede0cc7fc3a679da0c567.
See the post commit message in
https://github.com/llvm/llvm-project/pull/115416
Commit: 512defe603dd0c82fb49bc6a3e1e8481ac0f6f9e
https://github.com/llvm/llvm-project/commit/512defe603dd0c82fb49bc6a3e1e8481ac0f6f9e
Author: antangelo <contact at antangelo.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
Log Message:
-----------
[NFC][GISel][AArch64] Pre-commit baseline tests for translation of @llvm.expect.with.probability (#117842)
Pre-commit of tests for generic GlobalISel translation of
`@llvm.expect.with.probability` for when optimizations are not enabled
Commit: 301c8e60474e09e0e537316cef6218c14562a9b9
https://github.com/llvm/llvm-project/commit/301c8e60474e09e0e537316cef6218c14562a9b9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_cvt_scalef32_sr instructions (#117820)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 265e209ceba8c330403d77f46a33b8e138c5633f
https://github.com/llvm/llvm-project/commit/265e209ceba8c330403d77f46a33b8e138c5633f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (#117821)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 142b33c58b26aae4d27f3f063eb492256beda3a6
https://github.com/llvm/llvm-project/commit/142b33c58b26aae4d27f3f063eb492256beda3a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
Log Message:
-----------
AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (#117822)
For multipass instructions, overlap on VDST and SRC’s
would result in HW race & undefined results.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 62dc8f3069cb08f9c955435e03a30c59228c6bb6
https://github.com/llvm/llvm-project/commit/62dc8f3069cb08f9c955435e03a30c59228c6bb6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
Log Message:
-----------
AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (#117823)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 561565720954a2de31ac8dfdb4fdd02ce1780030
https://github.com/llvm/llvm-project/commit/561565720954a2de31ac8dfdb4fdd02ce1780030
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (#117824)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: a2c3e0c4cb08e9cf26f4a745777295e1eb562e1b
https://github.com/llvm/llvm-project/commit/a2c3e0c4cb08e9cf26f4a745777295e1eb562e1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
A clang/test/SemaOpenCL/builtins-amdgcn-wave32-func-attr.cl
Log Message:
-----------
AMDGPU/clang: Add global_load_lds size check support for gfx950 (#117825)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: d9c4e9ffe78c34db247b164aa46eea2625b08d3a
https://github.com/llvm/llvm-project/commit/d9c4e9ffe78c34db247b164aa46eea2625b08d3a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/MC/AMDGPU/mai-gfx950-err.s
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
Log Message:
-----------
AMDGPU: Verify f8f6f4 formats in assembler (#117826)
Verify the register widths of the corresponding operands match
the floating point format expected size.
Commit: 61a23646c977f5530829742fdf5b901b7d9815a2
https://github.com/llvm/llvm-project/commit/61a23646c977f5530829742fdf5b901b7d9815a2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
M llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
A llvm/test/CodeGen/Generic/sjlj-eh-prepare.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
M llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll
M llvm/test/CodeGen/X86/sjlj-eh.ll
Log Message:
-----------
[SjLjEHPrepare] Configure call sites correctly (#117656)
After 9fe78db4, the pass inserts `store volatile i32 -1, ptr %call_site`
before all invoke instruction except the one in the entry block, which
has the effect of bypassing landing pads on exceptions.
When configuring the call site for a potentially throwing instruction
check that it is not `InvokeInst` -- they are handled by earlier code.
Commit: bc1e0c53a281822e08df89a02b02b6b0db222087
https://github.com/llvm/llvm-project/commit/bc1e0c53a281822e08df89a02b02b6b0db222087
Author: Josh Stone <jistone at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M compiler-rt/test/profile/Linux/binary-id-offset.c
Log Message:
-----------
[profile] Make the binary-id-offset.c test more robust (#117647)
Using a `--section-start` address in the test was causing link errors on
some targets. Now it uses a linker script to move the note after `.bss`,
which should still have the kind of memory offset we're looking for.
This is a follow-up to #114907 to fix buildbot errors.
Commit: 0d15d46362bd6ab5a9a2165805adaab13a7689f4
https://github.com/llvm/llvm-project/commit/0d15d46362bd6ab5a9a2165805adaab13a7689f4
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGen/bounds-checking.c
M clang/test/CodeGen/catch-undef-behavior.c
M clang/test/CodeGen/ubsan-trap-merge.c
M llvm/test/CodeGen/X86/ubsan-trap-merge.ll
M llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
Log Message:
-----------
[ubsan] Change ubsan-unique-traps to use nomerge instead of counter (#117651)
https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011. Instead, it added a
counter (based on TrapBB->getParent()->size()) to each ubsantrap call.
However, this counter is not guaranteed to be unique after inlining, as
shown by https://github.com/llvm/llvm-project/pull/83470, which can
result in ubsantraps being merged by the backend.
https://github.com/llvm/llvm-project/pull/101549 has since fixed the
nomerge limitation ("It sets nomerge flag for the node if the
instruction has nomerge arrtibute."). This patch therefore takes
advantage of nomerge instead of using the counter, guaranteeing that the
ubsantraps are not merged.
This patch is equivalent to
https://github.com/llvm/llvm-project/pull/83470 but also adds nomerge
and updates tests (https://github.com/llvm/llvm-project/pull/117649:
ubsan-trap-merge.c; https://github.com/llvm/llvm-project/pull/117657:
ubsan-trap-merge.ll, ubsan-trap-nomerge.ll; catch-undef-behavior.c).
Commit: 40d0058e6ad16d4716192a0e331ac58a6ed9def3
https://github.com/llvm/llvm-project/commit/40d0058e6ad16d4716192a0e331ac58a6ed9def3
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
A llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor reduction intrinsics (#116854)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.reduce.1D -> 5D variants, supporting both Tile
and Im2Col modes.
* These intrinsics optionally support cache_hints as indicated by the
boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in
cp-async-bulk-tensor-reduce.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 24eb2ae0a1803f0279facaca50001a1900d6bb85
https://github.com/llvm/llvm-project/commit/24eb2ae0a1803f0279facaca50001a1900d6bb85
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
Log Message:
-----------
[NVPTX] Fix a warning
This patch fixes:
llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp:452:3:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Commit: 6934870a134ce9000752f0613295596fb876e5c6
https://github.com/llvm/llvm-project/commit/6934870a134ce9000752f0613295596fb876e5c6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (#117827)
Commit: b4a16a78c2626d56864d4d6c0f9b2779e293914a
https://github.com/llvm/llvm-project/commit/b4a16a78c2626d56864d4d6c0f9b2779e293914a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/bitop3.ll
Log Message:
-----------
AMDGPU: Match and Select BITOP3 on gfx950 (#117843)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 53c0a25db7a0469f6d47e130d5a0e8f7a88b9585
https://github.com/llvm/llvm-project/commit/53c0a25db7a0469f6d47e130d5a0e8f7a88b9585
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
Log Message:
-----------
[LoongArch] Use div.w/mod.w to eliminate unnecessary sign-extend for sdiv/srem i32. (#117298)
Commit: 3618c9930f70b13b4e678ac04cb9f813056d560c
https://github.com/llvm/llvm-project/commit/3618c9930f70b13b4e678ac04cb9f813056d560c
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[MISched] Use right boundary when trying latency heuristics (#116592)
We may do bottom-up or bidirectional scheduling but previously we
assume we are doing top-down scheduling, which may cause some issues.
Commit: 6c7b988e64b60cff7e9f3777dfcc2b2511ee48c6
https://github.com/llvm/llvm-project/commit/6c7b988e64b60cff7e9f3777dfcc2b2511ee48c6
Author: 루밀LuMir <rpfos at naver.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/tools/clang-format/git-clang-format
Log Message:
-----------
[clang-format] Add mjs to default_extensions in git-clang-format (#117730)
Commit: 50dfb0772b3995c6e5543600b2813f56d0736442
https://github.com/llvm/llvm-project/commit/50dfb0772b3995c6e5543600b2813f56d0736442
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV] Support f32/f64 libcalls for sin/cos/pow/log/log2/log10/exp/exp2
Test cases copied from SelectionDAG.
Commit: c00e53208db638c35499fc80b555f8e14baa35f0
https://github.com/llvm/llvm-project/commit/c00e53208db638c35499fc80b555f8e14baa35f0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Add YAML-based deserialization for MemProf profile (#117829)
This patch adds YAML-based deserialization for MemProf profile.
It's been painful to write tests for MemProf passes because we do not
have a text format for the MemProf profile. We would write a test
case in C++, run it for a binary MemProf profile, and then finally run
a test written in LLVM IR with the binary profile.
This patch paves the way toward YAML-based MemProf profile.
Specifically, it adds new class YAMLMemProfReader derived from
MemProfReader. For now, it only adds a function to parse StringRef
pointing to YAML data. Subseqeunt patches will wire it to
llvm-profdata and read from a file.
The field names are based on various printYAML functions in MemProf.h.
I'm not aiming for compatibility with the format used in printYAML,
but I don't see a point in changing the field names.
Commit: e636434bdf74cf40071b776ef05aafbf161ce4cd
https://github.com/llvm/llvm-project/commit/e636434bdf74cf40071b776ef05aafbf161ce4cd
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
Log Message:
-----------
[BasicAA][LAA] Don't use same-block phis in cross iteration mode (#116802)
In 4de3184f07fd8c548125d315dd306d4afa7c9698 we exposed BasicAA's
cross-iteration mode for use in LAA, so we can handle selects with equal
conditions correctly (where the select condition is not actually equal
across iterations).
However, if we replace the selects with equivalent phis, the issue still
exists. In the phi case, we effectively still have an assumption that
the condition(s) that control which phi arg is used will be the same
across iterations. Fix this by disabling this phi handling in
cross-iteration mode.
(I'm not entirely sure whether this is also needed when BasicAA enables
cross-iteration mode during internal phi recursion, but I wouldn't be
surprised if that's the case.)
Commit: 204d7153629db22c44a313733a5469cd6f7056df
https://github.com/llvm/llvm-project/commit/204d7153629db22c44a313733a5469cd6f7056df
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][vector] Add more tests for ConvertVectorToLLVM (11/n) (#117160)
Adds tests with scalable vectors for the Vector-To-LLVM conversion pass.
Covers the following Ops:
* `vector.splat`.
In addition:
* Removed `@make_fixed_vector_of_scalable_vect`, which duplicated
`@broadcast_vec2d_from_scalar_scalable` (and wasn't grouped with other
tests for `vector.broadcast`).
* Moved `@vector_bitcast_2d` near other tests for `vector.bitcast` and
added a variant with scalable vectors.
Commit: 4dfa0216ba7849fde270f27e2358d4327fac988d
https://github.com/llvm/llvm-project/commit/4dfa0216ba7849fde270f27e2358d4327fac988d
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/string.c
M clang/test/Analysis/string.cpp
A clang/test/Analysis/string_notnullterm.c
Log Message:
-----------
[clang][analyzer] Bring checker 'alpha.unix.cstring.NotNullTerminated' out of alpha (#113899)
Commit: 072387042021b0f74c24c617b940fe8157f9f1a5
https://github.com/llvm/llvm-project/commit/072387042021b0f74c24c617b940fe8157f9f1a5
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
Log Message:
-----------
[lldb] Add timeout argument to Socket::Accept (#117691)
Allows us to stop waiting for a connection if it doesn't come in a
certain amount of time. Right now, I'm keeping the status quo (infitnite
wait) in the "production" code, but using smaller (finite) values in
tests. (A lot of these tests create "loopback" connections, where a
really short wait is sufficient: on linux at least even a poll (0s wait)
is sufficient if the other end has connect()ed already, but this doesn't
seem to be the case on Windows, so I'm using a 1s wait in these cases).
Commit: e8a01e75e6b17e84710e7cc3bfb70d95a3a696a2
https://github.com/llvm/llvm-project/commit/e8a01e75e6b17e84710e7cc3bfb70d95a3a696a2
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/include/lldb/Symbol/Block.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
Log Message:
-----------
[lldb] Make sure Blocks always have a parent (#117683)
It's basically true already (except for a brief time during
construction). This patch makes sure the objects are constructed with a
valid parent and enforces this in the type system, which allows us to
get rid of some nullptr checks.
Commit: 7e312c3b90cad9358d863b9b74de75d4da632845
https://github.com/llvm/llvm-project/commit/7e312c3b90cad9358d863b9b74de75d4da632845
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
Revert "[memprof] Add YAML-based deserialization for MemProf profile (#117829)"
This reverts commit c00e53208db638c35499fc80b555f8e14baa35f0.
It looks like this breaks building LLVM on macOS and some other
platform/compiler combos
https://lab.llvm.org/buildbot/#/builders/23/builds/5252
https://green.lab.llvm.org/job/llvm.org/job/clang-san-iossim/5356/console
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/lib/ProfileData/MemProfReader.cpp:34:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/MemProfReader.h:24:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/InstrProfReader.h:22:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/InstrProfCorrelator.h:21:
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:1173:36: error: implicit instantiation of undefined template 'llvm::yaml::MissingTrait<unsigned long>'
char missing_yaml_trait_for_type[sizeof(MissingTrait<T>)];
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:961:7: note: in instantiation of function template specialization 'llvm::yaml::yamlize<unsigned long>' requested here
yamlize(*this, Val, Required, Ctx);
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:883:11: note: in instantiation of function template specialization 'llvm::yaml::IO::processKey<unsigned long, llvm::yaml::EmptyContext>' requested here
this->processKey(Key, Val, true, Ctx);
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/MIBEntryDef.inc:55:1: note: in instantiation of function template specialization 'llvm::yaml::IO::mapRequired<unsigned long>' requested here
MIBEntryDef(AccessHistogram = 27, AccessHistogram, uintptr_t)
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/lib/ProfileData/MemProfReader.cpp:77:8: note: expanded from macro 'MIBEntryDef'
Io.mapRequired(KeyStr.str().c_str(), MIB.Name); \
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:310:8: note: template is declared here
struct MissingTrait;
^
1 error generated.
Commit: 17b87853c3b07b8e1c7f000c3818efab7fdd8883
https://github.com/llvm/llvm-project/commit/17b87853c3b07b8e1c7f000c3818efab7fdd8883
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
Log Message:
-----------
[lldb] Fix premature MainLoop wakeup on windows (#117756)
The windows system APIs only take milliseconds. Make sure we round the
sleep interval (in nanoseconds) upwards.
Commit: 427be0767523b6e0f4004a421892f463d62446ac
https://github.com/llvm/llvm-project/commit/427be0767523b6e0f4004a421892f463d62446ac
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mlamcas.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
A llvm/test/Transforms/AtomicExpand/LoongArch/atomicrmw-expand.ll
Log Message:
-----------
[LoongArch] Support amcas[_db].{b/h/w/d} instructions. (#114189)
Two options for clang: -mlamcas & -mno-lamcas.
Enable or disable amcas[_db].{b/h} instructions.
The default is -mno-lamcas.
Only works on LoongArch64.
Commit: eb001820b47176fc3e7bc643525c6352b76dcd1d
https://github.com/llvm/llvm-project/commit/eb001820b47176fc3e7bc643525c6352b76dcd1d
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/temp/temp.deduct.guide/p3.cpp
Log Message:
-----------
[Clang] prevent errors for deduction guides using deduced type aliases (#117450)
Fixes #54909
---
Clang incorrectly produces diagnostics for alias templates in deduction
guides, treating them as separate from their underlying types. This
issue arises because Clang doesn't properly handle
`TypeAliasTemplateDecl` when comparing template names for equality in
the context of deduction guides, resulting in diagnostics that don't
align with the C++ standard. As the C++ standard specifies - _an alias
template is considered a synonym for its underlying type_
With this change, Clang now correctly resolves alias templates to their
underlying types in deduction guides, ensuring compliance with the C++
standard.
Commit: 74392bde2e603c8ca3f0956d4c55ba181fe9989b
https://github.com/llvm/llvm-project/commit/74392bde2e603c8ca3f0956d4c55ba181fe9989b
Author: Maurice Heumann <MauriceHeumann at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Headers/intrin.h
Log Message:
-----------
[X86] Consistently use __inline__ keyword in intrin.h (#117856)
Using `inline` instead of `__inline__` may cause duplicate symbol errors in some scenarios.
This fixes #117854
Commit: 712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
https://github.com/llvm/llvm-project/commit/712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
Author: David Green <david.green at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
Log Message:
-----------
[AArch64][GlobalISel] Fix smull and umull intrinsics.
These were the wrong way around somehow, with aarch64_neon_umull being converted
to G_SMULL.
Commit: 345b3319c8544a0124aed9602c31f8793228ab63
https://github.com/llvm/llvm-project/commit/345b3319c8544a0124aed9602c31f8793228ab63
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[AMDGPU][SplitModule] Fix unintentional integer division (#117586)
A static analysis tool warned that a division was always being performed
in integer division, so was either 0.0 or 1.0.
This doesn't seem intentional, so has been fixed to return a true ratio
using floating-point division. This in turn showed a bug where a
comparison against this ratio was incorrect.
Commit: 1fccba5ca1997db13cfa88f788b7acb8cc300b48
https://github.com/llvm/llvm-project/commit/1fccba5ca1997db13cfa88f788b7acb8cc300b48
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
Log Message:
-----------
[AArch64][PAC] Eliminate excessive MOVs when computing blend (#115185)
As function calls do not generally preserve X16 and X17, it is beneficial
to allow AddrDisc operand of BLRA instruction to reside in these
registers and make use of this condition when computing the
discriminator.
This can save up to two MOVs in cases such as loading a (signed) virtual
function pointer via a (signed) pointer to vtable, for example
ldr x9, [x16]
mov x8, x16
mov x17, x8
movk x17, #34646, lsl #48
blraa x9, x17
can be simplified to
ldr x8, [x16]
movk x16, #34646, lsl #48
blraa x8, x16
Commit: c979ec05642f292737d250c6682d85ed49bc7b6e
https://github.com/llvm/llvm-project/commit/c979ec05642f292737d250c6682d85ed49bc7b6e
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Reland - [Offload] Introduce offload-tblgen and initial new API implementation (#108413) (#117704)
Relands changes from #108413 - this was reverted due to build issues.
The problem was just that the `offload-tblgen` tool was behind recent
changes to tablegen that ensure `const` records. This has been fixed and
the PR is otherwise identical.
___
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
# From the runtime build directory
$ ninja LibomptUnitTests
$ OFFLOAD_TRACE=1 ./offload/unittests/OffloadAPI/offload.unittests
```
### Open questions and future work
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: fc5c89900f2a4b50e0f3a88ef7c89115d93684f4
https://github.com/llvm/llvm-project/commit/fc5c89900f2a4b50e0f3a88ef7c89115d93684f4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
A llvm/test/Transforms/SimpleLoopUnswitch/pr117537.ll
Log Message:
-----------
[SimpleLoopUnswitch] Fix LCSSA phi node invalidation
Fixes https://github.com/llvm/llvm-project/issues/117537.
Commit: 0cb5846a68cc5c5e519b2c80ab106e7e4fc6eedb
https://github.com/llvm/llvm-project/commit/0cb5846a68cc5c5e519b2c80ab106e7e4fc6eedb
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "Reland - [Offload] Introduce offload-tblgen and initial new API implementation (#108413) (#117704)"
This reverts commit c979ec05642f292737d250c6682d85ed49bc7b6e.
This showed failures in the post-merge CI.
Commit: f6f2929fc6fa39f62e2c3109b7a1b0f866c1c17b
https://github.com/llvm/llvm-project/commit/f6f2929fc6fa39f62e2c3109b7a1b0f866c1c17b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx2.s
Log Message:
-----------
[X86] Fix HSW/BDW masked store schedules
Vector masked stores don't use Port5 or Port 7.
Confirmed by augner/uops.info
Commit: 124b1f8d85af71e512e6dc6250c8bfa370a33d48
https://github.com/llvm/llvm-project/commit/124b1f8d85af71e512e6dc6250c8bfa370a33d48
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
Log Message:
-----------
[X86] Fix HSW/BDW shift/rotate by CL schedules
This is just Port06 not Port0156 - fixes reported thoughputs
Confirmed by augner/uops.info
Commit: 37aebcf4e60e5c913e3d99675548b3e2c631398b
https://github.com/llvm/llvm-project/commit/37aebcf4e60e5c913e3d99675548b3e2c631398b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/barrier_output.s
Log Message:
-----------
[X86] Cleanup SFENCE/MFENCE schedules
Remove unnecessary overrides.
UOp + Port usage confirmed by augner/uops.info
Commit: e874c8fc27bbc0e340691d5b5d01c7a1bd365890
https://github.com/llvm/llvm-project/commit/e874c8fc27bbc0e340691d5b5d01c7a1bd365890
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
[SelectOpt] Refactor to prepare for support more select-like operations (#117582)
* Enables conversion of several select-like instructions within one
group
* Any number of auxiliary instructions depending on the same condition
can be in between select-like instructions
* After splitting the basic block, move select-like instructions into
the relevant basic blocks and optimise them
* Make it easier to add support shift-base select-like instructions and
also any mixture of zext/sext/not instructions
Commit: 7b2a708a27da1cbdf16b912aa2c98e9718256596
https://github.com/llvm/llvm-project/commit/7b2a708a27da1cbdf16b912aa2c98e9718256596
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
M llvm/unittests/AsmParser/AsmParserTest.cpp
Log Message:
-----------
AsmParser: parse zeroinitializer, poison constants (#117809)
LLParser::parseConstantValue is missing support for parsing
zeroinitializer and poison constants. Fix this.
Commit: 284d4e0a7a789848b7af7f85158ccf522d70c6f0
https://github.com/llvm/llvm-project/commit/284d4e0a7a789848b7af7f85158ccf522d70c6f0
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/unittests/debugserver/RNBSocketTest.cpp
Log Message:
-----------
[lldb] Fix RNBSocketTest for #117691
Commit: 2eb40aadda48e4470bd1bf2cba90a7d593690a6b
https://github.com/llvm/llvm-project/commit/2eb40aadda48e4470bd1bf2cba90a7d593690a6b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/Analysis/MemorySSA/loop-unswitch.ll
M llvm/test/Analysis/MemorySSA/pr40037.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr46574.ll
M llvm/test/Analysis/MemorySSA/simple_loop_unswitch_nontrivial.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-13-SingleEntryPHI.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-27-DeadSwitchCase.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-Unreachable.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-tl.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-12-ExitDomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-13-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-18-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2008-06-02-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2010-11-18-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-06-02-CritSwitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-09-26-EHCrash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-04-02-IndirectBr.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-05-20-Phi.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2015-09-18-Addrspace.ll
M llvm/test/Transforms/SimpleLoopUnswitch/LIV-loop-condtion.ll
M llvm/test/Transforms/SimpleLoopUnswitch/cleanuppad.ll
M llvm/test/Transforms/SimpleLoopUnswitch/copy-metadata.ll
M llvm/test/Transforms/SimpleLoopUnswitch/crash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-behavior.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-cost.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-skip-selects-in-guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/preserve-analyses.ll
Log Message:
-----------
[SimpleLoopUnswitch] Use loop-mssa in more tests (NFC)
We had a lot of -verify-memoryssa tests that did not actually use
MemorySSA, because they were not using the loop-mssa adaptor.
Commit: f30f7a084c93bb7ef4983cda583985b56ad123d2
https://github.com/llvm/llvm-project/commit/f30f7a084c93bb7ef4983cda583985b56ad123d2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-half-conversions.ll
Log Message:
-----------
[X86] canonicalizeShuffleWithOp - initial support for shuffle(cvt(x),cvt(y)) -> cvt(shuffle(x,y))
Initial support is just for UNPCKL(CVTPH2PS(X),CVTPH2PS(Y)) -> CVTPH2PS(UNPCKL(X,Y))
Making this more general for other shuffles/conversions will have to be done carefully as we have to handle changes in src/dst element width, so I just handled the CVTPH2PS regression case.
Fixes #83414
Commit: dddeec4becabf71d4067080bcc2c09a9e67c3025
https://github.com/llvm/llvm-project/commit/dddeec4becabf71d4067080bcc2c09a9e67c3025
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/cxx-uninitialized-object-unguarded-access.cpp
A clang/test/Analysis/void-call-exit-modelling.c
Log Message:
-----------
[analyzer] Avoid out-of-order node traversal on void return (#117863)
The motivating example: https://compiler-explorer.com/z/WjsxYfs43
```C++
#include <stdlib.h>
void inf_loop_break_callee() {
void* data = malloc(10);
while (1) {
(void)data; // line 3
break; // -> execution continues on line 3 ?!!
}
}
```
To correct the flow steps in this example (see the fixed version in the
added test case) I changed two things in the engine:
- Make `processCallExit` create a new StmtPoint only for return
statements. If the last non-jump statement is not a return statement,
e.g. `(void)data;`, it is no longer inserted in the exploded graph after
the function exit.
- Skip the purge program points. In the example above, purge
points are still inserted after the `break;` executes. Now, when the bug
reporter is looking for the next statement executed after the function
execution is finished, it will ignore the purge program points, so it
won't confusingly pick the `(void)data;` statement.
CPP-5778
Commit: 318c69de52b61d64d5ea113dc2e9f307f7fd4d51
https://github.com/llvm/llvm-project/commit/318c69de52b61d64d5ea113dc2e9f307f7fd4d51
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
Reland "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)"
The issue with slow compile-time was caused by an assert in
AArch64RegisterInfo.cpp. The assert invokes 'checkAllSuperRegsMarked'
after adding all the reserved registers. This call gets very expensive
after adding the _HI registers due to the way the function searches
in the 'Exception' list, which is expected to be a small list but isn't
(the patch added 190 _HI regs).
It was possible to rewrite the code in such a way that the _HI registers
are marked as reserved after the check. This makes the problem go away
entirely and restores compile-time to what it was before (tested for
`check-runtimes`, which previously showed a ~5x slowdown).
This reverts commits:
1434d2ab215e3ea9c5f34689d056edd3d4423a78
2704647fb7986673b89cef1def729e3b022e2607
Commit: 66126c350f45617c10274cc36828bb1ec7ddbae4
https://github.com/llvm/llvm-project/commit/66126c350f45617c10274cc36828bb1ec7ddbae4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port 318c69de52b6
Commit: a807bbea6f48b368388cd796782724e3a53f58a0
https://github.com/llvm/llvm-project/commit/a807bbea6f48b368388cd796782724e3a53f58a0
Author: Victor Perez <victor.perez at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUToLLVMSPV/CMakeLists.txt
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
Log Message:
-----------
[MLIR][GPUToLLVMSPV] Use `llvm.func` attributes to convert `gpu.shuffle` (#116967)
Use `llvm.func`'s `intel_reqd_sub_group_size` attribute instead of
SPIR-V environment attributes in the `gpu.shuffle` conversion pattern.
This metadata is needed to check the semantics of the operation are
supported, i.e., it has a constant width and its value is equal to the
sub-group size.
As the pass also converts `gpu.func` to `llvm.func`, adding a
discardable attribute of name `intel_reqd_sub_group_size` attribute to
the latter is enough for this pattern to work.
We no longer have a notion of "default" sub-group size, so this
attribute needs to be set in the parent function for `gpu.shuffle`
operations to be converted.
Drop dependency on the SPIR-V dialect as we no longer require creating
attributes from this dialect to lower `gpu.shuffle` instances.
---------
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Commit: 89b31c9c32f2cd2c038fe2b12d9c66a53c779fc1
https://github.com/llvm/llvm-project/commit/89b31c9c32f2cd2c038fe2b12d9c66a53c779fc1
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/declare-target-interface.f90
Log Message:
-----------
[Flang][OpenMP] Fix a crash for declare target in an interface (#117709)
This is a point fix for the crash in #116426. Leaving the bug open to
further explore declare target issues for interfaces.
Commit: 5eeb3fef61bf5542c3fdcb71622fc4e826527789
https://github.com/llvm/llvm-project/commit/5eeb3fef61bf5542c3fdcb71622fc4e826527789
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
R clang-tools-extra/CODE_OWNERS.TXT
A clang-tools-extra/Maintainers.txt
Log Message:
-----------
Rename CODE_OWNERS -> Maintainers (#114544)
Commit: 43ee6f7a01fca8cf08e1029c54acc23240b86fca
https://github.com/llvm/llvm-project/commit/43ee6f7a01fca8cf08e1029c54acc23240b86fca
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
Log Message:
-----------
[AlwaysInline] Avoid unnecessary BFI fetches (#117750)
AlwaysInliner doesn't use BFI itself, it only updates it. If BFI is not
already computed, it will spend time to first compute it, and then
update it. This is not necessary: If BFI is not available in the first
place, there is no need to update it.
This is mainly relevant in debug builds for IR that has a lot of
alwaysinline functions.
Commit: 8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
https://github.com/llvm/llvm-project/commit/8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
Log Message:
-----------
[OpenACC] enable 'deviceptr' for combined constructs.
This is another clause whose implementation is identical for combined
constructs as with compute constructs, so this adds tests and enables
it.
Commit: 198fb5ed4ac7d096da03ea4a0a27832d18b1350f
https://github.com/llvm/llvm-project/commit/198fb5ed4ac7d096da03ea4a0a27832d18b1350f
Author: Samira Bazuzi <bazuzi at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
Log Message:
-----------
[clang][dataflow] Add captured parameters to ReferencedDecls for lamb… (#117771)
…da call operators.
This doesn't require that they be used in the operator's body, unlike
other ReferencedDecls. This is most obviously different from captured
local variables, which can be captured but will not appear in
ReferencedDecls unless they appear in the operator's body.
This difference simplifies the collection of the captured parameters,
but probably could be eliminated if desirable.
Commit: f67ba5855278401728413431216dda5d370ac2e0
https://github.com/llvm/llvm-project/commit/f67ba5855278401728413431216dda5d370ac2e0
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
Log Message:
-----------
[Clang] replace 'bitfield' with 'bit-field' for consistency (#117881)
Fixes #117711
Commit: 38049dc8eef0dca7e82c25e4012228a9a135e255
https://github.com/llvm/llvm-project/commit/38049dc8eef0dca7e82c25e4012228a9a135e255
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
Log Message:
-----------
[libc] Handle differing wavefront sizes correctly in the AMDHSA loader (#117788)
Summary:
The AMDGPU backend can handle wavefront sizes of 32 and 64, with the
native hardware preferring one or the other. The user can override the
hardware with `-mwavefrontsize64` or `-mwavefrontsize32` which
previously wasn't handled. We need to know the wavefront size to know
how much memory to allocate and how to index the RPC buffer. There isn't
a good way to do this with ROCm so we just use the LLVM support for
offloading to check this from the image.
Commit: 32ff209b87a84890a1487b4e0bbb4a7645d31645
https://github.com/llvm/llvm-project/commit/32ff209b87a84890a1487b4e0bbb4a7645d31645
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Analysis/Consumed.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
Log Message:
-----------
[Clang] skip consumed analysis for consteval conditions in control-flow terminators (#117403)
Fixes #117385
---
These changes extend the work done in #116513. The changes add
additional handling to ensure correct behavior by skipping further
checks when a **CFG** contains a `consteval` condition, where no
_explicit expression_ is present, which is required to proceed with
consumed analyses.
Commit: e98396f4846bfcaabe2c2ee568aab4b78655f307
https://github.com/llvm/llvm-project/commit/e98396f4846bfcaabe2c2ee568aab4b78655f307
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
Reapply [memprof] Add YAML-based deserialization for MemProf profile (#117829)
This patch adds YAML-based deserialization for MemProf profile.
It's been painful to write tests for MemProf passes because we do not
have a text format for the MemProf profile. We would write a test
case in C++, run it for a binary MemProf profile, and then finally run
a test written in LLVM IR with the binary profile.
This patch paves the way toward YAML-based MemProf profile.
Specifically, it adds new class YAMLMemProfReader derived from
MemProfReader. For now, it only adds a function to parse StringRef
pointing to YAML data. Subseqeunt patches will wire it to
llvm-profdata and read from a file.
The field names are based on various printYAML functions in MemProf.h.
I'm not aiming for compatibility with the format used in printYAML,
but I don't see a point in changing the field names.
This iteration works around the unavailability of
ScalarTraits<uintptr_t> on macOS.
Commit: 611f5b8ff913c21cfd85b0f4170ab880838a4c9e
https://github.com/llvm/llvm-project/commit/611f5b8ff913c21cfd85b0f4170ab880838a4c9e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/test/Transforms/GVN/setjmp.ll
Log Message:
-----------
[GVN] Add test for #116668 (NFC)
Commit: d668304998344d40c5a0b512fd0c0cb91e8d534c
https://github.com/llvm/llvm-project/commit/d668304998344d40c5a0b512fd0c0cb91e8d534c
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
Log Message:
-----------
[lld][MachO] Support `-allowable_client` (#117155)
Closes #117113.
Follow-up to #114638.
Commit: 969b7658fe34cf7638e1385d813e765a4c61dfc7
https://github.com/llvm/llvm-project/commit/969b7658fe34cf7638e1385d813e765a4c61dfc7
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
Log Message:
-----------
[OpenACC] Enable 'wait' for combined constructs
Once again a situation where the combined and compute do the exact same
thing as far as Sema/AST/etc is concerned, so this patch adds tests and
enables it.
Commit: 24593f1814dc02c7404526674838ccfb1c61d780
https://github.com/llvm/llvm-project/commit/24593f1814dc02c7404526674838ccfb1c61d780
Author: Saleem Abdulrasool <compnerd at compnerd.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
Log Message:
-----------
[lldb] build: cleanup extraneous include paths (#117615)
Clean up some unnecessary include paths. The use of `LibXml2::LibXml2`
with `target_link_libraries` on `libLLDBHost` ensures that the header
search path is properly propagated.
Commit: 8358437bbb5b06d9aebc2940475a5a4d86c091c9
https://github.com/llvm/llvm-project/commit/8358437bbb5b06d9aebc2940475a5a4d86c091c9
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl]: Print stack-trace on crash (#117896)
Call `llvm::sys::PrintStackTraceOnErrorSignal` at the start of main to
1. Print a strack trace on crash
2. Disable the assertion failed popup in Windows Debug Builds
Other tools (for example clang-check or clang-query) already do this.
This fixes debug build bots on windows hanging (waiting for the popup to
be dismissed) and ultimately getting terminated due to timeout.
Commit: b71704436e61057a5bd6426915c368e5d76cb7de
https://github.com/llvm/llvm-project/commit/b71704436e61057a5bd6426915c368e5d76cb7de
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Simplify generated code for validateOperandClass (#117889)
Implement the register operand handling in validateOperandClass with a
table lookup instead of a potentially huge switch.
Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
Commit: 2f02b5af6ecb973d3a7faad9b0daff22646e724d
https://github.com/llvm/llvm-project/commit/2f02b5af6ecb973d3a7faad9b0daff22646e724d
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy][modernize-use-starts-ends-with] Fix operator rewriting false negative (#117837)
In C++20, `operator!=` can be rewritten by negating `operator==`. This
is the case for `std::string`, where `operator!=` is not provided hence
relying on this rewriting.
Cover this case by matching `binaryOperation` and adding one case to
`isNegativeComparison`.
Commit: 1e3e199ed9f214594e358eb0c7892cdedc703f7a
https://github.com/llvm/llvm-project/commit/1e3e199ed9f214594e358eb0c7892cdedc703f7a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[Sema] Migrate away from PointerUnion::{is,get} (NFC) (#117498)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: c29e895ad2bce8ca36debd8ef09d0540dabc99b6
https://github.com/llvm/llvm-project/commit/c29e895ad2bce8ca36debd8ef09d0540dabc99b6
Author: knickish <knickish at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
Log Message:
-----------
[M68k] Handle 16 bit MOVs to and from CCR (#114714)
Builds on @TechnoElf 's CCR MOV pr
https://github.com/llvm/llvm-project/pull/107591 and adds some tests.
Fixes https://github.com/llvm/llvm-project/issues/106210.
---------
Co-authored-by: TechnoElf <technoelf at undertheprinter.com>
Commit: 991154d0fbc951e2b999589a95dabc7deff7acd1
https://github.com/llvm/llvm-project/commit/991154d0fbc951e2b999589a95dabc7deff7acd1
Author: Krzysztof Pszeniczny <kpszeniczny at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionImport.cpp
Log Message:
-----------
[LTO] Use .at instead of .lookup to avoid copies. (NFC) (#117888)
`DenseMap::lookup` returns by value (because it default-creates the
returned value if the key isn't present in the map), which means that we
do a lot of copying here. Since we assert that something is present in
the returned value two lines below this call, it's safe to use `.at`
here instead.
Copying and then destroying dense maps here is responsible for 60% of
the time spent in LTO indexing in a large internal build.
Commit: b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
https://github.com/llvm/llvm-project/commit/b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/test/Sema/builtin-counted-by-ref.c
Log Message:
-----------
[Clang] Improve Sema diagnostic performance for __builtin_counted_by_ref (#116719)
Implement the sema checks with a placeholder. We then check for that
placeholder in all of the places we care to emit a diagnostic.
Fixes: #115520
Commit: a4751804985554815899b5dc1544e27139bacdc4
https://github.com/llvm/llvm-project/commit/a4751804985554815899b5dc1544e27139bacdc4
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
Log Message:
-----------
[PowerPC] Use setbc for values from vector compare conditions (#114858)
For P10 use the setbc instruction to get int values from vector compare
summary condition results.
Commit: 9d55e862d938c17a5e3f970326139c53b9aaf37e
https://github.com/llvm/llvm-project/commit/9d55e862d938c17a5e3f970326139c53b9aaf37e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Fix warnings on MSVC
MSVC doesn't seem to count a use in static_assert as a use.
Commit: 35a5c7129a32f7eedf2d1913447c53cee96eab13
https://github.com/llvm/llvm-project/commit/35a5c7129a32f7eedf2d1913447c53cee96eab13
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
Log Message:
-----------
[OpenACC] Add tests forgotten in 969b7658fe
Commit: bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
https://github.com/llvm/llvm-project/commit/bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
Log Message:
-----------
[OpenACC] Enable 'attach' clause for combined constructs
Once again, this clause has the same implementation for compute
constructs as combined, so this adds the tests and enables it.
Commit: 87503fa51c8d726510d48e707a7d2885a5b5936c
https://github.com/llvm/llvm-project/commit/87503fa51c8d726510d48e707a7d2885a5b5936c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
Log Message:
-----------
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
This reverts commit e9c49901a43f5b16c3df416460b7e4dbdd24ce03.
Current AMDGPURegBankSelect does nothing different then RegBankSelect.
Revert to using generic RegBankSelect in preparation for adding new
regbankselect passes. New AMDGPURegBankSelect, that will use uniformity
analysis for regbank select decisions, will not subclass RegBankSelect.
Revert regression tests to use regbankselect since amdgpu-regbankselect
will be used by new pass and behavior will be different.
Commit: 2e9469885d4572a2eedf2669190742c9e3272e6a
https://github.com/llvm/llvm-project/commit/2e9469885d4572a2eedf2669190742c9e3272e6a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 87503fa51c8d
Commit: dae9cf3816bbb2b4589d258a82e6ac90fad71485
https://github.com/llvm/llvm-project/commit/dae9cf3816bbb2b4589d258a82e6ac90fad71485
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
Log Message:
-----------
[RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC
Improves coverage for more configurations.
Commit: d7643e86100a3515660dc807c88eea79bf755016
https://github.com/llvm/llvm-project/commit/d7643e86100a3515660dc807c88eea79bf755016
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support f32/f64 llvm.exp10 intrinsics.
Commit: 1bc9de247477b58a14547a31047d1c9a365e2d5d
https://github.com/llvm/llvm-project/commit/1bc9de247477b58a14547a31047d1c9a365e2d5d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
Commit: 92a15dd7482ff4e1fae7a07f888564e5b1d53eee
https://github.com/llvm/llvm-project/commit/92a15dd7482ff4e1fae7a07f888564e5b1d53eee
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][LLVM] Plumb range attributes on parameters and results through (#117801)
We've had the ability to define LLVM's `range` attribute through
#llvm.constant_range for some time, and have used this for some GPU
intrinsics. This commit allows using `llvm.range` as a parameter or
result attribute on function declarations and definitions.
Commit: 3ce8b7d2205507c91f1609337382ad950f3be805
https://github.com/llvm/llvm-project/commit/3ce8b7d2205507c91f1609337382ad950f3be805
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove inline call stacks (#117833)
Now that MemProf format version 1 has been removed, nobody uses:
- IndexedAllocationInfo::CallStack
- IndexedMemProfRecord::CallSites
This patch removed the dead struct fields.
You might notice that IndexedMemProfRecord::{clear,merge} do not
mention CallSiteIds at all. I think it's an oversight. clear doesn't
matter at the moment because we call it during serialization to reduce
memory footprint. merge is simply not as well tested as it should be.
I'll follow up with a separate patch to address these issues.
Commit: 82b437944e53afeb25dd85507664e2a980ddfe07
https://github.com/llvm/llvm-project/commit/82b437944e53afeb25dd85507664e2a980ddfe07
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use "using" directives in unit tests (NFC) (#117852)
This tests uses existing "using" directives to shorten unit tests.
- llvm::memprof::hashCallStack -> hashCallStack
- testing::Pair -> Pair
- testing::ElementsAreArray -> ElementsAre
- testing::Contains -> UnorderedElementsAre
Commit: 06246b2952d5b061e8fd75979bac9c90ccd493a4
https://github.com/llvm/llvm-project/commit/06246b2952d5b061e8fd75979bac9c90ccd493a4
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
Log Message:
-----------
[RISCV] Add shrinkwrap test cases showing gaps in current impl
This covers multiple interactions reduced from larger workloads:
1) Rematerializing addi s0, x0, <imm> to avoid the need to spill a CSR, with
the common user being a branch. (i.e. branch on immediate idioms)
2) Rematerializing addi s0, a0, <imm> to avoid the need to spill a CSR, with
the common user being a vector load or store. (i.e. because we don't
have (reg+imm) addressing on vector.)
3) Independent of the previous, we could still shrink wrap these by locally
using a non-CSR, and deferring the move into csr into the non-shrink
wrapped path.
4) Weirdly, MachineCSE is producing a different result when an edge is
manually split. This edge split should be irrelevant to the CSE?
Commit: c60b055d463a3e9f18a494aec075f35d38d447a0
https://github.com/llvm/llvm-project/commit/c60b055d463a3e9f18a494aec075f35d38d447a0
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
Log Message:
-----------
Reapply "Respect the [[clang::unsafe_buffer_usage]] attribute for field and constructor initializers (#91991)"
It was originally reverted due to an [existing bug](https://github.com/llvm/llvm-project/issues/116286). Relanding it as the bug was fixed by https://github.com/llvm/llvm-project/pull/116433.
Commit: d681e1030ffd71412294d3fadc7ef673f822b832
https://github.com/llvm/llvm-project/commit/d681e1030ffd71412294d3fadc7ef673f822b832
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/latch
M libcxx/include/semaphore
Log Message:
-----------
[libc++] Refactor atomic_wait using lambdas (#115746)
Now that we've dropped support for older C++ dialects in the
synchronization library, we can use lambdas to clarify some of the code
used to implement atomic_wait.
Commit: 8c1bd9792be1d7d19eebce57be556d5cadeb2d15
https://github.com/llvm/llvm-project/commit/8c1bd9792be1d7d19eebce57be556d5cadeb2d15
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-clause.c
A clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
Log Message:
-----------
[OpenACC] Expose 'no_create' clause in combined constructs
Once again, not much work besides ensuring they are supposed to work the
same.
Commit: b6ab04c69c907362dc7ab65eb43a9907c9adcdc1
https://github.com/llvm/llvm-project/commit/b6ab04c69c907362dc7ab65eb43a9907c9adcdc1
Author: Clément Fournier <clem.fournier at proton.me>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Matchers.h
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Fix arith maxnumf/minnumf folder (#114595)
Fix #114594
#### Context
[IEEE754-2019](https://ieeexplore.ieee.org/document/8766229) Sec 9.6
defines 2 minimum and 2 maximum operations. They are termed
- `maximum` and `maximumNumber`
- `minimum` and `minimumNumber`
In the arith dialect they are respectively named `maximumf` and
`maxnumf`, `minimumf` and `minnumf` so I use these names.
These operations only differ in how they handle NaN values. For
`maximumf` and `minimumf`, if any operand is NaN, then the result is
NaN, ie, NaN is propagated. For `maxnumf` and `minnumf`, if any operand
is NaN, then the other operand is returned, ie, NaN is absorbed. The
following identities hold:
```
maximumf(x, NaN) = maximumf(NaN, x) = NaN
maxnumf(x, NaN) = maxnumf(NaN, x) = x
```
(and same for min).
#### Arith folders
In the following I am talking about the folders for the arith
operations. The folders implement the following canonicalizations (`op`
is one of maximumf, maxnumf, minimumf, minnumf):
1. `op(x, x)` folds to `x`
2. for `op(x, y)`, if `y` folds to the neutral element of the `op`, then
the `op` is folded to `x`.
1. The neutral element of `maximumf` is -Infty
2. The neutral element of `minimumf` is +Infty
3. The neutral element of `maxnumf` and `minnumf` is NaN as shown above.
3. for `op(x, y)`, if both `x` and `y` fold to constants `x'` and `y'`,
then the `op` is folded and the result is calculated with a
corresponding runtime function.
The folders are properly implemented for `maximumf` and `minimumf`, but
the same implementations were copied for the respective `maxnumf` and
`minnumf` functions. This means the neutral element of the second folder
above is wrong:
- `maxnumf(x, -Infty)` is folded to `x`, but that's wrong, because if
`x` is NaN then -Infty should be the result
- `minnumf(x, +Infty)` is folded to `x`, but same thing, the result
should be +Infty when `x` is NaN.
This is fixed by using `NaN` as neutral element for the `maxnumf` and
`minnumf` ops.[^1]
Again because of copy paste mistake, the third pattern above is using
`llvm::maximum` instead of `llvm::maximumnum` to calculate the result in
case both arguments fold to a constant:
- `maxnumf(NaN, x')` would have been folded to `llvm::maximum(NaN, x')`
which is `NaN`, whereas the result should be `x'`.
This folder for `minnumf` already correctly uses `llvm::minnum`, but I
fixed the one for `maxnumf` in this PR.
[^1]: this is by the way already correctly implemented in
[`arith::getIdentityValueAttr`](https://github.com/oowekyala/llvm-project/blob/a821964e0320d1e35514ced149ec10ec06d7131a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp#L2493-L2498)
Commit: 854d7301f989dd1e3c838ef4f48cb57bb7d496e0
https://github.com/llvm/llvm-project/commit/854d7301f989dd1e3c838ef4f48cb57bb7d496e0
Author: Vigneshwar Jayakumar <vigneshwarjayakumar at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
A clang/test/SemaHIP/zero-sized-device-array.hip
Log Message:
-----------
[Clang/AMDGPU] Zero sized arrays not allowed in HIP device code. (#113470)
Added diagnosis to throw error when zero sized arrays are used in the
HIP device code. SWDEV-449592
---------
Co-authored-by: vigneshwar jayakumar <vigneshwar.jayakumar at amd.com>
Commit: 175051b05edcd10d997d8f98f142af1ff191b93a
https://github.com/llvm/llvm-project/commit/175051b05edcd10d997d8f98f142af1ff191b93a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support libcalls for f32/f64 acos/asin/atan/atan2/cosh/sinh/tanh.
Commit: 89d8e70031189eacb915beae2ffc642c0de1ec1a
https://github.com/llvm/llvm-project/commit/89d8e70031189eacb915beae2ffc642c0de1ec1a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/src/__support/RPC/rpc_client.cpp
M libc/src/__support/RPC/rpc_client.h
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Export a pointer to the RPC client directly (#117913)
Summary:
We currently have an unnecessary level of indirection when initializing
the RPC client. This is a holdover from when the RPC client was not
trivially copyable and simply makes it more complicated. Here we use the
`asm` syntax to give the C++ variable a valid name so that we can just
copy to it directly.
Another advantage to this, is that if users want to piggy-back on the
same RPC interface they need only declare theirs as extern with the same
symbol name, or make it weak to optionally use it if LIBC isn't
avaialb.e
Commit: 1d810ece2b2c8fab77720493864257f0ea3336a9
https://github.com/llvm/llvm-project/commit/1d810ece2b2c8fab77720493864257f0ea3336a9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/shared/rpc_opcodes.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
R libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Move libc server handlers to a shared header (#117908)
Summary:
We can simply include this header from the shared directory now and do
not need to have this level of indirection. Simply stash it with the
other libc opcode handlers.
If we were able to move the printf handlers to the shared directory then
this could just be a header as well, which would HEAVILY simplify the
mess associated with building the RPC server first in the projects
build, then copying it to the runtimes build.
Commit: 1669ac434cd4aa0ad47d42401c6d4e2afd826d30
https://github.com/llvm/llvm-project/commit/1669ac434cd4aa0ad47d42401c6d4e2afd826d30
Author: lialan <me at alanli.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
Log Message:
-----------
[MLIR] Refactor mask compression logic when emulating `vector.maskedload` ops (#116520)
This patch simplifies and extends the logic used when compressing masks
emitted by `vector.constant_mask` to support extracting 1-D vectors from
multi-dimensional vector loads. It streamlines mask computation, making
it applicable for multi-dimensional mask generation, improving the
overall handling of masked load operations.
Commit: febbf9105f7101d7124e802e87d8303237b64a80
https://github.com/llvm/llvm-project/commit/febbf9105f7101d7124e802e87d8303237b64a80
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Match vcompress during shuffle lowering (#117748)
This change matches a subset of vcompress patterns during shuffle
lowering. The subset implemented requires a contiguous prefix of
demanded elements followed by undefs. This subset was chosen for two
reasons: 1) which elements to spurious demand is a non-obvious problem,
and 2) my first several attempts at implementing the general case were
buggy. I decided to go with the simple case to start with.
vcompress scales better with LMUL than a general vrgather, and at least
the SpaceMit X60, has higher throughput even at m1. It also has the
advantage of requiring smaller vector constants at one bit per element
as opposed to vrgather which is a minimum of 8 bits per element. The
downside to using vcompress is that we can't fold a vselect into it, as
there is no masked vcompress variant.
For reference, here are the relevant throughputs from camel-cdr's data
table on BP3 (X60):
vrgather.vv v8,v16,v24 4.0 16.0 64.0 256.0
vcompress.vm v8,v16,v24 3.0 10.0 36.0 136.
vmerge.vvm v8,v16,v24,v0 2.0 4.0 8.0 16.0
The largest concern with the extra vmerge is that we locally increase
register pressure. If we do have masking, we also have a passthru,
without the ability to fold that into the vcompress, we need to keep it
alive a bit longer. This can hurt at e.g. m8 where we have very few
architectural registers. As compared with the vrgather.vv sequence, this
is only one additional m1 VREG - since we no longer need the index
vector. It compares slightly worse against vrgatherie16.vv which can use
index vectors smaller than other operands. Note that we could
potentially fold the vmerge if only tail elements are being preserved; I
haven't investigated this.
It is unfortunately hard given our current lowering structure to know if
we're emitting a shuffle where masking will follow. Thankfully, it
doesn't seem to show up much in practice, so I think we can probably
ignore it.
This patch only handles single source compress idioms at the moment.
This is an effort to avoid interacting with other patches on review for
changing how we canonicalize length changing shuffles.
Commit: e3fdc3aa81c7e8196d804fbde1a3f76796dbd5dd
https://github.com/llvm/llvm-project/commit/e3fdc3aa81c7e8196d804fbde1a3f76796dbd5dd
Author: Felipe Magno de Almeida <felipe.m.almeida at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
Log Message:
-----------
[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044)
Change the intersect for the anticipated algorithm to ignore unknown
when anticipating. This effectively allows VXRM writes speculatively
because it could do a VXRM write even when there's branches where VXRM
is unneeded.
The importance of this change is because VXRM writes causes pipeline
flushes in some micro-architectures and so it makes sense to allow more
aggressive hoisting even if it causes some degradation for the slow
path.
An example is this code:
```
typedef unsigned char uint8_t;
__attribute__ ((noipa))
void foo (uint8_t *dst, int i_dst_stride,
uint8_t *src1, int i_src1_stride,
uint8_t *src2, int i_src2_stride,
int i_width, int i_height )
{
for( int y = 0; y < i_height; y++ )
{
for( int x = 0; x < i_width; x++ )
dst[x] = ( src1[x] + src2[x] + 1 ) >> 1;
dst += i_dst_stride;
src1 += i_src1_stride;
src2 += i_src2_stride;
}
}
```
With this patch, the code above generates a hoisting VXRM writes out of
the outer loop.
Commit: c6f2d35c4d698deff781366cea46e273ff508693
https://github.com/llvm/llvm-project/commit/c6f2d35c4d698deff781366cea46e273ff508693
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
Fix a build warning introduce by my febbf910
Commit: 4cb4516ae9ae2f267ec755ed0ec6b671fe6747b8
https://github.com/llvm/llvm-project/commit/4cb4516ae9ae2f267ec755ed0ec6b671fe6747b8
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
Log Message:
-----------
[OpenMP] Fix RPC client not being optimized out after changes
Summary:
I forgot that this check deliberately looked through the indirection I
removed. Fix it to just check if the symbol has no users.
Commit: 80afdbe6a55a10cb246cb748149f0d41e778d01b
https://github.com/llvm/llvm-project/commit/80afdbe6a55a10cb246cb748149f0d41e778d01b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Use RISCVSubtarget::is64Bit() instead of hasFeature(RISCV::Feature64Bit). NFC
Commit: 8df63211a65693c7cc760e361adf20edd450fafa
https://github.com/llvm/llvm-project/commit/8df63211a65693c7cc760e361adf20edd450fafa
Author: Pranav Kant <prka at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Bitstream/Reader/BitstreamReader.cpp
Log Message:
-----------
[BitstreamReader] Fix 32-bit overflow (#117363)
This got exposed when processing large LTO-generated files leading to
crashes.
Commit: 21af99ab84e434819b20452367325b187492d372
https://github.com/llvm/llvm-project/commit/21af99ab84e434819b20452367325b187492d372
Author: Maurice Heumann <MauriceHeumann at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86WinEHState.cpp
A llvm/test/CodeGen/WinEH/wineh-scope-statenumbering.ll
Log Message:
-----------
[WinEH] Emit state stores for SEH scopes (#116546)
At the moment Windows 32 bit SEH state stores are only emitted for
throwing calls.
Windows 32 bit SEH state stores should also be emitted before SEH scope
begin and before SEH scope end.
An invalid inline memory access would otherwise not trigger unwinding,
in combination with /EHa.
This fixes #90946
Commit: e573c6b67eb729a625431121139100bebc61ba1f
https://github.com/llvm/llvm-project/commit/e573c6b67eb729a625431121139100bebc61ba1f
Author: Yusuke MINATO <minato.yusuke at fujitsu.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/HLFIR/goto-do-body.f90
M flang/test/Lower/goto-do-body.f90
M flang/test/Lower/nsw.f90
Log Message:
-----------
[flang] Add nsw to DO loop parameters (#113854)
nsw is added to DO loop parameters (initial parameters, terminal
parameters, and incrementation parameters).
This can help vectorization in some cases like #110609.
See also the discussion in
https://discourse.llvm.org/t/rfc-add-nsw-flags-to-arithmetic-integer-operations-using-the-option-fno-wrapv/77584/20.
Commit: 9bdf683ba6cd9ad07667513d264a2bc02d969186
https://github.com/llvm/llvm-project/commit/9bdf683ba6cd9ad07667513d264a2bc02d969186
Author: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/extract-vselect-setcc.ll
Log Message:
-----------
[X86] Enforce strict pre-legalization to combine in scalarizeExtEltFP (#117681)
Use a `DCI` object to actually check the DAG combine level instead of
using the type `i1` because this assumption fails on AVX512 where we
have types like `v8i1` after legalization.
Closes #117684
Commit: 65339e4d74923711c1bf6babfd59fd46f74647ba
https://github.com/llvm/llvm-project/commit/65339e4d74923711c1bf6babfd59fd46f74647ba
Author: Stella Laurenzo <stellaraccident at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
Log Message:
-----------
[mlir] Add option to disable MLIR Python dev package configuration. (#117934)
Adds a CMake option MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES which
gates doing package discovery and configuration for Python dev packages
by MLIR (this was made opt-out to preserve compatibility with
find_package(MLIR) based uses which do not set the standard options).
The default Python setup that MLIR does has been a problem for
super-projects that include LLVM for a long time because it forces a
very specific package discovery mechanism that is not uniform in all
uses.
When reviewing #117922, I noted that this would effectively be a break
the world event for downstreams, forcing them to adapt their nanobind
dep to the exact way that MLIR does it. Adding the option to just
wholesale skip the built-in configuration heuristics at least gives us a
mechanism to tell downstreams to migrate to, giving them complete
control and not requiring packaging workarounds. This seemed a better
option than (once again) creating a situation where downstreams could
not integrate the dep change without doing tricky infra upgrades, and it
removes the burden from the author of that patch from needing to think
about how this affects super-projects that include MLIR (i.e. they can
just be told to do it themselves as needed vs being in a wedged state
and unable to upgrade).
Commit: d2b482b0efd1d523852c9add8ed6b2035ce1acd9
https://github.com/llvm/llvm-project/commit/d2b482b0efd1d523852c9add8ed6b2035ce1acd9
Author: Omar Hossam <moar.ahmed at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] (reland #117503) Implement process_mrelease (#117851)
This PR implements process_mrelease.
A previous PR was merged #117503, but failed on merge due to an issue in
the tests. Namely the failing tests were comparing against return type
as opposed to errno. This is fixed in this PR.
Commit: 63c5a422f07da9925a4700f54016ab8623567718
https://github.com/llvm/llvm-project/commit/63c5a422f07da9925a4700f54016ab8623567718
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/DeclCXX.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/SemaCXX/literal-type.cpp
Log Message:
-----------
[Clang] Fix constexpr-ness on implicitly deleted destructors (#116359)
In C++20, a defaulted but implicitly deleted destructor is constexpr if
and only if the class has no virtual base class. This hasn't been
changed in C++23 by P2448R2.
Constexpr-ness on a deleted destructor affects almost nothing. The
`__is_literal` intrinsic is related, while the corresponding
`std::is_literal_type(_v)` utility has been removed in C++20. A recently
added example in `test/AST/ByteCode/cxx23.cpp` will become valid, and
the example is already accepted by GCC.
Clang currently behaves correctly in C++23 mode, because the
constexpr-ness on defaulted destructor is relaxed by P2448R2. But we
should make similar relaxation for an implicitly deleted destructor.
Fixes #85550.
Commit: c8cd497c9889b051671c7fe2eb6e4b3bbe6606f9
https://github.com/llvm/llvm-project/commit/c8cd497c9889b051671c7fe2eb6e4b3bbe6606f9
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/UsersManual.rst
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[Driver] Support fprofile-sample-use= for CL (#117282)
Sampling PGO has already been supported on Windows. This patch adds
/fprofile-sample-use= /fprofile-sample-use: /fno-profile-sample-use and
supports -fprofile-sample-use= for CL.
Commit: 819b155c2a18460d2f22482975d33d77bb4f8831
https://github.com/llvm/llvm-project/commit/819b155c2a18460d2f22482975d33d77bb4f8831
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/src/sys/mman/linux/process_mrelease.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] skip test and return ENOSYS when processm_release unavailable (#117951)
Commit: 4a3f46de5022418452947bb630cdb5b9658e82ea
https://github.com/llvm/llvm-project/commit/4a3f46de5022418452947bb630cdb5b9658e82ea
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
Log Message:
-----------
[LV][EVL] Support call instruction with EVL-vectorization (#110412)
Commit: a24aa7dfa579c41365f23f8205b619b838e32184
https://github.com/llvm/llvm-project/commit/a24aa7dfa579c41365f23f8205b619b838e32184
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/plugins-nextgen/common/CMakeLists.txt
M runtimes/cmake/Modules/FindLibcCommonUtils.cmake
Log Message:
-----------
[Offload] Use libc 'hand-in-hand' module to find RPC header (#117928)
Summary:
We should now use the official™ way to include the files from
`libc/shared`. This required some code to make sure that it's not
included twice if multiple people use it as well as a sanity check on
the directory.
Commit: 054f914741421ca9dd1eaa58ea74a20f8695bae6
https://github.com/llvm/llvm-project/commit/054f914741421ca9dd1eaa58ea74a20f8695bae6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/utils/merge-json.py
M runtimes/CMakeLists.txt
Log Message:
-----------
[Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)
Summary:
When building a project in a runtime mode, the compilation database is a
separate CMake invocation. So its `compile_commands.json` file will be
placed elsewhere in the `runtimes/runtime-bins` directory. This is
somewhat annoying for ongoing development when a runtimes build is
necessary. This patch adds some CMake magic to merge the two files.
Commit: 700d9ac9ef82fa5aa6b2972e8656ab5055a90d15
https://github.com/llvm/llvm-project/commit/700d9ac9ef82fa5aa6b2972e8656ab5055a90d15
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
Log Message:
-----------
[libc] disable process_mrelease for riscv (#117956)
`process_mrelease` upsets the RV32 build bot. Disable it for now.
Commit: 1f422dc399e2b62d0c8fc64849af915d89c28d67
https://github.com/llvm/llvm-project/commit/1f422dc399e2b62d0c8fc64849af915d89c28d67
Author: sfzhu93 <42506672+sfzhu93 at users.noreply.github.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
Log Message:
-----------
[MLIR][mlir-opt] add support for disabling diagnostics (#117669)
This PR adds a command line argument `--mlir-disable-diagnostic` for
disabling diagnostic information for mlir-opt.
When debugging with mlir-opt, some developers would like to disable the
diagnostic information and focus specifically on the dumped IR. For
example, https://github.com/triton-lang/triton/pull/5250
Commit: db273c6c242f51792ed4298a24bd2c344214ce38
https://github.com/llvm/llvm-project/commit/db273c6c242f51792ed4298a24bd2c344214ce38
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/tools/mlir-tblgen/EnumsGen.cpp
Log Message:
-----------
[MLIR][ODS] Add support for wrapping enums with std::optional in Type/Attr definitions (#117719)
Commit: c8b15157d70c57489b9aba939065c01c3f697ddb
https://github.com/llvm/llvm-project/commit/c8b15157d70c57489b9aba939065c01c3f697ddb
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
Log Message:
-----------
[mlir-opt] Fix -Wcovered-switch-default in MlirOptMain.cpp (NFC)
/llvm-project/mlir/lib/Tools/mlir-opt/MlirOptMain.cpp:262:7:
error: default label in switch which covers all enumeration values [-Werror,-Wcovered-switch-default]
default:
^
1 error generated.
Commit: 3a115279f888b6489902df60c3fe2e76447d375c
https://github.com/llvm/llvm-project/commit/3a115279f888b6489902df60c3fe2e76447d375c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/docs/DialectConversion.md
M mlir/include/mlir/Transforms/DialectConversion.h
Log Message:
-----------
[mlir][Transforms][NFC] Dialect conversion: Improve docs for materializations (#117847)
The terms "legal type" and "illegal type" are ambiguous when talking
about materializations. E.g., for target materializations we do not
necessarily convert from illegal to legal types. We convert from the
most recently mapped value to the type that was produced by converting
the original type.
---------
Co-authored-by: Markus Böck <markus.boeck02 at gmail.com>
Commit: 81f544d4659a96772c7e2ffed1bbe557993f4b34
https://github.com/llvm/llvm-project/commit/81f544d4659a96772c7e2ffed1bbe557993f4b34
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A flang/include/flang/Common/OpenMP-utils.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/lib/Common/CMakeLists.txt
A flang/lib/Common/OpenMP-utils.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
A flang/test/Lower/OpenMP/generic-loop-rewriting.f90
A flang/test/Transforms/generic-loop-rewriting-todo.mlir
A flang/test/Transforms/generic-loop-rewriting.mlir
Log Message:
-----------
[flang][OpenMP] Rewrite `omp.loop` to semantically equivalent ops (#115443)
Introduces a new conversion pass that rewrites `omp.loop` ops to their
semantically equivalent op nests bases on the surrounding/binding
context of the `loop` op. Not all forms of `omp.loop` are supported yet.
See `isLoopConversionSupported` for more info on which forms are
supported.
Commit: 2918a47f421b3d41eb54dbd8751c6e8df2adbe23
https://github.com/llvm/llvm-project/commit/2918a47f421b3d41eb54dbd8751c6e8df2adbe23
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[mlir][OpenMP] Annotate `private` vars with `map_idx` when needed (#116770)
This PR extends the MLIR representation for `omp.target` ops by adding a
`map_idx` to `private` vars. This annotation stores the index of the map
info operand corresponding to the private var. If the variable does not
have a map operand, the `map_idx` attribute is either not present at all
or its value is `-1`.
This makes matching the private variable to its map info op easier (see
https://github.com/llvm/llvm-project/pull/116576 for usage).
Commit: f710b042336d93fd1080124d3ec889702b77a730
https://github.com/llvm/llvm-project/commit/f710b042336d93fd1080124d3ec889702b77a730
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Core.cpp
Log Message:
-----------
[ORC] Fail early in ExecutionSession::registerJITDispatchHandlers.
Check that we're not reusing any handler tag addresses before installing any
handlers. This ensures that either all of the handlers are installed*, or none
of them are, simplifying error recovery.
* Ignoring handlers whose tags couldn't be resolved at all: these were never
installed.
Commit: fb3765959f2fcb97fbb2a247b619150926f0e0b6
https://github.com/llvm/llvm-project/commit/fb3765959f2fcb97fbb2a247b619150926f0e0b6
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
A llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
Log Message:
-----------
[llvm-debuginfo-analyzer] Common handling of unsigned attribute values. (#116027)
- In the DWARF reader, for those attributes that can have an unsigned
value, allow for the following cases:
* Is an implicit constant
* Is an optional value
- The testing is done by creating a file with generated DWARF, using
`DwarfGenerator` (generate DWARF debug info for unit tests).
Commit: 1c7695846559c2b191463aec46beb26c4a5c2bae
https://github.com/llvm/llvm-project/commit/1c7695846559c2b191463aec46beb26c4a5c2bae
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
Log Message:
-----------
[NVPTX] Add unreachable for TMA Inst Printer (#117850)
This patch adds the llvm_reachable() for TMA
reduction opcode printer method, outside the
switch.
We had this inside the default-case leading to
the warning below (and hence was removed):
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: f3cf24fcc46ab1b9612d7dcb55ec5f18ea2dc62f
https://github.com/llvm/llvm-project/commit/f3cf24fcc46ab1b9612d7dcb55ec5f18ea2dc62f
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/arrayset.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/box-offset-codegen.fir
M flang/test/Fir/box.fir
M flang/test/Fir/boxproc.fir
M flang/test/Fir/commute.fir
M flang/test/Fir/coordinateof.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/field-index.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
M flang/test/Fir/struct-passing-x86-64-byval.fir
M flang/test/Fir/target-rewrite-complex-10-x86.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Transforms/constant-argument-globalisation.fir
A flang/test/Transforms/function-attrs.fir
Log Message:
-----------
[flang] Apply nocapture attribute to dummy arguments (#116182)
Apply llvm.nocapture attribute to dummy arguments that do not have the
target, asynchronous, volatile, or pointer attributes in a procedure
that is not a bind(c). This was discussed in
https://discourse.llvm.org/t/applying-the-nocapture-attribute-to-reference-passed-arguments-in-fortran-subroutines/81401
Commit: d36a4c07156de01b05ea41d5876c671de64e99c6
https://github.com/llvm/llvm-project/commit/d36a4c07156de01b05ea41d5876c671de64e99c6
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll
Log Message:
-----------
[RISCV] Rename some Feature* to Tune* (#117966)
These features should be tune features.
Commit: 9ea5be639d31560faec993b4aebb3e10c7d4c8e2
https://github.com/llvm/llvm-project/commit/9ea5be639d31560faec993b4aebb3e10c7d4c8e2
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
Log Message:
-----------
Recommit "[LV][VPlan] Remove any-of reduction from precomputeCost. NFC (#117109)" (#117289)
Update the test cases contains `any-of` printings from the
precomputeCost().
Origin message:
The any-of reduction contains phi and select instructions.
The select instruction might be optimized and removed in the vplan which
may cause VF difference between legacy and VPlan-based model. But if the
select instruction be removed, planContainsAdditionalSimplifications()
will catch it and disable the assertion.
Therefore, we can just remove the ayn-of reduction calculation in the
precomputeCost().
Recommit "[LV][VPlan] Remove any-of reduction from precomputeCost. NFC
(#117109)"
Commit: c4645ffedacad18e4cd1dd372288aa55178b1c44
https://github.com/llvm/llvm-project/commit/c4645ffedacad18e4cd1dd372288aa55178b1c44
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcicsr-invalid.s
A llvm/test/MC/RISCV/xqcicsr-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: 93f7398bdba9d1547df21156db4d5393f0ab5ec8
https://github.com/llvm/llvm-project/commit/93f7398bdba9d1547df21156db4d5393f0ab5ec8
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
Log Message:
-----------
[RISCV] Add TuneDisableLatencySchedHeuristic
This tune feature will disable latency scheduling heuristic.
This can reduce the number of spills/reloads but will cause some
regressions on some cores.
CPU may add this tune feature if they find it's profitable.
Reviewers: lukel97, michaelmaitland, asb, preames, mshockwave, topperc
Reviewed By: michaelmaitland, mshockwave, topperc
Pull Request: https://github.com/llvm/llvm-project/pull/115858
Commit: c1dff7152592f1beee9059ee8e2cb3cc68baea4d
https://github.com/llvm/llvm-project/commit/c1dff7152592f1beee9059ee8e2cb3cc68baea4d
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Host/common/UDPSocket.h
M lldb/include/lldb/Host/linux/AbstractSocket.h
M lldb/include/lldb/Host/posix/DomainSocket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/common/UDPSocket.cpp
M lldb/source/Host/linux/AbstractSocket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/DomainSocket.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/debugserver/RNBSocketTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
Log Message:
-----------
[lldb] Remove child_process_inherit from the socket classes (#117699)
It's never set to true. Also, using inheritable FDs in a multithreaded
process pretty much guarantees descriptor leaks. It's better to
explicitly pass a specific FD to a specific subprocess, which we already
mostly can do using the ProcessLaunchInfo FileActions.
Commit: f6694534ac86cb6949b241c11ddc7fd8ee44f027
https://github.com/llvm/llvm-project/commit/f6694534ac86cb6949b241c11ddc7fd8ee44f027
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
Log Message:
-----------
[Driver] Remove non MSVC CL flags /fprofile-sample-use (#117970)
Those flags are introduced in #117282. They are not supported by MSVC.
Commit: 69d66fafec968b17f84e30bc09faffb3dc8e5f15
https://github.com/llvm/llvm-project/commit/69d66fafec968b17f84e30bc09faffb3dc8e5f15
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Fix description for fprofile-sample-use= on Windows (#117973)
We only support -fprofile-sample-use= for clang-cl.
Commit: 3ffee0086c1e31094e544c878f9d5cc413d36b46
https://github.com/llvm/llvm-project/commit/3ffee0086c1e31094e544c878f9d5cc413d36b46
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
M llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
Log Message:
-----------
[llvm-debuginfo-analyzer] Fix compile/link errors on specific builders. (#117971)
Link errors on builders:
- llvm-nvptx-nvidia-ubuntu
- llvm-nvptx64-nvidia-ubuntu
Add explicitly references to DebugInfoDWARF and Object.
Compile errors on builders:
- ppc64le-lld-multistage-test
- clang-ppc64le-linux-multistage
- clang-ppc64le-rhel
error: comparison of integers of different signs:
Add to the constants used in the 'EXPECT_EQ' the 'u' postfix.
Commit: 60db321081be2324bec7e18eb76421cc566625fd
https://github.com/llvm/llvm-project/commit/60db321081be2324bec7e18eb76421cc566625fd
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-frame-tail.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
Log Message:
-----------
[AArch64] Do not mark homogeneous prolog/epilog functions optnone (#117959)
The verifier complains that synthesized IR functions have minsize and
optnone attributes which are incompatible. This patch removes optnone
attribute and updates affected tests as needed.
Commit: 7173a7d7f9d3035e39508746efa46c2ec5c80119
https://github.com/llvm/llvm-project/commit/7173a7d7f9d3035e39508746efa46c2ec5c80119
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NVPTX][NFC] Use NAME macro for TMA intrinsic defs (#117907)
This patch updates the TMA intrinsic definitions to use the "NAME"
macro (inside the multiclass) instead of an empty string.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 332719561000dcac94384234ace1fa959362ad8e
https://github.com/llvm/llvm-project/commit/332719561000dcac94384234ace1fa959362ad8e
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
Log Message:
-----------
[mlir][LLVM][NFC] Implement `print/parse` for `LLVMStructType` (#117930)
The printing and parsing logic for struct types was still using ad-hoc
functions instead of the more conventional `print` and `parse` methods
whose declarations are automatically generated by TableGen.
This PR effectively renames these functions and uses them directly as
implementations for `print` and `parse` of `LLVMStructType`.
This additionally fixes linking errors when users or auto generated code
may call `print` and `parse` directly.
Fixes https://github.com/llvm/llvm-project/issues/117927
Commit: 76e6c8d3fc3dc097a3bd96e8959f73a809493976
https://github.com/llvm/llvm-project/commit/76e6c8d3fc3dc097a3bd96e8959f73a809493976
Author: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
A clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
Log Message:
-----------
Codegen changes for strict modifier with grainsize/num_tasks of taskloop construct (#117196)
Initial parsing/sema for 'strict' modifier with 'num_tasks' and
‘grainsize’ clause is present in these commits
[grainsize_parsing](https://github.com/llvm/llvm-project/commit/ab9eac762c35068e77f57795e660d06f578c9614)
and
[num_tasks_parsing](https://github.com/llvm/llvm-project/commit/56c166017055595a9f26933e85bfd89e30c528d0#diff-4184486638e85284c3a2c961a81e7752231022daf97e411007c13a6732b50db9R6545)
. However, this implementation appears incomplete as it lacks code
generation support. A runtime patch was introduced in this runtime
commit
[runtime_patch](https://github.com/llvm/llvm-project/commit/540007b42701b5ac9adba076824bfd648a265413#diff-5e95f9319910d6965d09c301359dbe6b23f3eef5ce4d262ef2c2d2137875b5c4R374)
, which adds a new API, _kmpc_taskloop_5, to accommodate the strict
modifier.
In this patch I have added codegen support. When the strict modifier is
present alongside the grainsize or num_tasks clauses of taskloop
construct, the code now emits a call to _kmpc_taskloop_5, which includes
an additional parameter of type i32 with the value 1 to indicate the
strict modifier. If the strict modifier is not present, it falls back to
the existing _kmpc_taskloop API call.
---------
Co-authored-by: Chandra Ghale <ghale at pe31.hpc.amslabs.hpecorp.net>
Commit: 89b08c8ee7b5184f8cfb0d356f2762173fb87d42
https://github.com/llvm/llvm-project/commit/89b08c8ee7b5184f8cfb0d356f2762173fb87d42
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Simplify generated code for isSubclass (#117351)
Implement isSubclass with direct lookup into some tables instead of
nested switches.
Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
Commit: 71648a4ef93867ce47afa512f6cf808be3cd0a2e
https://github.com/llvm/llvm-project/commit/71648a4ef93867ce47afa512f6cf808be3cd0a2e
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
Log Message:
-----------
Make MCDCRecord::getNumConditions() `const&`
Some users were trying to get a reference to the return value.
Commit: 0604d13790b20f6b385507bb63c62aa87162da9b
https://github.com/llvm/llvm-project/commit/0604d13790b20f6b385507bb63c62aa87162da9b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/SemaCXX/attr-no-specializations.cpp
Log Message:
-----------
[Clang] Add [[clang::no_specializations]] (#101469)
This can be used to inform users when a template should not be
specialized. For example, this is the case for the standard type traits
(except for `common_type` and `common_reference`, which have more
complicated rules).
Commit: f8f238d38eaa0a2e27f09fb6d01bcc8e7eab9e93
https://github.com/llvm/llvm-project/commit/f8f238d38eaa0a2e27f09fb6d01bcc8e7eab9e93
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[AArch64] Add extra add/cast tests for select-optimize.
Extra tests for https://github.com/llvm/llvm-project/pull/115489
with different operand order. Also fixes the target triple.
Commit: 2c242b98c608021e6768f0369498f5b8b5144d34
https://github.com/llvm/llvm-project/commit/2c242b98c608021e6768f0369498f5b8b5144d34
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
Log Message:
-----------
[clang] Add a lifetime_capture_by testcase for temporary capturing object. (#117733)
Add a test case to indicate this is an expected behavior.
Commit: 88c2af80fac423fc338027c007e1499333f05ddb
https://github.com/llvm/llvm-project/commit/88c2af80fac423fc338027c007e1499333f05ddb
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[NFC][clang][FMV][TargetInfo] Refactor API for FMV feature priority. (#116257)
Currently we have code with target hooks in CodeGenModule shared between
X86 and AArch64 for sorting MultiVersionResolverOptions. Those are used
when generating IFunc resolvers for FMV. The RISCV target has different
criteria for sorting, therefore it repeats sorting after calling
CodeGenFunction::EmitMultiVersionResolver.
I am moving the FMV priority logic in TargetInfo, so that it can be
implemented by the TargetParser which then makes it possible to query it
from llvm. Here is an example why this is handy:
https://github.com/llvm/llvm-project/pull/87939
Commit: 3b8426d340ab730ee3303257ea204ee083b1273a
https://github.com/llvm/llvm-project/commit/3b8426d340ab730ee3303257ea204ee083b1273a
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M .ci/generate_test_report.py
Log Message:
-----------
[ci] Fix unit tests for test report generator
Last time I fixed a bug here I forgot to update them.
Commit: 0c0f765cab4b16eb0342d514584cdf64cabc433a
https://github.com/llvm/llvm-project/commit/0c0f765cab4b16eb0342d514584cdf64cabc433a
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/test/CodeGen/Thumb/frame-chain.ll
A llvm/test/CodeGen/Thumb/returnaddress.ll
Log Message:
-----------
[ARM] Fix llvm.returnaddress for Thumb1 with R11 frame-pointer (#117735)
When the llvm.returnaddress intrinsic is used, the LR is marked as
live-in to the function, so it must be preserved through the prologue.
This is normally fine, but there is one case for Thumb1 where we use LR
as a temporary in the prologue to set up a frame chain using r11 as the
frame pointer. There are no other registers guaranteed to be free to do
this, so we have to re-load LR from the stack after pushing the callee
saved registers.
Commit: 79eb406a67fe08458548289da72cda18248a9313
https://github.com/llvm/llvm-project/commit/79eb406a67fe08458548289da72cda18248a9313
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A mlir/include/mlir/Conversion/MeshToMPI/MeshToMPI.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
A mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
Log Message:
-----------
[mlir][mesh, MPI] Mesh2mpi (#104566)
Pass for lowering `Mesh` to `MPI`.
Initial commit lowers `UpdateHaloOp` only.
Commit: 04a2d50efd668b752718f90811a7c628bfa761d7
https://github.com/llvm/llvm-project/commit/04a2d50efd668b752718f90811a7c628bfa761d7
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
A llvm/test/CodeGen/PowerPC/frameindex-negative-offset.ll
Log Message:
-----------
[PPC] Use getSignedConstant() for frame index offset
The offset is signed. Fixes assertion failure reported at:
https://github.com/llvm/llvm-project/pull/117558#issuecomment-2504413074
Commit: 61653f8e39666ea974561fd9ddccd7d473852fad
https://github.com/llvm/llvm-project/commit/61653f8e39666ea974561fd9ddccd7d473852fad
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/test/CodeGen/AArch64/init-undef.mir
Log Message:
-----------
Reland "[InitUndef] handleSubReg should skip artificial subregs. (#116248)"
This patch can now reland after 318c69de52b6 relanded #114827.
This reverts commit 1683f84d289348ba6879635c4161979204f75230.
Commit: 243c9791872a694ca341cc51c18d96fbc189a06b
https://github.com/llvm/llvm-project/commit/243c9791872a694ca341cc51c18d96fbc189a06b
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
Log Message:
-----------
Reland "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)"
This patch can now reland after 318c69de52b6 relanded #114827.
This reverts commit 14a58a1390a72ba6c66606e58e86425dcb902763.
Commit: 0f131704386db648e6b9388172bb93824823e277
https://github.com/llvm/llvm-project/commit/0f131704386db648e6b9388172bb93824823e277
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
Log Message:
-----------
[SPIR-V] Implement intrinsics llvm.scmp.* and llvm.ucmp.* (#117341)
This PR add translation of intrinsics `llvm.scmp.*` and `llvm.ucmp.*`.
Commit: 831469fb552ba03d15fb717eeb526a71bfac8b6d
https://github.com/llvm/llvm-project/commit/831469fb552ba03d15fb717eeb526a71bfac8b6d
Author: Marc Auberer <marc.auberer at chillibits.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M .github/new-issues-labeler.yml
Log Message:
-----------
Automatically add false-positive/false-negative labels (#117811)
Fixes #117762
Commit: 82821254f532c1dbdfd5d985ef7130511efaaa83
https://github.com/llvm/llvm-project/commit/82821254f532c1dbdfd5d985ef7130511efaaa83
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-alloca-in-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)
If IVUpdateMayOverflow is false, we proved that the induction increment
cannot overflow in the vector loop. This allows setting NUW in some
cases when folding the tail.
PR: https://github.com/llvm/llvm-project/pull/111758
Commit: 871e3dc8d8717bbcf5e3ad44331a21c3417c2639
https://github.com/llvm/llvm-project/commit/871e3dc8d8717bbcf5e3ad44331a21c3417c2639
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/tools/lldb-server/lldb-gdbserver.cpp
Log Message:
-----------
[lldb] Fixup #117699 for windows builds
Commit: 992b00020fae2d8b0f150a45885768551a867a10
https://github.com/llvm/llvm-project/commit/992b00020fae2d8b0f150a45885768551a867a10
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Reland #2 - [Offload] Introduce offload-tblgen and initial new API implementation (#108413. #117704) (#117894)
Relands #117704, which relanded changes from #108413 - this was reverted
due to build issues. The new offload library did not build with
`LIBOMPTARGET_OMPT_SUPPORT` enabled, which was not picked up by
pre-merge testing.
The last commit contains the fix; everything else is otherwise identical
to the approved PR.
___
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
# From the runtime build directory
$ ninja LibomptUnitTests
$ OFFLOAD_TRACE=1 ./offload/unittests/OffloadAPI/offload.unittests
```
### Open questions and future work
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: 98204a2e5bb754b0260175e42614c5463807beb5
https://github.com/llvm/llvm-project/commit/98204a2e5bb754b0260175e42614c5463807beb5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
A llvm/test/Bitcode/Inputs/invalid-initializer.bc
M llvm/test/Bitcode/invalid.test
Log Message:
-----------
[Bitcode] Verify types for aggregate initializers
Unfortunately all the nice error messages get lost because we
don't forward errors from lazy value materialization.
Fixes https://github.com/llvm/llvm-project/issues/117707.
Commit: b869f1bd4fc96fd1d2038720bd1ca84788d71370
https://github.com/llvm/llvm-project/commit/b869f1bd4fc96fd1d2038720bd1ca84788d71370
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
Log Message:
-----------
[clang] Remove unused lambda capture (NFC)
/llvm-project/clang/lib/Basic/Targets/X86.cpp:1368:23:
error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture]
auto getPriority = [this](StringRef Feature) -> unsigned {
^~~~
1 error generated.
Commit: 159e6012beb5cfd9864b4e2a910086d6f1230b03
https://github.com/llvm/llvm-project/commit/159e6012beb5cfd9864b4e2a910086d6f1230b03
Author: 执着 <118413413+dty2 at users.noreply.github.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Stop.h
M flang/include/flang/Runtime/stop.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/runtime/stop.cpp
A flang/test/Lower/Intrinsics/backtrace.f90
Log Message:
-----------
[flang]Add new intrinsic function backtrace and complete the TODO of abort (#117603)
Hey guys, I found that Flang's built-in ABORT function is incomplete
when I was using it. Compared with gfortran's ABORT (which can both
abort and print out a backtrace), flang's ABORT implementation lacks the
function of printing out a backtrace. This feature is essential for
debugging and understanding the call stack at the failure point.
To solve this problem, I completed the "// TODO:" of the abort function,
and then implemented an additional built-in function BACKTRACE for
flang. After a brief reading of the relevant source code, I used
backtrace and backtrace_symbols in "execinfo.h" to quickly implement
this. But since I used the above two functions directly, my
implementation is slightly different from gfortran's implementation (in
the output, the function call stack before main is additionally output,
and the function line number is missing). In addition, since I used the
above two functions, I did not need to add -g to embed debug information
into the ELF file, but needed -rdynamic to ensure that the symbols are
added to the dynamic symbol table (so that the function name will be
printed out).
Here is a comparison of the output between gfortran 's backtrace and my
implementation:
gfortran's implemention output:
```
#0 0x557eb71f4184 in testfun2_
at /home/hunter/plct/fortran/test.f90:5
#1 0x557eb71f4165 in testfun1_
at /home/hunter/plct/fortran/test.f90:13
#2 0x557eb71f4192 in test_backtrace
at /home/hunter/plct/fortran/test.f90:17
#3 0x557eb71f41ce in main
at /home/hunter/plct/fortran/test.f90:18
```
my impelmention output:
```
Backtrace:
#0 ./test(_FortranABacktrace+0x32) [0x574f07efcf92]
#1 ./test(testfun2_+0x14) [0x574f07efc7b4]
#2 ./test(testfun1_+0xd) [0x574f07efc7cd]
#3 ./test(_QQmain+0x9) [0x574f07efc7e9]
#4 ./test(main+0x12) [0x574f07efc802]
#5 /usr/lib/libc.so.6(+0x25e08) [0x76954694fe08]
#6 /usr/lib/libc.so.6(__libc_start_main+0x8c) [0x76954694fecc]
#7 ./test(_start+0x25) [0x574f07efc6c5]
```
test program is:
```
function testfun2() result(err)
implicit none
integer :: err
err = 1
call backtrace
end function testfun2
subroutine testfun1()
implicit none
integer :: err
integer :: testfun2
err = testfun2()
end subroutine testfun1
program test_backtrace
call testfun1()
end program test_backtrace
```
I am well aware of the importance of line numbers, so I am now working
on implementing line numbers (by parsing DWARF information) and
supporting cross-platform (Windows) support.
Commit: 1858a4ebf0ebe9f1f3be6204af204e420e33bb6a
https://github.com/llvm/llvm-project/commit/1858a4ebf0ebe9f1f3be6204af204e420e33bb6a
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/Runtime/Stop.h
M flang/include/flang/Runtime/stop.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/Runtime/Stop.cpp
M flang/runtime/stop.cpp
R flang/test/Lower/Intrinsics/backtrace.f90
Log Message:
-----------
Revert "[flang]Add new intrinsic function backtrace and complete the TODO of abort" (#117990)
Reverts llvm/llvm-project#117603 due to failed buildbot
https://lab.llvm.org/buildbot/#/builders/152/builds/710
The important bit of the log was
```
FAILED: CMakeFiles/FortranRuntime.dir/stop.cpp.o
ccache /usr/bin/g++ -DFLANG_LITTLE_ENDIAN=1 -DGTEST_HAS_RTTI=0 -DRT_USE_LIBCUDACXX=1 -D_DEBUG -D_GLIBCXX_ASSERTIONS -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/../include -I/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/build -I/home/buildbot/worker/third-party/nv/cccl/libcudacxx/include -fvisibility-inlines-hidden -Werror=date-time -fno-lifetime-dse -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -Wimplicit-fallthrough -Wno-nonnull -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -fno-lto -O3 -DNDEBUG -U_GLIBCXX_ASSERTIONS -U_LIBCPP_ENABLE_ASSERTIONS -UNDEBUG -std=c++17 -fno-exceptions -fno-unwind-tables -fno-asynchronous-unwind-tables -fno-rtti -MD -MT CMakeFiles/FortranRuntime.dir/stop.cpp.o -MF CMakeFiles/FortranRuntime.dir/stop.cpp.o.d -o CMakeFiles/FortranRuntime.dir/stop.cpp.o -c /home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/stop.cpp
/home/buildbot/worker/as-builder-7/ramdisk/flang-runtime-cuda-gcc/llvm-project/flang/runtime/stop.cpp:19:10: fatal error: llvm/Config/config.h: No such file or directory
19 | #include "llvm/Config/config.h"
| ^~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
```
CC @dty2
Commit: 6f55d7d22c1ebf2b8425c5864b335762bc3d5363
https://github.com/llvm/llvm-project/commit/6f55d7d22c1ebf2b8425c5864b335762bc3d5363
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/79eb406a67fe08458548289da72cda18248a9313
Commit: cf47898453c83c977f92155c03e9cf205bfb2b19
https://github.com/llvm/llvm-project/commit/cf47898453c83c977f92155c03e9cf205bfb2b19
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
Log Message:
-----------
[clang] Remove unused lambda capture. (#117988)
Fixes regression in sanitizer buildbots caused by #116257.
Commit: b7749efb749541716b6785c48fc8d6c2a4453ffb
https://github.com/llvm/llvm-project/commit/b7749efb749541716b6785c48fc8d6c2a4453ffb
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M mlir/lib/Dialect/MPI/IR/CMakeLists.txt
M mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
Log Message:
-----------
adding MLIRMemRefDialect (#117986)
fixing post-CI failures #104566
Commit: 32ef417603e1b747c2be946f8193fdb7c31d957e
https://github.com/llvm/llvm-project/commit/32ef417603e1b747c2be946f8193fdb7c31d957e
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
Log Message:
-----------
Fix CMake dependencies on mlir-linalg-ods-yaml-gen (#113565)
Fix a number of dependencies issue to build mlir-linalg-ods-yaml-gen
host binary which make a cross-build using the Make generator fail.
Namely:
- do not use binary path for the custom target created when
LLVM_USE_HOST_TOOLS is true;
- use target name instead of name of variable holding the target name
for add_custom_target and set_target_properties in setup_host_tool();
- force setting of executable and target cache variable which are only
used as global variables;
- remove dependency on target defined in different directory in
add_linalg_ods_yaml_gen() since add_custom_target DEPENDS can only be
used on "files and outputs of custom commands created with
add_custom_command() command calls in the same directory";
- remove unneeded dependency on ${MLIR_LINALG_ODS_YAML_GEN_EXE}, the
target dependency will ensure the binary will be built.
Note that we keep using ${MLIR_LINALG_ODS_YAML_GEN_EXE} in the COMMAND
rather than use ${MLIR_LINALG_ODS_YAML_GEN_TARGET} because when
LLVM_NATIVE_TOOL_DIR is used the latter is an empty string.
Testing-wise, all three codepaths in get_host_tool_path() were tested
with both GNU Make and Ninja generators:
- cross-compiling with LLVM_NATIVE_TOOL_DIR checks the if path;
- cross-compiling without LLVM_NATIVE_TOOL_DIR checks the elseif path;
- native build without LLVM_NATIVE_TOOL_DIR checks the else path.
Commit: 6e720df1ae23c715aefc36476ab46284a96e9371
https://github.com/llvm/llvm-project/commit/6e720df1ae23c715aefc36476ab46284a96e9371
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
Log Message:
-----------
[clang] Improve the lifetime_capture_by diagnostic on the constructor. (#117792)
With this change, the lifetime_capture_by code path will not handle the
constructor decl to avoid bogus diagnostics (see the testcase).
Instead, we reuse the lifetimebound code as the
lifetime_capture_by(this) has the same semantic as lifetimebound in
constructor. The downside is that the lifetimebound diagnostic is reused
for the capture case (I think it is not a big issue).
Fixes #117680
Commit: cb5bdf8ce095b0b9fe874545e4d54d97d552a1c4
https://github.com/llvm/llvm-project/commit/cb5bdf8ce095b0b9fe874545e4d54d97d552a1c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
Log Message:
-----------
[X86] Remove HSW/BDW incorrect MOVQ2DQ override
MOVQ2DQ is treated the same as other vector moves on Port015 (matches SandyBridge, not Skylake or later).
Confirmed by augner/uops.info
Commit: 5208bc3694473f9378fc0d98eeee63e5ad5c5f04
https://github.com/llvm/llvm-project/commit/5208bc3694473f9378fc0d98eeee63e5ad5c5f04
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "Reland #2 - [Offload] Introduce offload-tblgen and initial new API implementation (#108413. #117704)" (#117995)
Reverts llvm/llvm-project#117894
Buildbot failures in OpenMP/Offload bots.
https://lab.llvm.org/buildbot/#/builders/30/builds/11193
Commit: 392bd3404b98c2be74e4e94d2019dffaa85919eb
https://github.com/llvm/llvm-project/commit/392bd3404b98c2be74e4e94d2019dffaa85919eb
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
Log Message:
-----------
[WebAssembly] use poison instead of undef as placeholder for missing args [NFC]
Commit: 12ccb628da231f3ab751c8e7b759e9920d38510b
https://github.com/llvm/llvm-project/commit/12ccb628da231f3ab751c8e7b759e9920d38510b
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaAttr.cpp
Log Message:
-----------
[clang] Add a common definition of isPointerLikeType for lifetime analysis (#117315)
Also checks for annotation for template specializations which sometimes
may not have the annotation attached.
Commit: e4ee970c4b286b472a4c0b0cb43da85f77e97d79
https://github.com/llvm/llvm-project/commit/e4ee970c4b286b472a4c0b0cb43da85f77e97d79
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/utils/TableGen/SveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
Log Message:
-----------
[AArch64] Implement intrinsics for F1CVTL/F2CVTL and BF1CVTL/BF2CVTL (#116959)
This patch implements the following intrinsics:
8-bit floating-point convert to deinterleaved half-precision or
BFloat16.
``` c
// Variant is also available for: _bf16[_mf8]_x2
svfloat16x2_t svcvtl1_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm) __arm_streaming;
svfloat16x2_t svcvtl2_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm) __arm_streaming;
```
Defined in https://github.com/ARM-software/acle/pull/323
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Marian Lukac marian.lukac at arm.com
Commit: c952f0ee5436318733c1ab21a8a7402f7f0a4caa
https://github.com/llvm/llvm-project/commit/c952f0ee5436318733c1ab21a8a7402f7f0a4caa
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/critical_within_default.f90
Log Message:
-----------
[Flang][OpenMP] Do not default privatize symbols that are not variables (#117886)
Fixes an issue where the compiler is trying to default privatize
construct names.
Fixes #112572
Commit: 53326ee0cf45fce3f80e2e98638dd27edb20c516
https://github.com/llvm/llvm-project/commit/53326ee0cf45fce3f80e2e98638dd27edb20c516
Author: Nathan Gauër <brioche at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/branching/if-merging.ll
M llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll
M llvm/test/CodeGen/SPIRV/instructions/ret-type.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll
M llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll
M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-simple-while-identity.ll
M llvm/test/CodeGen/SPIRV/structurizer/return-early.ll
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVSortBlocksTests.cpp
Log Message:
-----------
[SPIR-V] Fix block sorting with irreducible CFG (#116996)
Block sorting was assuming reducible CFG. Meaning we always had a best
node to continue with. Irreducible CFG makes breaks this assumption, so
the algorithm looped indefinitely because no node was a valid candidate.
Fixes #116692
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 79dab3f5ebac85b7cd1f4b1943d72776db9bcf70
https://github.com/llvm/llvm-project/commit/79dab3f5ebac85b7cd1f4b1943d72776db9bcf70
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
Log Message:
-----------
[CostModel][X86] Add shuffle 'splat' tests for broadcasts of non-zero element index.
As noticed on #115201 - its possible for SK_Broadcast to occur for non-zero element index which we don't currently handle.
Commit: ddaf1d68784a03fd3d476e25689f25ba9c5f961a
https://github.com/llvm/llvm-project/commit/ddaf1d68784a03fd3d476e25689f25ba9c5f961a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/gfni-lzcnt.ll
A llvm/test/CodeGen/X86/gfni-tzcnt.ll
Log Message:
-----------
[X86] Add GFNI test coverage for vXi8 LZCNT/TZCNT
Commit: 07a8ebed56cfa223d1587903e4de0d5788b5f777
https://github.com/llvm/llvm-project/commit/07a8ebed56cfa223d1587903e4de0d5788b5f777
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/warn-memaccess.cpp
Log Message:
-----------
[clang] Move warning about memset/memcpy to NonTriviallyCopyable type… (#117387)
…s to its own flag
Namely -Wnontrivial-memcall, implied by -Wnontrivial-memaccess
This is a followup to #111434
Commit: c5cd1e958c2cea9fe5a6a9087c3481537d598e24
https://github.com/llvm/llvm-project/commit/c5cd1e958c2cea9fe5a6a9087c3481537d598e24
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/__vector/vector_bool.h
M libcxx/test/std/containers/sequences/vector.bool/ctor_exceptions.pass.cpp
A libcxx/test/std/containers/sequences/vector/common.h
Log Message:
-----------
[libc++] Add exception guard for vector<bool>::__init_with_sentinel (#115491)
As a drive-by, also improve the test coverage for throwing exceptions
in vector<bool> constructors.
Commit: 3923e0451a4b02c4fe7c394e0f0ec90708ebca7a
https://github.com/llvm/llvm-project/commit/3923e0451a4b02c4fe7c394e0f0ec90708ebca7a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
Log Message:
-----------
[AMDGPU] Preserve all analyses if nothing changed (#117994)
Commit: 6cbc37383f4ad32474a59976df3da0ee53f68fed
https://github.com/llvm/llvm-project/commit/6cbc37383f4ad32474a59976df3da0ee53f68fed
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/CMakeLists.txt
R libcxx/src/legacy_pointer_safety.cpp
Log Message:
-----------
[libc++] Remove the pointer safety functions from the dylib (#117390)
The pointer safety functions were never implemented by anyone in a
non-trivial way, which lead us to removing them entirely from the
headers when they were removed in C++23. This also means that just about
nobody ever called these functions, especially not in production code.
Because of that, we expect there to be no references in the wild to the
functions in the dylib. Because of that, this patch removes the symbols
from the dylib.
Commit: c4fbb6500a557fec592af8b9c398169591cdcc5d
https://github.com/llvm/llvm-project/commit/c4fbb6500a557fec592af8b9c398169591cdcc5d
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_GNU_template_name.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/DW_AT_GNU_template_name.ll
Log Message:
-----------
[llvm-debuginfo-analyzer] Add support for DW_AT_GNU_template_name. (#115724)
For the given C++ code:
```
template <typename T> class Foo { T Member; };
template <template <typename T> class TemplateType>
class Bar {
TemplateType<int> Int;
};
template <template <template <typename> class> class TemplateTemplateType>
class Baz {
TemplateTemplateType<Foo> Foo;
};
typedef Baz<Bar> Example;
Example TT;
```
The '--attribute=encoded' option, will produce the logical view:
```
{Class} 'Foo<int>'
{Encoded} <int>
{Class} 'Bar<Foo>'
{Encoded} <> <-- Missing the template argument info (Foo)
{Class} 'Baz<Bar>'
{Encoded} <> <-- Missing the template argument info (Bar)
```
When the template argument is another template it is not included in the
{Encoded} field. The correct output should be:
```
{Class} 'Foo<int>'
{Encoded} <int>
{Class} 'Bar<Foo>'
{Encoded} <Foo>
{Class} 'Baz<Bar>'
{Encoded} <Bar>
```
Commit: b5ed375f9d63c1f37bb490f32898e6dc711c8a15
https://github.com/llvm/llvm-project/commit/b5ed375f9d63c1f37bb490f32898e6dc711c8a15
Author: Peter Waller <peter.waller at arm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/check-init-not-moved.s
Log Message:
-----------
[BOLT] Skip _init; avoiding GOT breakage for static binaries (#117751)
_init is used during startup of binaires. Unfortunately, its
address can be shared (at least on AArch64 glibc static binaries) with a
data
reference that lives in the GOT. The GOT rewriting is currently unable
to distinguish between data addresses and function addresses. This leads
to the data address being incorrectly rewritten, causing a crash on
startup of the binary:
Unexpected reloc type in static binary.
To avoid this, don't consider _init for being moved, by skipping it.
~We could add further conditions to narrow the skipped case for known
crashes, but as a straw man I thought it'd be best to keep the condition
as simple as possible and see if there any objections to this.~
(Edit: this broke the test
bolt/test/runtime/X86/retpoline-synthetic.test,
because _init was skipped from the retpoline pass and it has an indirect
call in it, so I include a check for static binaries now, which avoids
the test failure,
but perhaps this could/should be narrowed further?)
For now, skip _init for static binaries on any architecture; we could
add further conditions to narrow the skipped case for known crashes, but
as a straw man I thought it'd be best to keep the condition as simple as
possible and see if there any objections to this.
Updates #100096.
Commit: 3a01b46dae1a00f77ed8c46a4239595803c9e35e
https://github.com/llvm/llvm-project/commit/3a01b46dae1a00f77ed8c46a4239595803c9e35e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Move getGFNICtrlMask before CTLZ/CTTZ lowering. NFC.
Pulled out of #118012
Commit: 2a6e5896a572c3be47ffe78afed8ba6ef278d336
https://github.com/llvm/llvm-project/commit/2a6e5896a572c3be47ffe78afed8ba6ef278d336
Author: Rafael Eckstein <44746868+Casperento at users.noreply.github.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/unittests/Transforms/Utils/CMakeLists.txt
A llvm/unittests/Transforms/Utils/MergeFunctionsTest.cpp
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Log Message:
-----------
[MergeFunctions] Add support to run the pass over a set of function pointers (#111045)
This modification will enable the usage of `MergeFunctions` as a
standalone library. Currently, `MergeFunctions` can only be applied to
an entire module. By adopting this change, developers will gain the
flexibility to reuse the `MergeFunctions` code within their own
projects, choosing which functions to merge; hence, promoting code
reusability. Notice that this modification will not break backward
compatibility, because `MergeFunctions` will still work as a pass after
the modification.
Commit: b96e7570c991f1bb67646a20427a83f247326a25
https://github.com/llvm/llvm-project/commit/b96e7570c991f1bb67646a20427a83f247326a25
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/IPO/CMakeLists.txt
A llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
M llvm/unittests/Transforms/Utils/CMakeLists.txt
R llvm/unittests/Transforms/Utils/MergeFunctionsTest.cpp
Log Message:
-----------
[UnitTests] Move MergeFunction test from Utils to IPO
So we depend on the correct library.
Commit: 45b567be8d0d430c786c41f826d192fadf863bb8
https://github.com/llvm/llvm-project/commit/45b567be8d0d430c786c41f826d192fadf863bb8
Author: Nathan Gauër <brioche at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVPartialOrderingVisitorTests.cpp
Log Message:
-----------
[SPIR-V] Add partial order tests, assert reducible (#117887)
Add testing for the visitor and added a note explaining irreducible CFG
are not supported.
Related to #116692
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 66d350a01738c0c64a28b943af5e995a5fbc348d
https://github.com/llvm/llvm-project/commit/66d350a01738c0c64a28b943af5e995a5fbc348d
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/PowerPC/ssubo-32.ll
Log Message:
-----------
[PowerPC][NFC] Pre-commit test case to prepare for patch to custom lower ssubo
Commit: f623df6376b94906671ad6e875e6f504b74fed31
https://github.com/llvm/llvm-project/commit/f623df6376b94906671ad6e875e6f504b74fed31
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
Log Message:
-----------
[InstSimplify] Add tests for monotonic icmps (NFC)
Commit: 12cefcc7ecd2615069206b35b0ea81b9e78bb1ea
https://github.com/llvm/llvm-project/commit/12cefcc7ecd2615069206b35b0ea81b9e78bb1ea
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
A llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int-also-fusable-multiply.ll
Log Message:
-----------
[Matrix] Skip already fused instructions before trying to fuse multiply.
lowerDotProduct called above may already lower a matrix multiply and
mark it as procssed by adding it to FusedInsts. Don't try to process it
again in LowerMatrixMultiplyFused by checking if FusedInsts.
Without this change, we trigger an assertion when trying to erase the
same original matrix multiply twice.
Commit: 26fd693b979f17c83cbd5a3313fdea950ce3d356
https://github.com/llvm/llvm-project/commit/26fd693b979f17c83cbd5a3313fdea950ce3d356
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
Log Message:
-----------
RegisterCoalescer: Fix creating full / empty subrange on undef subreg use (#117936)
Commit: aa5cdcea3950b26a6b755201706bb1961e65eaa5
https://github.com/llvm/llvm-project/commit/aa5cdcea3950b26a6b755201706bb1961e65eaa5
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
LAA: improve code in a couple of routines (NFC) (#108092)
Commit: 4e8eabd93e2c60a9dc2f6afde506012fbca77f81
https://github.com/llvm/llvm-project/commit/4e8eabd93e2c60a9dc2f6afde506012fbca77f81
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DeadStoreElimination/stores-of-existing-values.ll
Log Message:
-----------
DSE: pre-commit tests for scalable vectors (#110669)
As AliasAnalysis now has support for scalable sizes, add tests to
DeadStoreElimination covering the scalable vectors case, in preparation
to extend it.
Commit: b207a17ea07df4cbcae5509dee3e8e1d09a485df
https://github.com/llvm/llvm-project/commit/b207a17ea07df4cbcae5509dee3e8e1d09a485df
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
R llvm/utils/merge-json.py
M runtimes/CMakeLists.txt
Log Message:
-----------
Revert "[Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)"
This reverts commit 054f914741421ca9dd1eaa58ea74a20f8695bae6, which was
found to break the runtimes build.
Commit: 261a4026e8a367eda229879838709b92abaf445c
https://github.com/llvm/llvm-project/commit/261a4026e8a367eda229879838709b92abaf445c
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate2.f90
M flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
Log Message:
-----------
[Flang][OpenMP] Use internal linkage for OpenMP code-gen'ed helper functions (#117911)
When compiling WORKSHARE construct in different compilation units, a
linker error happened, when two equal WORKSHARE constructs with a copy
operation have been compiled:
```
/usr/bin/ld: module2.o: in function `_workshare_copy_f64':
FIRModule:(.text+0x0): multiple definition of `_workshare_copy_f64'; module1.o:FIRModule:(.text+0x0): first defined here
```
Reason is that the generate copy function has the wrong linkage:
```
0000000000000000 T _workshare_copy_f64
```
while it should be
```
0000000000000000 t _workshare_copy_f64
```
Commit: 335cfb3441242a78447d1db42cd67ce9eba829db
https://github.com/llvm/llvm-project/commit/335cfb3441242a78447d1db42cd67ce9eba829db
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/lib/Headers/avx512vpopcntdqintrin.h
M clang/lib/Headers/avx512vpopcntdqvlintrin.h
M clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c
M clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
Log Message:
-----------
[clang][x86] Add initial constexpr support for VPOPCNTDQ intrinsics (#118017)
#117473 added constexpr support to __builtin_elementwise_popcount - which the VPOPCNTDQ intrinsics just wrap.
Still working on how to make __builtin_ia32_select* intrinsic wrappers constexpr
Commit: 611ccfcae9842a1356195189d5595ef1684e3df4
https://github.com/llvm/llvm-project/commit/611ccfcae9842a1356195189d5595ef1684e3df4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Add reduced test case for #114360
Commit: 448ac7d3418a31d35b462440c8bf644287efac8a
https://github.com/llvm/llvm-project/commit/448ac7d3418a31d35b462440c8bf644287efac8a
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
Log Message:
-----------
[lldb][Mach-O] Handle shared cache binaries correctly (#117832)
The Mach-O load commands have an LC_SYMTAB / struct symtab_command which
represents the offset of the symbol table (nlist records) and string
table for this binary. In a mach-o binary on disk, these are file
offsets. If a mach-o binary is loaded in memory with all segments
consecutive, the `symoff` and `stroff` are the offsets from the TEXT
segment (aka the mach-o header) virtual address to the virtual address
of the start of these tables.
However, if a Mach-O binary is a part of the shared cache, then the
segments will be separated -- they will have different slide values. And
it is possible for the LINKEDIT segment to be greater than 4GB away from
the TEXT segment in the virtual address space, so these 32-bit offsets
cannot express the offset from TEXT segment to these tables.
Create separate uint64_t variables to track the offset to the symbol
table and string table, instead of reusing the 32-bit ones in the
symtab_command structure.
rdar://140432279
Commit: a4c8ef0f401d86040594cc6f01bcdad9392e8ee2
https://github.com/llvm/llvm-project/commit/a4c8ef0f401d86040594cc6f01bcdad9392e8ee2
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Fix detecting _Float16 support for secondary targets (#117813)
It turns out we were not passing -m32 to the check_c_source_compiles()
invocation since CMAKE_REQUIRE_FLAGS needs to be string separated list
and
we were passing a ;-separated CMake list which appears to be parsed by
CMake as 'ignore all arguments beyond the first'.
Fix this by transforming the list to a command line first.
With this change, Clang 17 no longer claims to support _Float16 for
i386.
Commit: dab4121a55225fd00f3db1cb232cf563ea573ef2
https://github.com/llvm/llvm-project/commit/dab4121a55225fd00f3db1cb232cf563ea573ef2
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
M llvm/test/CodeGen/PowerPC/ssubo-32.ll
Log Message:
-----------
[PowerPC] Add custom lowering for ssubo (#111748) (#115875)
This patch is to improve the codegen for ssubo node for i32 by custom lowering.
Commit: 961c66c57144ac46b65277338d9d1ebdc284e0df
https://github.com/llvm/llvm-project/commit/961c66c57144ac46b65277338d9d1ebdc284e0df
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] shrinkAndImmediate - bail on failed constant fold
Workaround for issue #114360 where shrinkAndImmediate folds away the AND after the ZEXT has already been folded away to SUBREG_TO_REG losing the implicit zext guarantee.
There's the possibility that other instructions can result in a similar regression, but this is a stopgap until I can investigate whether shrinkAndImmediate needs to be replaced entirely.
Fixes #114360
Commit: 056153f36eca184f81969f5cd5c8cd967c935f96
https://github.com/llvm/llvm-project/commit/056153f36eca184f81969f5cd5c8cd967c935f96
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__vector/vector.h
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/GenerateInput.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
Optimize vector::assign for InputIterator-only pair inputs (#113852)
This PR optimizes the input iterator overload of `assign(_InputIterator,
_InputIterator)` in `std::vector<_Tp, _Allocator>` by directly assigning
to already initialized memory, rather than first destroying existing
elements and then constructing new ones. By eliminating unnecessary
destruction and construction, the proposed algorithm enhances the
performance by up to 2x for trivial element types (e.g.,
`std::vector<int>`), up to 2.6x for non-trivial element types like
`std::vector<std::string>`, and up to 3.4x for more complex non-trivial
types (e.g., `std::vector<std::vector<int>>`).
### Google Benchmarks
Benchmark tests (`libcxx/test/benchmarks/vector_operations.bench.cpp`)
were conducted for the `assign()` implementations before and after this
patch. The tests focused on trivial element types like
`std::vector<int>`, and non-trivial element types such as
`std::vector<std::string>` and `std::vector<std::vector<int>>`.
#### Before
```
-------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------------------------------------------------
BM_AssignInputIterIter/vector_int/1024/1024 1157 ns 1169 ns 608188
BM_AssignInputIterIter<32>/vector_string/1024/1024 14559 ns 14710 ns 47277
BM_AssignInputIterIter<32>/vector_vector_int/1024/1024 26846 ns 27129 ns 25925
```
#### After
```
-------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
-------------------------------------------------------------------------------------------------
BM_AssignInputIterIter/vector_int/1024/1024 561 ns 566 ns 1242251
BM_AssignInputIterIter<32>/vector_string/1024/1024 5604 ns 5664 ns 128365
BM_AssignInputIterIter<32>/vector_vector_int/1024/1024 7927 ns 8012 ns 88579
```
Commit: 81c88135e402d3dfee7387acef86b173132cfb64
https://github.com/llvm/llvm-project/commit/81c88135e402d3dfee7387acef86b173132cfb64
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/locale
Log Message:
-----------
[libc++] Use the __strtoNUM functions from __locale instead of the old API (#118029)
The commit where I switched from using the old locale base API to the
new functions defined inside the __locale namespace forgot to update
references to the strtoNUM functions. This patch fixes that.
Commit: 59716479fc2f78ccabb2fc47b23cdc636d4ce122
https://github.com/llvm/llvm-project/commit/59716479fc2f78ccabb2fc47b23cdc636d4ce122
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
A libcxx/docs/CodingGuidelines.rst
M libcxx/docs/Contributing.rst
M libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
R libcxx/docs/DesignDocs/NodiscardPolicy.rst
M libcxx/docs/index.rst
Log Message:
-----------
[libc++] Add coding guidelines to the docs (#117051)
We have a buch of coding guidelines which are either documented as
design docs, which aren't really applicable or not at all. This moves
coding guidelines we have currently in the design docs into a separate
file and adds a bunch of guidelines which we have but aren't documented
anywhere.
Commit: d648eed5899c4be10f1f7866eebef2bc171e673f
https://github.com/llvm/llvm-project/commit/d648eed5899c4be10f1f7866eebef2bc171e673f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++] Simplify the implementation of reserve() and shrink_to_fit() (#113453)
Since we changed the implementation of `reserve(size_type)` to only ever
extend,
it doesn't make a ton of sense anymore to have `__shrink_or_extend`,
since the code
paths of `reserve` and `shrink_to_fit` are now almost completely
separate.
This patch splits up `__shrink_or_extend` so that the individual parts
are in `reserve`
and `shrink_to_fit` depending on where they are needed.
Commit: d9c269577e6e68e1336461f266b20780f4d78dba
https://github.com/llvm/llvm-project/commit/d9c269577e6e68e1336461f266b20780f4d78dba
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Remove manual constant fold in VPWidenIntOrFpInductionRecipe. NFC (#118028)
This manual constant folding was added in 2017 in
https://reviews.llvm.org/D29956, but since then it looks like IRBuilder
has learnt to fold it away itself.
I'm not sure at what point this happened, I just verified this by
stepping through the call to CreateVectorSplat in the debugger.
Commit: d106a39c3372b924668f203fedbce69aa986cf50
https://github.com/llvm/llvm-project/commit/d106a39c3372b924668f203fedbce69aa986cf50
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Log Message:
-----------
[AArch64] Minor cleanup and speedup for getVectorInstrCostHelper
If UserToExtractIdx is empty then we can skip checking the users.
Commit: f2d500c61701fc50f5c0c2cd9660a93e15ecc9b9
https://github.com/llvm/llvm-project/commit/f2d500c61701fc50f5c0c2cd9660a93e15ecc9b9
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Fix bug in `UnresolvedMaterializationRewrite` rollback (#105949)
When an unresolved materialization (`unrealized_conversion_cast` op) is
rolled back, the mapping should be rolled back as well, regardless of
whether it is a source, target or argument materialization. Otherwise,
we accumulate pointers to erased IR in the `mapping`. This is harmless
in most cases, but can cause issues when a new operation is allocated at
the same memory location and the pointer is "reused".
It is not possible to write a test case for this because I cannot
trigger the pointer reuse programmatically.
Commit: c2171d748685be8c7ce2366deefe01aaae1c61a0
https://github.com/llvm/llvm-project/commit/c2171d748685be8c7ce2366deefe01aaae1c61a0
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
Log Message:
-----------
[gn] port fb3765959f
Commit: 7c5300e73445310ba40515bc01c2da59d4c58d50
https://github.com/llvm/llvm-project/commit/7c5300e73445310ba40515bc01c2da59d4c58d50
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn build] Port 45b567be8d0d
Commit: 958ab3a4a53357ddf27b7ccae8bdbae5878d3cca
https://github.com/llvm/llvm-project/commit/958ab3a4a53357ddf27b7ccae8bdbae5878d3cca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn build] Port 53326ee0cf45
Commit: bfa6c9a959e15e4548e411144fc7eda7d6b7e4dc
https://github.com/llvm/llvm-project/commit/bfa6c9a959e15e4548e411144fc7eda7d6b7e4dc
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
Log Message:
-----------
[gn build] Port 6cbc37383f4a
Commit: eb42e94d9793d5426de64266ef637b3267ed0b40
https://github.com/llvm/llvm-project/commit/eb42e94d9793d5426de64266ef637b3267ed0b40
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Transforms/IPO/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port b96e7570c991
Commit: c5ab28a42db95e287bf7f4623e8f5703b2f200d9
https://github.com/llvm/llvm-project/commit/c5ab28a42db95e287bf7f4623e8f5703b2f200d9
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
Log Message:
-----------
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
Commit: dab9fa2d7f3b3092d4ab0c815868ec68a968a31a
https://github.com/llvm/llvm-project/commit/dab9fa2d7f3b3092d4ab0c815868ec68a968a31a
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Flang.h
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Driver/mabi-loongarch.f90
A flang/test/Fir/struct-passing-loongarch64-byreg.fir
A flang/test/Fir/struct-passing-return-loongarch64-bystack.fir
A flang/test/Fir/struct-return-loongarch64-byreg.fir
Log Message:
-----------
[Flang] LoongArch64 support for BIND(C) derived types in mabi=lp64d. (#117108)
This patch:
- Supports both the passing and returning of BIND(C) type parameters.
- Adds `mabi` check for LoongArch64. Currently, flang only supports
`mabi=` option
set to `lp64d` in LoongArch64, other ABIs will report an error and may
be supported
in the future.
Reference ABI:
https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#subroutine-calling-sequence
Commit: d714b221c77203107284544b8f5543bd4c35ccc9
https://github.com/llvm/llvm-project/commit/d714b221c77203107284544b8f5543bd4c35ccc9
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Analysis/CostModel/AArch64/extract_float_streaming.ll
Log Message:
-----------
[AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. (#117749)
If the getRegisterBitWidth is zero (such as in sme streaming functions),
then we could hit a crash from using % RegWidth.
Commit: b2d3cb1e7502a5ddb7d6688dce5cf51573f6189c
https://github.com/llvm/llvm-project/commit/b2d3cb1e7502a5ddb7d6688dce5cf51573f6189c
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[TTI][RISCV] Remove deduplicate type-based VP costing of VPReduction.NFC (#117708)
Refered to: #115983
Commit: d83148f9b9debde1358f0686594da208ce33182e
https://github.com/llvm/llvm-project/commit/d83148f9b9debde1358f0686594da208ce33182e
Author: Abhishek Varma <avarma094 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[MLIR][Affine] Update ::fold() to have constant basis attr for affine.delinearize_index/linearize_index (#117572)
-- This commit updates `::fold()` to have constant(CST)
attribute for affine.delinearize_index/linearize_index op's basis
wherever applicable.
-- Essentially the code checks if the mixed basis OpFoldResult
set contains any constant SSA value and converts it to a constant
integer instead.
Signed-off-by: Abhishek Varma <abhvarma at amd.com>
Commit: 8fcbba82d6c8038c4a0c5859275523414107b198
https://github.com/llvm/llvm-project/commit/8fcbba82d6c8038c4a0c5859275523414107b198
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcisls-invalid.s
A llvm/test/MC/RISCV/xqcisls-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)
This extension adds 8 load/store instructions with a scaled index
addressing mode.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: d02c1676d75a6bab1252b48da9a955fc7dc1251f
https://github.com/llvm/llvm-project/commit/d02c1676d75a6bab1252b48da9a955fc7dc1251f
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Support/Error.h
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Object/XCOFFObjectFile.cpp
M llvm/lib/Support/DataExtractor.cpp
Log Message:
-----------
[Support][Error] Add ErrorAsOutParameter constructor that takes an Error by ref.
ErrorAsOutParameter's Error* constructor supports cases where an Error might not
be passed in (because in the calling context it's known that this call won't
fail). Most clients always have an Error present however, and for them an Error&
overload is more convenient.
Commit: cf478bf744fa2aacb634b151b7f6c9844f0d3851
https://github.com/llvm/llvm-project/commit/cf478bf744fa2aacb634b151b7f6c9844f0d3851
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] always clean up child process to avoid hanging ninja (#118049)
Commit: 01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
https://github.com/llvm/llvm-project/commit/01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
A llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
Log Message:
-----------
[RISCV] Set a barrier between mask producer and user of V0 (#114012)
Here we add a scheduling mutation in pre-ra scheduling, which will
add an artificial dependency edge between mask producer and its
previous nearest instruction that uses V0 register.
This prevents the overlap of live intervals of mask registers and
as a consequence we can reduce some spills/moves.
>From the test changes, we can see some improvements and also some
regressions (more vtype toggles).
Partially fixes #113489.
Commit: 9b163d2ee78383fe9a89e1f2e9c8c635a557cdf4
https://github.com/llvm/llvm-project/commit/9b163d2ee78383fe9a89e1f2e9c8c635a557cdf4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 01a15dca09e5
Commit: 9b5b3edd64e56af02295c0365269177443d4a64d
https://github.com/llvm/llvm-project/commit/9b5b3edd64e56af02295c0365269177443d4a64d
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
Log Message:
-----------
[clang-format][doc] Fix formatting, etc.
Commit: 18760ce0fd811140fe6cb9a01b766d73bb50bf4d
https://github.com/llvm/llvm-project/commit/18760ce0fd811140fe6cb9a01b766d73bb50bf4d
Author: AlexErofeev <framalex at nxt.ru>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/StmtPrinter.cpp
A clang/test/AST/ast-print-packindexingexpr.cpp
Log Message:
-----------
[Clang][AST] Fix PackIndexingExpr AST printout (#117947)
Fixes #116486
Also added a test
Commit: 2df0d2962725a26a1d8c438888f7e70946943589
https://github.com/llvm/llvm-project/commit/2df0d2962725a26a1d8c438888f7e70946943589
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in AffineOps.cpp (NFC)
/llvm-project/mlir/lib/Dialect/Affine/IR/AffineOps.cpp:4590:25:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare]
if (dynamicBasisIndex == dynamicBasis.size())
~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
1 error generated.
Commit: 96dd39c575be64896995e08881b9bc27688ce5d1
https://github.com/llvm/llvm-project/commit/96dd39c575be64896995e08881b9bc27688ce5d1
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-28 (Thu, 28 Nov 2024)
Changed paths:
M compiler-rt/lib/xray/weak_symbols.txt
M compiler-rt/lib/xray/xray_flags.cpp
M compiler-rt/lib/xray/xray_flags.h
A compiler-rt/test/xray/TestCases/Posix/default-options.cpp
M llvm/docs/XRay.rst
Log Message:
-----------
[XRay] Add `__xray_default_options` to specify build-time defined options (#117921)
Similar to `__asan_default_options`, users can specify default options
upon building the instrumented binaries by providing their own
definition of `__xray_default_options` which returns the option strings.
This is useful in cases where setting the `XRAY_OPTIONS` environment
variable might be difficult. Plus, it's a convenient way to populate
XRay options when you always want the instrumentation to be enabled.
Commit: 3b43276575fc939b4f6e8089277fac083c770990
https://github.com/llvm/llvm-project/commit/3b43276575fc939b4f6e8089277fac083c770990
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
Log Message:
-----------
[ORC] Remove some SymbolStringPtr copies.
Commit: e034c4ef7b52635bb9cc78b6d3f97a4af5002f92
https://github.com/llvm/llvm-project/commit/e034c4ef7b52635bb9cc78b6d3f97a4af5002f92
Author: vabridgers <58314289+vabridgers at users.noreply.github.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/ChrootChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/chroot.c
M clang/test/Analysis/show-checker-list.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[analyzer] Modernize, improve and promote chroot checker (#117791)
This change modernizes, improves and promotes the chroot checker from
alpha to the Unix family of checkers. This checker covers the POS05
recommendations for use of chroot.
The improvements included modeling of a success or failure from chroot
and not falsely reporting a warning along an error path. This was made
possible through modernizing the checker to be flow sensitive.
---------
Co-authored-by: einvbri <vince.a.bridgers at ericsson.com>
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: 91285e26bf67179a6804c931203c93f07c08183d
https://github.com/llvm/llvm-project/commit/91285e26bf67179a6804c931203c93f07c08183d
Author: Clement Courbet <courbet at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
A clang-tools-extra/test/clang-reorder-fields/FieldAnnotationsInMacros.cpp
Log Message:
-----------
[clang-reorder-fields] Handle macros fields declarations. (#118005)
Right now fields with macro declarations break the tool:
```
struct Foo {
Mutex mu;
int x GUARDED_BY(mu);
int y;
};
```
reordered by mu,y,x yields:
```
struct Foo {
Mutex mu;
int y GUARDED_BY(mu);
int x;
};
```
Commit: d7791f51cecbaaa81a65e4a16d781fbf338f9272
https://github.com/llvm/llvm-project/commit/d7791f51cecbaaa81a65e4a16d781fbf338f9272
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
Log Message:
-----------
[llvm-debuginfo-analyzer] Remove superfluous link components. (#118052)
As 'LLVM_TARGETS_TO_BUILD' control which targets are enabled, the lines:
AllTargetsDescs
AllTargetsDisassemblers
AllTargetsInfos
are redundant.
Commit: aa9d36869090fdff8cd416c83a5106a1b45b0ff7
https://github.com/llvm/llvm-project/commit/aa9d36869090fdff8cd416c83a5106a1b45b0ff7
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
Log Message:
-----------
[mlir][linalg] Relax scalable vectorization restrictions (#117991)
Currently, the Linalg vectorizer disallows non-trailing parallel
dimensions to be scalable, e.g., `vector_sizes [[8], 1]` (*), for cases
like:
```mlir
%0 = linalg.fill ins(%arg0 : f32) outs(%A : tensor<?x?xf32>) -> tensor<?x?xf32>
```
This restriction exists to avoid generating "scalable" arrays of
aggregates, which LLVM does not support (multi-dim vectors are lowered
into arrays of aggregates at the LLVM level).
This patch relaxes that restriction when the trailing parallel vector
dimension is `1`, e.g., for `vector_sizes [[8], 1]`. Such cases are safe
since trailing unit dimensions can be collapsed. This relaxation is
necessary to support scalable vectorization for tensor.pack, where inner
tile sizes are `[8]` (scalable) and `1` (scalar).
(*) Transform Dialect notation
Commit: a943922c0de52efb78e84e08dbc5d74f428b2377
https://github.com/llvm/llvm-project/commit/a943922c0de52efb78e84e08dbc5d74f428b2377
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Remove duplicate instruction `FF 25 ...`. (#116894)
It appears already some lines above with this comment:
"Cannot overwrite control-instruction. Return 0 to indicate failure.".
Replacing just the comment in the first appearance.
Found after creating the test in #113085.
Commit: 9b2ec87f5bce57cc900cf52a99f805d999716053
https://github.com/llvm/llvm-project/commit/9b2ec87f5bce57cc900cf52a99f805d999716053
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/iterator-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling-aggressive-std-find-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling.cpp
M clang/test/Analysis/template-param-objects.cpp
Log Message:
-----------
[analyzer] Avoid creating LazyCompoundVal when possible (#116840)
In #115916 I allowed copying empty structs.
Later in #115917 I changed how objects are copied, and basically when we
would want to copy a struct (an LCV) of a single symbol (likely coming
from an opaque fncall or invalidation), just directly bind that symbol
instead of creating an LCV referring to the symbol. This was an
optimization to skip a layer of indirection.
Now, it turns out I should have apply the same logic in #115916. I
should not have just blindly created an LCV by calling
`createLazyBinding()`, but rather check if I can apply the shortcut
described in #115917 and only create the LCV if the shortcut doesn't
apply.
In this patch I check if there is a single default binding that the copy
would refer to and if so, just return that symbol instead of creating an
LCV.
There shouldn't be any observable changes besides that we should have
fewer LCVs. This change may surface bugs in checkers that were
associating some metadata with entities in a wrong way. Notably,
STLAlgorithmModeling and DebugIteratorModeling checkers would likely
stop working after this change.
I didn't investigate them deeply because they were broken even prior to
this patch. Let me know if I should migrate these checkers to be just as
bugged as they were prior to this patch - thus make the tests pass.
Commit: 352f8688d0ca250c9e8774321f6c3bcd4298cc09
https://github.com/llvm/llvm-project/commit/352f8688d0ca250c9e8774321f6c3bcd4298cc09
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaAttr.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
Log Message:
-----------
[clang] Fix incorrect inferred lifetime_capture_by attr on STL (#118013)
We incorrectly annotate the iterator parameter for `insert` method
(`void insert(const_iterator, const value_type& value)`), because
iterator is also a gsl-pointer type.
This patch fixes it.
Commit: 27e01ee5aafb79a8aeca5fc9eb41e7f1243a7a46
https://github.com/llvm/llvm-project/commit/27e01ee5aafb79a8aeca5fc9eb41e7f1243a7a46
Author: Dmitry Sidorov <dmitry.sidorov at intel.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
Log Message:
-----------
[SPIR-V][NFC] Fix number of operands for cooperative matrix instructions (#118014)
This PR fixes number of operands of SPIR-V wrapper builtins for
cooperative matrix instructions.
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov at intel.com>
Commit: 26baa00908b2eb8b2925800af6bc64fbe53cac48
https://github.com/llvm/llvm-project/commit/26baa00908b2eb8b2925800af6bc64fbe53cac48
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/AST/ByteCode/records.cpp
A clang/test/SemaCXX/cxx20-warn-dangling-paren-list-agg-init.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
Log Message:
-----------
[clang] Diagnose dangling references for parenthesized aggregate initialization. (#117690)
Unlike brace initialization, the parenthesized aggregate initialization
in C++20 does not extend the lifetime of a temporary object bound to a
reference in an aggreate. This can lead to dangling references:
```
struct A { const int& r; };
A a1(1); // well-formed, but results in a dangling reference.
```
With this patch, clang will diagnose this common dangling issues.
Fixes #101957
Commit: e9be21786c972de93206599d4e06b79c2ca8f772
https://github.com/llvm/llvm-project/commit/e9be21786c972de93206599d4e06b79c2ca8f772
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/cmake/modules/GetHostTriple.cmake
Log Message:
-----------
[CMake] Handle clang in MSVC mode in GetHostTriple (#116701)
When configuring CMake with Clang in MSVC mode, Clang can either be
invoked with the MSVC style driver (clang-cl) or the GNU style driver
(clang). When using the MSVC style driver, CMake sets the CMake variable
MSVC (which indicates the kind of command line interface), but when
using the GNU style driver, this variable isn't set, while Clang still
operates in MSVC mode.
Even though CMake doesn't set the variable MSVC, it still does set
CMAKE_C_COMPILER_ARCHITECTURE_ID, which it does set for MSVC and Clang
in MSVC mode, but not for Clang in MinGW mode.
For this configuration, use the MSVC style,
CMAKE_C_COMPILER_ARCHITECTURE_ID based GetHostTriple implementation.
Commit: ed7f36e1ecc26d6360126fc6ed0514b592fcc029
https://github.com/llvm/llvm-project/commit/ed7f36e1ecc26d6360126fc6ed0514b592fcc029
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] update a couple of struct/vector creation examples to use poison
Commit: a174aa1e416c4e27945f5a8c646b119126dc8441
https://github.com/llvm/llvm-project/commit/a174aa1e416c4e27945f5a8c646b119126dc8441
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
Log Message:
-----------
[clang-repl] Fix generation of wasm binaries while running clang-repl in browser (#117978)
Co-authored-by: Vassil Vassilev <v.g.vassilev at gmail.com>
Commit: cb4f22c0a737b13c06f54566dac1e40cc4ec06c8
https://github.com/llvm/llvm-project/commit/cb4f22c0a737b13c06f54566dac1e40cc4ec06c8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Adjust triple on test case for #114360
An attempt to fix a buildbot failure on clang-x64-windows-msvc
Commit: 26ffca08439f23e8db43beeb021c4cae32716822
https://github.com/llvm/llvm-project/commit/26ffca08439f23e8db43beeb021c4cae32716822
Author: lonely eagle <2020382038 at qq.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/test/Dialect/Affine/ops.mlir
Log Message:
-----------
[mlir][gpu]add AffineScope to gpu.func op. (#118010)
This PR in order to solve the following problem.
https://github.com/llvm/llvm-project/pull/117721.
To efficiently implement the thread-to-data mapping relationship, I
introduced AffineScope in gpu.func(Data or thread layout).
Commit: 9c97aa5abb6aa4ce4055095a89ae7d72e1b61803
https://github.com/llvm/llvm-project/commit/9c97aa5abb6aa4ce4055095a89ae7d72e1b61803
Author: Richard Dzenis <richard at dzenis.dev>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
A llvm/test/tools/llvm-objcopy/MachO/dysymtab-zero-indirectsym.test
Log Message:
-----------
[llvm-objcopy] Always update indirectsymoff in MachO (#117726)
Let's say we've run llvm-strip over some MachO. The resulting MachO
became smaller and there are no indirect symbols anymore.
Then according to previous code we would not update indirectsymoff
field. This would lead to `MachOWriter::totalSize()` report size that is
larger than the new MachO. As a result we would get MachO that has zero
bytes past contents of the very last load command.
Codesign has a strict check that size of MachO file must be equal to
lastLoadCommand.offset + lastLoadCommand.size
If this is not satisfied codesign reports the following error
main executable failed strict validation
Fixes #117723
Commit: 7ed36b9ec6147fbada27592292bca28f9f76c983
https://github.com/llvm/llvm-project/commit/7ed36b9ec6147fbada27592292bca28f9f76c983
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr114360.ll
Log Message:
-----------
[X86] Add missing REQUIRES to test case for #114360
Commit: 0d1d1b363d9588c192152cec4f256f3edfea7e48
https://github.com/llvm/llvm-project/commit/0d1d1b363d9588c192152cec4f256f3edfea7e48
Author: itrofimow <i.trofimow at yandex.ru>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
Log Message:
-----------
[DebugInfo] Clean up LLVMSymbolizer::DemangleName API: const string& -> StringRef (#118056)
Commit: b68340c83529bd8d13d1c4441777baa31863d1cf
https://github.com/llvm/llvm-project/commit/b68340c83529bd8d13d1c4441777baa31863d1cf
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A llvm/include/llvm/CodeGen/SpillPlacement.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/SpillPlacement.cpp
R llvm/lib/CodeGen/SpillPlacement.h
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[CodeGen][NewPM] Port SpillPlacement analysis to NPM (#116618)
Commit: 8dd0da5bd1c427a7ba2091b918c59b3ee7a8b79f
https://github.com/llvm/llvm-project/commit/8dd0da5bd1c427a7ba2091b918c59b3ee7a8b79f
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Log Message:
-----------
[AArch64] Silence warning with different types in ternary. NFC
This just casts the Register to an unsigned, to fit in with the other types
returned from the function.
Commit: 5540eac4e5161d124ac547e4a9d3451408bb71e9
https://github.com/llvm/llvm-project/commit/5540eac4e5161d124ac547e4a9d3451408bb71e9
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable `from_elements` for scalable vectors (#117868)
Disables `vector.from_elements` for scalable vectors. Given that the
length of scalable vectors is unknown at compile time, the semantics of
this Op are unclear in this context.
Commit: 044362215d5264280abc807ea1da6c652530c926
https://github.com/llvm/llvm-project/commit/044362215d5264280abc807ea1da6c652530c926
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/mmx-cvt.ll
Log Message:
-----------
[X86] Add test for new _mm_movpi64_epi64 lowering
With the MMX retirement, _mm_movpi64_epi64 now lowers to shuffle((__m64)(double)x,(__m64)0) pattern - which demonstrates a unnecessary FPU->GPU->FPU transfer
Commit: 1784275e43976df2388a27805fb684def76c5c8a
https://github.com/llvm/llvm-project/commit/1784275e43976df2388a27805fb684def76c5c8a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-masked.ll
Log Message:
-----------
[X86] vector-shuffle-masked.ll - update extract_subvector shuffle tests to take poison arg instead of undef
Commit: 568ae0afabe07837ecfae8f8fe9dacf0de74a1e5
https://github.com/llvm/llvm-project/commit/568ae0afabe07837ecfae8f8fe9dacf0de74a1e5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
Log Message:
-----------
[X86] widen_shuffle-1.ll - update shuffle tests to take poison arg instead of undef
Commit: e04d7549cca3b82fb0f71d2b073fa88654ae2212
https://github.com/llvm/llvm-project/commit/e04d7549cca3b82fb0f71d2b073fa88654ae2212
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[llvm][docs] Link to correct maintainers file for clang-tools-extra
5eeb3fef61bf5542c3fdcb71622fc4e826527789 moved it from CODE_OWNERS.txt.
Commit: 59f57be94f38758616b1339b293b43af845571af
https://github.com/llvm/llvm-project/commit/59f57be94f38758616b1339b293b43af845571af
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
Revert "[libc++] Simplify the implementation of reserve() and shrink_to_fit() (#113453)"
This reverts commit d648eed5899c4be10f1f7866eebef2bc171e673f. Breaks
anything that relies on sized deallocation, e.g. asan and tcmalloc.
Commit: 55dd475d1d89db5cd23534a4d9b200854410703d
https://github.com/llvm/llvm-project/commit/55dd475d1d89db5cd23534a4d9b200854410703d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/mmx-cvt.ll
Log Message:
-----------
[X86] Fold (v2i64 (scalar_to_vector (i64 (bitcast (double))))) -> (bitcast (v2f64 scalar_to_vector))
This can occur more frequently after the MMX retirement if anyone is still using MMX intrinsics that now wrap to SSE
Commit: baaf1115ca007f95fd08c52dc8bec54d310f5b27
https://github.com/llvm/llvm-project/commit/baaf1115ca007f95fd08c52dc8bec54d310f5b27
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/unittests/ADT/BitmaskEnumTest.cpp
Log Message:
-----------
[BitmaskEnum] Add support for shift operators. (#118007)
For enums that describe a bitmask where successive bits within that mask
describe some enum value (as described in the same enum), it is useful
to support operator<< and operator>> as well.
For example:
```
enum class E : unsigned {
// 2 bits per option
OptionA = 0,
OptionB = 1,
OptionC = 2,
OptionD = 3,
OptionMask = 3,
// Given 3 values in the bitmask X, Y and Z, each is 2 bits in size
// and represents a choice of OptionA..OptionD.
ShiftX = 0,
ShiftY = 2,
ShiftZ = 4,
};
// The mask can be encoded with:
E mask;
mask |= getOptionFor(X) << E::ShiftX;
mask |= getOptionFor(Y) << E::ShiftY;
mask |= getOptionFor(Z) << E::ShiftZ;
// And to extract a value:
E OptionForX = (mask >> E::ShiftX) & E::OptionMask;
E OptionForY = (mask >> E::ShiftY) & E::OptionMask;
E OptionForZ = (mask >> E::ShiftZ) & E::OptionMask;
```
Commit: 9300274a12d758368c036812d903b73d70d64ea4
https://github.com/llvm/llvm-project/commit/9300274a12d758368c036812d903b73d70d64ea4
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/MC/RISCV/xqcicsr-invalid.s
M llvm/test/MC/RISCV/xqcicsr-valid.s
M llvm/test/MC/RISCV/xqcisls-invalid.s
M llvm/test/MC/RISCV/xqcisls-valid.s
Log Message:
-----------
[RISCV][NFCI] Fix Xqci Line Endings
Changes the new files for `Xqci`, including `Xqcicsr` and `Xqcisls`, to
use Unix line endings rather than Windows line endings.
Commit: bbea1dee28f4bd7cfa897a79e38c5331fca5d796
https://github.com/llvm/llvm-project/commit/bbea1dee28f4bd7cfa897a79e38c5331fca5d796
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
Log Message:
-----------
[X86][FP16] Fix masking problem of VF[,C]MADDCSH intrinsics (#118071)
Fixes: #98306
Commit: 6f4b4f41ca41d7d0b44a32d9968aef7667c68184
https://github.com/llvm/llvm-project/commit/6f4b4f41ca41d7d0b44a32d9968aef7667c68184
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
R llvm/test/Transforms/LoopVectorize/AArch64/scatter-cost.ll
Log Message:
-----------
[AArch64] Remove LoopVectorizer/AArch64/scatter-cost.ll test. NFC
This test checks the costs, not vectorization, so is better placed in the
existing gather/scatter cost modelling tests. An extra neoverse-v2 check line
has been added for both gathers and scatters.
Commit: f4974e09312afc9549fcfc0304b738d235da9eca
https://github.com/llvm/llvm-project/commit/f4974e09312afc9549fcfc0304b738d235da9eca
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/ashr-node-with-poison.ll
Log Message:
-----------
[SLP] Add a check for poison value in AShrChecker
Need to check if the value in AShrChecker is a poison before casting it
to instruction to avoid compiler crash
Fixes #118030
Commit: 2b3266c1701f315d7e89c81977800001563afacb
https://github.com/llvm/llvm-project/commit/2b3266c1701f315d7e89c81977800001563afacb
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
Log Message:
-----------
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11) (#116259)
SVE2.2 introduces instructions with predicated forms with zeroing of the
inactive lanes. This allows in some cases to save a `movprfx` or a `mov`
instruction when emitting code for `_x` or `_z` variants of intrinsics.
This patch adds support for emitting the zeroing forms of `ABS`, `NEG`,
`FABS`, and `FNEG` instructions.
Commit: e973f7ae52e753ebe53f5414ddf1c4d29e49deb5
https://github.com/llvm/llvm-project/commit/e973f7ae52e753ebe53f5414ddf1c4d29e49deb5
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV][Xqcicsr] Instructions have Side Effects (#118089)
Xqcicsr was added in #117169. I missed that `hasSideEffects` was set to
0, rather than 1 (which all other CSR-modifying instructions have).
This has no effect on the current assembly-only support, but I think is
worth fixing before I forget. I accidentally fixed the closing comment
in 9300274a12d758368c036812d903b73d70d64ea4.
Commit: ef86a31a593a023946a2dc805948360efdad3930
https://github.com/llvm/llvm-project/commit/ef86a31a593a023946a2dc805948360efdad3930
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/cmake/modules/GetHostTriple.cmake
Log Message:
-----------
[CMake] Fix mismatched endif warning
Caused by https://github.com/llvm/llvm-project/pull/116701.
Seems like a lot of arguments to repeat, so just use a plain endif().
Commit: 2a18162daa96e1cca5144a634bb03134405b52cb
https://github.com/llvm/llvm-project/commit/2a18162daa96e1cca5144a634bb03134405b52cb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
Log Message:
-----------
[X86] update shuffle lowering tests to take poison arg instead of undef
Commit: 5c181a9191bfb758575329ff7eb8db4fc46ffac9
https://github.com/llvm/llvm-project/commit/5c181a9191bfb758575329ff7eb8db4fc46ffac9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
Log Message:
-----------
[X86] update vector shift lowering tests to take poison arg instead of undef
Commit: 38098b486e44ad077b674e512eee399fc6f5a30c
https://github.com/llvm/llvm-project/commit/38098b486e44ad077b674e512eee399fc6f5a30c
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][vector] Disable CompressStoreOp/ExpandLoadOp for scalable vectors (#117538)
These operations were introduced as counterparts to the following LLVM
intrinsics:
* `@llvm.masked.expandload.*`,
* `@llvm.masked.compressstore.*`.
Currently, there is minimal test coverage for scalable vector use cases
involving these Ops (both LLVM and MLIR). Additionally, the verifier is
flawed - it incorrectly allows mixing fixed-width and scalable vectors.
To address these issues, scalable vector support for these Ops is being
disabled for now. This decision can be revisited if a clear need arises
for their use with scalable vectors in the future.
Commit: b40714b01206abef4130d3a39a90ac82aa96f18f
https://github.com/llvm/llvm-project/commit/b40714b01206abef4130d3a39a90ac82aa96f18f
Author: Tyler Nowicki <tyler.nowicki at amd.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A llvm/lib/Transforms/Coroutines/CoroCloner.h
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Log Message:
-----------
[Coroutines][NFC] Refactor CoroCloner (#116885)
* Move CoroCloner to its own header. For now, the header is located in llvm/lib/Transforms/Coroutines
* Change private to protected to allow inheritance
* Create CoroSwitchCloner and move some of the switch specific code into this cloner. More code will follow in later commits.
Commit: ef50d790c276600da609b465259a8e636e3531bc
https://github.com/llvm/llvm-project/commit/ef50d790c276600da609b465259a8e636e3531bc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M libcxx/utils/ci/run-buildbot-container
Log Message:
-----------
[libc++] Update run-buildbot-container with up-to-date image information
Commit: 31b7d4333a6c10aa8b7e1a7ca5aa0e281f124ec2
https://github.com/llvm/llvm-project/commit/31b7d4333a6c10aa8b7e1a7ca5aa0e281f124ec2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
M llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll
M llvm/test/CodeGen/X86/load-partial.ll
Log Message:
-----------
[DAG] Extend extract_element(bitcast(scalar_to_vector(X))) -> trunc(srl(X,C)) (#117900)
When extracting a smaller integer from a scalar_to_vector source, we were limited to only folding/truncating the lowest bits of the scalar source.
This patch extends the fold to handle extraction of any other element, by right shifting the source before truncation.
Fixes a regression from #117884
Commit: fe042904829b83a61c1f4bc904f8f9e5b6da891e
https://github.com/llvm/llvm-project/commit/fe042904829b83a61c1f4bc904f8f9e5b6da891e
Author: David Green <david.green at arm.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
Log Message:
-----------
[AArch64] Change the default vscale-for-tuning to 1. (#117174)
Most AArch64 cpus outside of Neoverse V1 (256) and A64FX (512) have an
SVE vector length of 128, and in environments like Android (where no
mcpu option is common) we would expect all cpus to match. This patch
changes the default vector length to 128 with -mcpu=generic, to match
the most common case.
Commit: 8fb748b4a7c45b56c2e4f37c327fd88958ab3758
https://github.com/llvm/llvm-project/commit/8fb748b4a7c45b56c2e4f37c327fd88958ab3758
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/InlineCost.h
M llvm/lib/Analysis/InlineCost.cpp
A llvm/test/Transforms/Inline/AArch64/memcpy-constant-size.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/memcpy-constant-size.ll
Log Message:
-----------
[Inliner] Don't count a call penalty for foldable __memcpy_chk and similar (#117876)
When the size is an appropriate constant, __memcpy_chk will turn into a
memcpy that gets folded away by InstCombine. Therefore this patch avoids
counting these as calls for purposes of inlining costs.
This is only really relevant on platforms whose headers redirect memcpy
to __memcpy_chk (such as Darwin). On platforms that use intrinsics,
memcpy and similar functions are already exempt from call penalties.
Commit: 77c2b005539c4b0c0e2b7edeefd5f57b95019bc9
https://github.com/llvm/llvm-project/commit/77c2b005539c4b0c0e2b7edeefd5f57b95019bc9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
A .ci/metrics/Dockerfile
A .ci/metrics/metrics.py
A .ci/metrics/requirements.lock.txt
A .ci/metrics/requirements.txt
Log Message:
-----------
[CI] Upstream metrics script and container definition (#117461)
This patch includes the script that pulls information from Github and
pushes it to Grafana. This is currently running in the cluster and
pushes information to
https://llvm.grafana.net/public-dashboards/6a1c1969b6794e0a8ee5d494c72ce2cd.
This script is designed to accept other jobs relatively easily and can
be easily modified to look at other metrics.
Commit: 122784f677f61c45a2c4e5db70d3e12cd2a7ee73
https://github.com/llvm/llvm-project/commit/122784f677f61c45a2c4e5db70d3e12cd2a7ee73
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-29 (Fri, 29 Nov 2024)
Changed paths:
M .ci/generate_test_report.py
M .ci/metrics/Dockerfile
M .ci/metrics/metrics.py
M .github/new-issues-labeler.yml
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/check-init-not-moved.s
M bolt/test/AArch64/data-at-0-offset.c
M bolt/test/AArch64/double_jump.cpp
M bolt/test/R_ABS.pic.lld.cpp
M bolt/test/X86/double-jump.test
M bolt/test/X86/dwarf5-df-inlined-subroutine-gc-sections-range.test
M bolt/test/X86/jmp-optimization.test
M bolt/test/X86/match-functions-with-call-graph.test
M bolt/test/pie.test
M bolt/test/runtime/X86/instrumentation-indirect.c
M bolt/test/runtime/bolt-reserved.cpp
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/utils/bughunter.sh
R clang-tools-extra/CODE_OWNERS.TXT
A clang-tools-extra/Maintainers.txt
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidConstOrRefDataMembersCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
A clang-tools-extra/test/clang-reorder-fields/FieldAnnotationsInMacros.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/avoid-const-or-ref-data-members.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
M clang/docs/ClangFormat.rst
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SanitizerCoverage.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConcepts.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/TemplateName.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Analysis/Consumed.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/FlowSensitive/Arena.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/IntervalPartition.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Flang.h
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/avx512vpopcntdqintrin.h
M clang/lib/Headers/avx512vpopcntdqvlintrin.h
M clang/lib/Headers/intrin.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/ChrootChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/AST/ByteCode/c23.c
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/AST/ByteCode/records.cpp
R clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RWBuffer-AST.hlsl
R clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
A clang/test/AST/HLSL/TypedBuffers-AST.hlsl
A clang/test/AST/ast-dump-cxx2b-deducing-this.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/AST/ast-print-packindexingexpr.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/chroot.c
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
M clang/test/Analysis/cxx-uninitialized-object-unguarded-access.cpp
M clang/test/Analysis/explain-svals.cpp
M clang/test/Analysis/iterator-modeling.cpp
M clang/test/Analysis/show-checker-list.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/stl-algorithm-modeling-aggressive-std-find-modeling.cpp
M clang/test/Analysis/stl-algorithm-modeling.cpp
M clang/test/Analysis/string.c
M clang/test/Analysis/string.cpp
A clang/test/Analysis/string_notnullterm.c
M clang/test/Analysis/template-param-objects.cpp
A clang/test/Analysis/void-call-exit-modelling.c
A clang/test/C/C23/n2412.c
M clang/test/CXX/temp/temp.deduct.guide/p3.cpp
A clang/test/CodeCompletion/keywords-cxx20.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
A clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c
M clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/attr-cpuspecific.c
M clang/test/CodeGen/bounds-checking.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-wasm.c
M clang/test/CodeGen/catch-undef-behavior.c
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
A clang/test/CodeGen/ubsan-trap-merge.c
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
A clang/test/CodeGenHLSL/resource-bindings.hlsl
A clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/Driver/cl-options.c
M clang/test/Driver/cuda-no-threadsafe-statics.cu
M clang/test/Driver/fveclib.c
M clang/test/Driver/hexagon-toolchain-linux.c
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mdiv32.c
A clang/test/Driver/loongarch-mlamcas.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
M clang/test/OpenMP/flush_ast_print.cpp
M clang/test/OpenMP/flush_codegen.cpp
M clang/test/OpenMP/flush_messages.cpp
A clang/test/OpenMP/taskloop_strictmodifier_codegen.cpp
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/riscv-target-features.c
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_cvt.c
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
A clang/test/Sema/attr-target-version-unsupported.c
M clang/test/Sema/builtin-counted-by-ref.c
M clang/test/Sema/constant_builtins_vector.cpp
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
A clang/test/SemaCXX/attr-no-specializations.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
A clang/test/SemaCXX/cxx20-warn-dangling-paren-list-agg-init.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
M clang/test/SemaCXX/literal-type.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
M clang/test/SemaCXX/warn-memaccess.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
M clang/test/SemaCXX/warn-unused-private-field.cpp
A clang/test/SemaHIP/zero-sized-device-array.hip
A clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/invalid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/combined-construct-no_create-clause.c
A clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
A clang/test/SemaOpenACC/combined-construct-present-ast.cpp
A clang/test/SemaOpenACC/combined-construct-present-clause.c
A clang/test/SemaOpenACC/combined-construct-present-clause.cpp
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
M clang/test/SemaOpenACC/compute-construct-varlist-ast.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
A clang/test/SemaOpenCL/builtins-amdgcn-wave32-func-attr.cl
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-format/git-clang-format
M clang/tools/clang-repl/ClangRepl.cpp
M clang/tools/clang-shlib/CMakeLists.txt
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/interception_win.h
M compiler-rt/lib/interception/tests/interception_win_test.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_deadlock_detector.h
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
M compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
M compiler-rt/lib/xray/weak_symbols.txt
M compiler-rt/lib/xray/xray_flags.cpp
M compiler-rt/lib/xray/xray_flags.h
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
M compiler-rt/test/builtins/Unit/fp_test.h
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
M compiler-rt/test/profile/Linux/binary-id-offset.c
A compiler-rt/test/tsan/many_held_mutex.cpp
A compiler-rt/test/xray/TestCases/Posix/default-options.cpp
M flang/docs/Intrinsics.md
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
A flang/include/flang/Common/OpenMP-utils.h
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Runtime/CUDA/allocatable.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Common/CMakeLists.txt
A flang/lib/Common/OpenMP-utils.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/GenericLoopConversion.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/runtime/CUDA/allocatable.cpp
A flang/test/Analysis/AliasAnalysis/gen_mod_ref_test.py
A flang/test/Analysis/AliasAnalysis/modref-call-after-inlining.fir
A flang/test/Analysis/AliasAnalysis/modref-call-args.f90
A flang/test/Analysis/AliasAnalysis/modref-call-dummies.f90
A flang/test/Analysis/AliasAnalysis/modref-call-equivalence.f90
A flang/test/Analysis/AliasAnalysis/modref-call-globals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-internal-proc.f90
A flang/test/Analysis/AliasAnalysis/modref-call-locals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-not-fortran.fir
A flang/test/Driver/mabi-loongarch.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Driver/print-supported-cpus.f90
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/arrayset.fir
M flang/test/Fir/arrexp.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/box-offset-codegen.fir
M flang/test/Fir/box.fir
M flang/test/Fir/boxproc.fir
M flang/test/Fir/commute.fir
M flang/test/Fir/coordinateof.fir
M flang/test/Fir/embox.fir
M flang/test/Fir/field-index.fir
M flang/test/Fir/ignore-missing-type-descriptor.fir
M flang/test/Fir/polymorphic.fir
A flang/test/Fir/struct-passing-loongarch64-byreg.fir
A flang/test/Fir/struct-passing-return-loongarch64-bystack.fir
M flang/test/Fir/struct-passing-x86-64-byval.fir
A flang/test/Fir/struct-return-aarch64.fir
A flang/test/Fir/struct-return-loongarch64-byreg.fir
M flang/test/Fir/target-rewrite-complex-10-x86.fir
M flang/test/Fir/target.fir
M flang/test/Integration/OpenMP/copyprivate.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/HLFIR/assumed-rank-internal-proc.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/HLFIR/goto-do-body.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/Intrinsics/len_trim.f90
M flang/test/Lower/Intrinsics/system.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
A flang/test/Lower/OpenMP/Todo/flush-seq-cst.f90
M flang/test/Lower/OpenMP/Todo/map-mapper.f90
R flang/test/Lower/OpenMP/Todo/task_mergeable.f90
M flang/test/Lower/OpenMP/copyprivate.f90
M flang/test/Lower/OpenMP/copyprivate2.f90
A flang/test/Lower/OpenMP/declare-target-interface.f90
A flang/test/Lower/OpenMP/generic-loop-rewriting.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
M flang/test/Lower/goto-do-body.f90
M flang/test/Lower/nsw.f90
A flang/test/Parser/OpenMP/bind-clause.f90
M flang/test/Parser/OpenMP/from-clause.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
M flang/test/Parser/OpenMP/target-update-to-clause.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/combined-constructs.f90
A flang/test/Semantics/OpenMP/critical_within_default.f90
M flang/test/Semantics/OpenMP/defaultmap-clause-v45.f90
M flang/test/Semantics/OpenMP/flush02.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/map-clause.f90
M flang/test/Semantics/OpenMP/map-modifiers.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
M flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
A flang/test/Transforms/OpenMP/lower-workshare-nested.mlir
M flang/test/Transforms/constant-argument-globalisation.fir
A flang/test/Transforms/function-attrs.fir
A flang/test/Transforms/generic-loop-rewriting-todo.mlir
A flang/test/Transforms/generic-loop-rewriting.mlir
M flang/unittests/Runtime/CMakeLists.txt
M flang/unittests/Runtime/CommandTest.cpp
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/shared/rpc.h
A libc/shared/rpc_opcodes.h
M libc/shared/rpc_util.h
M libc/spec/linux.td
M libc/src/__support/RPC/rpc_client.cpp
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/common.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/complex/generic/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/pthread/CMakeLists.txt
M libc/src/setjmp/riscv/CMakeLists.txt
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/stdfix/CMakeLists.txt
M libc/src/string/CMakeLists.txt
M libc/src/string/memory_utils/op_x86.h
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/src/threads/CMakeLists.txt
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M libc/utils/gpu/server/CMakeLists.txt
R libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
A libcxx/docs/CodingGuidelines.rst
M libcxx/docs/Contributing.rst
M libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
R libcxx/docs/DesignDocs/NodiscardPolicy.rst
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/index.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__chrono/duration.h
M libcxx/include/__config
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__split_buffer
A libcxx/include/__type_traits/detected_or.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/latch
M libcxx/include/locale
M libcxx/include/module.modulemap
M libcxx/include/semaphore
M libcxx/lib/abi/CHANGELOG.TXT
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/CMakeLists.txt
R libcxx/src/legacy_pointer_safety.cpp
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/GenerateInput.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
M libcxx/test/std/containers/sequences/vector.bool/ctor_exceptions.pass.cpp
A libcxx/test/std/containers/sequences/vector/addressof.compile.pass.cpp
A libcxx/test/std/containers/sequences/vector/common.h
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_copy.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_move.addressof.compile.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/exceptions.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_size_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.special/swap.addressof.compile.pass.cpp
M libcxx/utils/ci/run-buildbot-container
M lld/COFF/Config.h
M lld/COFF/SymbolTable.cpp
M lld/Common/ErrorHandler.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LinkerScript.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
M lld/include/lld/Common/ErrorHandler.h
M lld/test/COFF/arm64ec.test
A lld/test/ELF/arm-rwpi-debug-relocs.s
M lld/test/ELF/incompatible.s
M lld/test/ELF/invalid/x86-64-tlsdesc-gd.s
M lld/test/ELF/linkerscript/symbol-location.s
M lld/test/ELF/pack-dyn-relocs-tls-x86-64.s
M lld/test/ELF/reproduce.s
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
M lld/test/ELF/x86-64-tlsdesc-gd.s
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/use/aarch64-linux.md
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Host/common/TCPSocket.h
M lldb/include/lldb/Host/common/UDPSocket.h
M lldb/include/lldb/Host/linux/AbstractSocket.h
M lldb/include/lldb/Host/posix/DomainSocket.h
M lldb/include/lldb/Symbol/Block.h
M lldb/include/lldb/Target/Process.h
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/common/TCPSocket.cpp
M lldb/source/Host/common/UDPSocket.cpp
M lldb/source/Host/linux/AbstractSocket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/posix/DomainSocket.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/debugserver/RNBSocketTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/AddLLVM.cmake
M llvm/cmake/modules/GetHostTriple.cmake
M llvm/docs/DirectX/DXILResources.rst
M llvm/docs/GitHub.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/XRay.rst
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/include/llvm/Analysis/InlineCost.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
A llvm/include/llvm/CodeGen/SpillPlacement.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
A llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
M llvm/include/llvm/ExecutionEngine/Orc/IndirectionUtils.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Metadata.h
A llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/VFABIDemangler.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/Object/ELF.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/Support/Error.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/include/llvm/Transforms/IPO/MergeFunctions.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/Bitstream/Reader/BitstreamReader.cpp
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/lib/CodeGen/IntrinsicLowering.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocGreedy.h
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
M llvm/lib/CodeGen/SpillPlacement.cpp
R llvm/lib/CodeGen/SpillPlacement.h
M llvm/lib/DebugInfo/GSYM/CMakeLists.txt
A llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
M llvm/lib/DebugInfo/Symbolize/Symbolize.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/VFABIDemangler.cpp
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/GOFFObjectFile.cpp
M llvm/lib/Object/MachOObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Object/XCOFFObjectFile.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Support/Compression.cpp
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
A llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
A llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/Target/X86/X86WinEHState.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/lib/Transforms/Coroutines/CoroCloner.h
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Analysis/CostModel/AArch64/extract_float_streaming.ll
M llvm/test/Analysis/CostModel/AArch64/sve-gather.ll
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/abs.ll
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/fptoi_sat.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-codesize.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-latency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat-sizelatency.ll
A llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
M llvm/test/Analysis/MemorySSA/loop-unswitch.ll
M llvm/test/Analysis/MemorySSA/pr40037.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr46574.ll
M llvm/test/Analysis/MemorySSA/simple_loop_unswitch_nontrivial.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/Bitcode/Inputs/invalid-initializer.bc
M llvm/test/Bitcode/invalid.test
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-frame-tail.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
A llvm/test/CodeGen/AArch64/cgdata-merge-crash.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-local.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-no-params.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/init-undef.mir
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/selectopt.ll
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
A llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
A llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
A llvm/test/CodeGen/AMDGPU/bitop3.ll
A llvm/test/CodeGen/AMDGPU/coalescer-undef-subreg-use-invalid-lanemask.mir
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.mir
M llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions-obj-test.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/doubles.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/no_flags.ll
A llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
R llvm/test/CodeGen/DirectX/updateCounter.ll
A llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
R llvm/test/CodeGen/Generic/cgdata-merge-crash.ll
A llvm/test/CodeGen/Generic/sjlj-eh-prepare.ll
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
A llvm/test/CodeGen/NVPTX/div.ll
A llvm/test/CodeGen/PowerPC/frameindex-negative-offset.ll
M llvm/test/CodeGen/PowerPC/gcov_ctr_ref_init.ll
M llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
M llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll
A llvm/test/CodeGen/PowerPC/ssubo-32.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
A llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
M llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
A llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
A llvm/test/CodeGen/RISCV/rvv/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
A llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll
M llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll
M llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll
M llvm/test/CodeGen/SPIRV/branching/if-merging.ll
M llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll
M llvm/test/CodeGen/SPIRV/instructions/ret-type.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/scmp.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/ucmp.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll
M llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/cf.while.short-circuited-cond.ll
M llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll
M llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll
M llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll
M llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll
M llvm/test/CodeGen/SPIRV/structurizer/merge-exit-simple-while-identity.ll
M llvm/test/CodeGen/SPIRV/structurizer/return-early.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
A llvm/test/CodeGen/Thumb/returnaddress.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
A llvm/test/CodeGen/WebAssembly/thread_pointer.ll
A llvm/test/CodeGen/WinEH/wineh-scope-statenumbering.ll
A llvm/test/CodeGen/X86/apx/imulzu.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
A llvm/test/CodeGen/X86/extract-vselect-setcc.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
A llvm/test/CodeGen/X86/gfni-lzcnt.ll
A llvm/test/CodeGen/X86/gfni-tzcnt.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll
M llvm/test/CodeGen/X86/load-partial.ll
M llvm/test/CodeGen/X86/mmx-cvt.ll
A llvm/test/CodeGen/X86/pr114360.ll
M llvm/test/CodeGen/X86/pr114520.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/sjlj-eh.ll
A llvm/test/CodeGen/X86/ubsan-trap-merge.ll
A llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
M llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-masked.ll
M llvm/test/CodeGen/X86/widen_shuffle-1.ll
M llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
M llvm/test/MC/AArch64/local-bounds-single-trap.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx950_dlops.s
M llvm/test/MC/AMDGPU/gfx950_err.s
A llvm/test/MC/AMDGPU/gfx950_xdlops.s
M llvm/test/MC/AMDGPU/mai-gfx950-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_xdlops.txt
M llvm/test/MC/ELF/relocation.s
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/xqcicsr-invalid.s
A llvm/test/MC/RISCV/xqcicsr-valid.s
A llvm/test/MC/RISCV/xqcisls-invalid.s
A llvm/test/MC/RISCV/xqcisls-valid.s
A llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
A llvm/test/Transforms/AtomicExpand/LoongArch/atomicrmw-expand.ll
M llvm/test/Transforms/ConstraintElimination/and-implied-by-operands.ll
M llvm/test/Transforms/ConstraintElimination/or.ll
M llvm/test/Transforms/DeadStoreElimination/offsetted-overlapping-stores.ll
M llvm/test/Transforms/DeadStoreElimination/stores-of-existing-values.ll
A llvm/test/Transforms/EarlyCSE/noalias-addrspace.ll
M llvm/test/Transforms/GVN/noalias.ll
A llvm/test/Transforms/GVN/setjmp.ll
A llvm/test/Transforms/Inline/AArch64/memcpy-constant-size.ll
A llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll
A llvm/test/Transforms/Inline/LoongArch/lit.local.cfg
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
M llvm/test/Transforms/InstCombine/fptrunc.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
A llvm/test/Transforms/InstSimplify/icmp-monotonic.ll
M llvm/test/Transforms/JumpThreading/thread-loads.ll
M llvm/test/Transforms/LICM/hoist-metadata.ll
M llvm/test/Transforms/LICM/hoisting-preheader-debugloc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
R llvm/test/Transforms/LoopVectorize/AArch64/scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
A llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/pr47665.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-interleaved-accesses-gap.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
M llvm/test/Transforms/LoopVectorize/select-reduction.ll
M llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-alloca-in-loop.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
A llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int-also-fusable-multiply.ll
M llvm/test/Transforms/MemCpyOpt/aa-recursion-assertion-failure.ll
M llvm/test/Transforms/MergedLoadStoreMotion/st_sink_debuginvariant.ll
M llvm/test/Transforms/NewGVN/2010-03-31-RedundantPHIs.ll
M llvm/test/Transforms/NewGVN/2010-05-08-OneBit.ll
M llvm/test/Transforms/NewGVN/2011-04-27-phioperands.ll
M llvm/test/Transforms/NewGVN/2012-05-22-PreCrash.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/completeness.ll
M llvm/test/Transforms/NewGVN/crash.ll
M llvm/test/Transforms/NewGVN/deadstore.ll
M llvm/test/Transforms/NewGVN/eliminate-ssacopy.ll
M llvm/test/Transforms/NewGVN/metadata-nonnull.ll
M llvm/test/Transforms/NewGVN/noalias.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-move-block.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
M llvm/test/Transforms/NewGVN/pr25440.ll
M llvm/test/Transforms/NewGVN/pr31594.ll
M llvm/test/Transforms/NewGVN/pr31613.ll
M llvm/test/Transforms/NewGVN/pr31682.ll
M llvm/test/Transforms/NewGVN/pr32403.ll
M llvm/test/Transforms/NewGVN/pr32838.ll
M llvm/test/Transforms/NewGVN/pr32845.ll
M llvm/test/Transforms/NewGVN/pr32897.ll
M llvm/test/Transforms/NewGVN/pr32934.ll
M llvm/test/Transforms/NewGVN/pr33014.ll
M llvm/test/Transforms/NewGVN/pr33086.ll
M llvm/test/Transforms/NewGVN/pr33116.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33204.ll
M llvm/test/Transforms/NewGVN/pr33432.ll
M llvm/test/Transforms/NewGVN/pr33720.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr35074.ll
M llvm/test/Transforms/NewGVN/pr42422-phi-of-ops.ll
M llvm/test/Transforms/NewGVN/pr43441.ll
M llvm/test/Transforms/NewGVN/pre-new-inst-xfail.ll
M llvm/test/Transforms/NewGVN/predicates.ll
M llvm/test/Transforms/NewGVN/refine-stores.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
M llvm/test/Transforms/OpenMP/keep_rpc_client.ll
M llvm/test/Transforms/OpenMP/remove_rpc_client.ll
A llvm/test/Transforms/PhaseOrdering/AArch64/memcpy-constant-size.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-117393.ll
A llvm/test/Transforms/SLPVectorizer/X86/ashr-node-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-13-SingleEntryPHI.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-27-DeadSwitchCase.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-Unreachable.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-tl.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-12-ExitDomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-13-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-18-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2008-06-02-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2010-11-18-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-06-02-CritSwitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-09-26-EHCrash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-04-02-IndirectBr.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-05-20-Phi.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2015-09-18-Addrspace.ll
M llvm/test/Transforms/SimpleLoopUnswitch/LIV-loop-condtion.ll
M llvm/test/Transforms/SimpleLoopUnswitch/cleanuppad.ll
M llvm/test/Transforms/SimpleLoopUnswitch/copy-metadata.ll
M llvm/test/Transforms/SimpleLoopUnswitch/crash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-behavior.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-cost.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-skip-selects-in-guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
A llvm/test/Transforms/SimpleLoopUnswitch/pr117537.ll
M llvm/test/Transforms/SimpleLoopUnswitch/preserve-analyses.ll
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
M llvm/test/Transforms/SimplifyCFG/switch-branch-fold-indirectbr-102351.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-string.test
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/DW_AT_GNU_template_name.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/DW_AT_GNU_template_name.ll
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-dsym.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-exe.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-obj.test
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-adx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-aes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalgvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cd.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cdvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifmavl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaesvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-fma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lea.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x87.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/zero-idioms.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/barrier_output.s
A llvm/test/tools/llvm-objcopy/MachO/dysymtab-zero-indirectsym.test
A llvm/test/tools/llvm-reduce/distinct-dimetadata-nullptr.ll
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
M llvm/unittests/ADT/BitmaskEnumTest.cpp
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
M llvm/unittests/AsmParser/AsmParserTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
M llvm/unittests/DebugInfo/LogicalView/CMakeLists.txt
A llvm/unittests/DebugInfo/LogicalView/DWARFGeneratedTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVPartialOrderingVisitorTests.cpp
A llvm/unittests/Target/SPIRV/SPIRVSortBlocksTests.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/IPO/CMakeLists.txt
A llvm/unittests/Transforms/IPO/MergeFunctionsTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/GSYM/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/IPO/BUILD.gn
M mlir/CMakeLists.txt
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
M mlir/docs/Bufferization.md
M mlir/docs/DialectConversion.md
M mlir/docs/PatternRewriter.md
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h
A mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.td
A mlir/include/mlir/Conversion/GPUCommon/GPUToLLVM.h
A mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVM.h
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
A mlir/include/mlir/Conversion/MeshToMPI/MeshToMPI.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/AffineMap.h
M mlir/include/mlir/IR/AttrTypeBase.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Matchers.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/include/mlir/Interfaces/TilingInterface.td
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/CMakeLists.txt
M mlir/lib/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/GPUToLLVMSPV/CMakeLists.txt
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
A mlir/lib/Conversion/MeshToMPI/CMakeLists.txt
A mlir/lib/Conversion/MeshToMPI/MeshToMPI.cpp
M mlir/lib/Conversion/TensorToLinalg/TensorToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MPI/IR/CMakeLists.txt
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/TypeUtilities.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/__init__.py
M mlir/test/CAPI/ir.c
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-target-attr.mlir
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
A mlir/test/Conversion/MeshToMPI/convert-mesh-to-mpi.mlir
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Arith/bufferize.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-analysis.mlir
A mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-partial.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-force-copy-before-write.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/Bufferization/ops.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
M mlir/test/Dialect/GPU/barrier-elimination.mlir
M mlir/test/Dialect/Linalg/bufferize.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
A mlir/test/Dialect/Linalg/decompose-pad-tensor.mlir
M mlir/test/Dialect/Linalg/fusion-elementwise.mlir
R mlir/test/Dialect/Linalg/generalize-pad-tensor.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/MemRef/normalize-memrefs.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SCF/bufferize.mlir
A mlir/test/Dialect/SCF/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/Dialect/Shape/bufferize.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul24_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matvec_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sampled_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sddmm_lib.mlir
M mlir/test/Dialect/SparseTensor/constant_index_map.mlir
M mlir/test/Dialect/SparseTensor/dense.mlir
M mlir/test/Dialect/SparseTensor/fuse_sparse_pad_with_consumer.mlir
M mlir/test/Dialect/SparseTensor/sorted_coo.mlir
M mlir/test/Dialect/SparseTensor/sparse_1d.mlir
M mlir/test/Dialect/SparseTensor/sparse_2d.mlir
M mlir/test/Dialect/SparseTensor/sparse_3d.mlir
M mlir/test/Dialect/SparseTensor/sparse_affine.mlir
M mlir/test/Dialect/SparseTensor/sparse_batch.mlir
M mlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_fusion.mlir
M mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels_to_iterator.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
M mlir/test/Dialect/SparseTensor/sparse_nd.mlir
M mlir/test/Dialect/SparseTensor/sparse_outbuf.mlir
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
M mlir/test/Dialect/SparseTensor/sparse_parallel_reduce.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_scalars.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm_org.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_index.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
M mlir/test/Dialect/SparseTensor/unused-tensor.mlir
M mlir/test/Dialect/SparseTensor/vectorize_reduction.mlir
M mlir/test/Dialect/Tensor/bufferize.mlir
A mlir/test/Dialect/Tensor/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/bufferize.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/IR/properties.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
M mlir/test/Integration/Dialect/Tosa/CPU/test-maxpool-dynamic.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/mulf-full.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/muli-full.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/intel-ext-ops.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/tools/mlir-tblgen/BytecodeDialectGen.cpp
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/unittests/IR/AffineMapTest.cpp
M offload/CMakeLists.txt
M offload/DeviceRTL/src/Mapping.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/test/offloading/ompx_bare_ballot_sync.c
M offload/test/offloading/ompx_bare_shfl_down_sync.cpp
M runtimes/CMakeLists.txt
M runtimes/cmake/Modules/FindLibcCommonUtils.cmake
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/boomanaiden154/build-metrics-container
Compare: https://github.com/llvm/llvm-project/compare/0522707ac068...122784f677f6
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