[all-commits] [llvm/llvm-project] 2b3266: [AArch64] Generate zeroing forms of certain SVE2.2...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b3266c1701f315d7e89c81977800001563afacb
      https://github.com/llvm/llvm-project/commit/2b3266c1701f315d7e89c81977800001563afacb
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2024-11-29 (Fri, 29 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll

  Log Message:
  -----------
  [AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11) (#116259)

SVE2.2 introduces instructions with predicated forms with zeroing of the
inactive lanes. This allows in some cases to save a `movprfx` or a `mov`
instruction when emitting code for `_x` or `_z` variants of intrinsics.

This patch adds support for emitting the zeroing forms of `ABS`, `NEG`,
`FABS`, and `FNEG` instructions.



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