[all-commits] [llvm/llvm-project] 01a15d: [RISCV] Set a barrier between mask producer and us...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
      https://github.com/llvm/llvm-project/commit/01a15dca09e56dce850ab6fb3ecddfb3f8c6c172
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-29 (Fri, 29 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.h
    A llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne.ll

  Log Message:
  -----------
  [RISCV] Set a barrier between mask producer and user of V0 (#114012)

Here we add a scheduling mutation in pre-ra scheduling, which will
add an artificial dependency edge between mask producer and its
previous nearest instruction that uses V0 register.

This prevents the overlap of live intervals of mask registers and
as a consequence we can reduce some spills/moves.

>From the test changes, we can see some improvements and also some
regressions (more vtype toggles).

Partially fixes #113489.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications