[all-commits] [llvm/llvm-project] 18abc7: [PatternMatch] Introduce m_c_Select (#114328)
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Wed Nov 27 11:51:58 PST 2024
Branch: refs/heads/users/kparzysz/spr/m10-grainsize
Home: https://github.com/llvm/llvm-project
Commit: 18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
https://github.com/llvm/llvm-project/commit/18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Log Message:
-----------
[PatternMatch] Introduce m_c_Select (#114328)
This matches m_Select(m_Value(), L, R) or m_Select(m_Value(), R, L).
Commit: 9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
https://github.com/llvm/llvm-project/commit/9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
R llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
Revert "[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)" (#117556)
This reverts commit 22ec44f509ff266b581dbb490d7b040473b7c31a.
Commit: 6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
https://github.com/llvm/llvm-project/commit/6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/c23.c
Log Message:
-----------
[clang][bytecode] Use bitcasts to cast from integer to vector (#117547)
In C, a cast from an integer to a vector is a CK_BitCast. Implement this
using the same code we use for __builtin_bit_cast.
Commit: 2d62daab497bfe1991869dc090c7d20a71108360
https://github.com/llvm/llvm-project/commit/2d62daab497bfe1991869dc090c7d20a71108360
Author: David Truby <david.truby at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Fir/struct-return-aarch64.fir
Log Message:
-----------
[flang] AArch64 support for BIND(C) derived return types (#114051)
This patch adds support for BIND(C) derived types as return values
matching the AArch64 Procedure Call Standard for C.
Support for BIND(C) derived types as value parameters will be in a
separate patch.
Commit: 809c5ac3b0d78f504d93717ac4c0a02816cf47bb
https://github.com/llvm/llvm-project/commit/809c5ac3b0d78f504d93717ac4c0a02816cf47bb
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
[X86] Modify tests for constrained rounding functions (#116951)
The existing tests for constrained functions often use constant
arguments. If constant evaluation is enhanced, such tests will not check
code generation of the tested functions. To avoid it, the tests are
modified to use loaded value instead of constants. Now only the tests
for rounding functions are changed.
Commit: 06cb5c9d2c24e7560fcafd911fb145b96e96a675
https://github.com/llvm/llvm-project/commit/06cb5c9d2c24e7560fcafd911fb145b96e96a675
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update ARM maintainers (#117002)
Move rengolin and asl to former maintainers, and add davemgreen,
ostannard, nasherm, smithp35 and stuji from ARM as current
maintainers (with a focus area for some).
Commit: 4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
https://github.com/llvm/llvm-project/commit/4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
Revert "[SelectOpt] Refactor to prepare for support more select-like operations (#115745)"
This reverts commit b5a11d378db4b39ceb085ebd59c941e9369d9596.
Commit: a5506a39e0ae8de77136334659b526e5f224850d
https://github.com/llvm/llvm-project/commit/a5506a39e0ae8de77136334659b526e5f224850d
Author: Yadong Chen <cyd.matt at qq.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp assembly (#116943)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.
Changes:
updates the PtrAccessChainOp and InBoundPtrAccessChainOp defined in
SPIRVMemoryOps.td to use assemblyFormat. Removes part print/parse from
MemoryOps.cpp which is now generated by assemblyFormat
Updates tests to updated format
Issue: #73359
Commit: 6de97e9a679aaf3148d467e4d4e1ea99ba55d555
https://github.com/llvm/llvm-project/commit/6de97e9a679aaf3148d467e4d4e1ea99ba55d555
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/cmake/modules/prepare_libc_gpu_build.cmake
Log Message:
-----------
[libc] Allow NVPTX targets to build in debug mode
Summary:
This previously did not work, but recent improvements to the NVPTX
backend allow this to work now.
Commit: 387be04dde0a2618d2baf37a4652a076c003b4a2
https://github.com/llvm/llvm-project/commit/387be04dde0a2618d2baf37a4652a076c003b4a2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc.h
Log Message:
-----------
[libc][NFC] Add const to RPC header members
Summary:
Make sure that these don't get modified.
Commit: 7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
https://github.com/llvm/llvm-project/commit/7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
Author: thetruestblue <bblueconway at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/SanitizerCoverage.rst
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[SanitizerCoverage] Add gated tracing callbacks support to trace-cmp (#113227)
The option -sanitizer-coverage-gated-trace-callbacks gates the
invocation of the trace-pc-guard callbacks based on the value of a
global variable, which is stored in a specific section.
In this commit, we extend this feature to trace-cmp and gate the cmp
callbacks to the same variable used for trace-pc-guard.
Update SanitizerCoverage doc with this flag.
rdar://135404160
Patch by: Andrea Fioraldi
Commit: f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
https://github.com/llvm/llvm-project/commit/f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
Log Message:
-----------
[ADT] Add convenience function `filter_to_vector` (#117460)
This materializes a filter range as a small vector.
Similar to `map_to_vector`, this new utility function lives in the
`SmallVectorExtras.h` header.
Commit: 7e3187e12a2cef8b2552e08ce9423aca9c09d813
https://github.com/llvm/llvm-project/commit/7e3187e12a2cef8b2552e08ce9423aca9c09d813
Author: ddubov100 <155631080+ddubov100 at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Interfaces/TilingInterface.td
Log Message:
-----------
Adding mlir prefix for missing places in TilingInterface.td (#117495)
Commit: 57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
https://github.com/llvm/llvm-project/commit/57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
Log Message:
-----------
[SLP]Relax assertion in mask combine for non-power-of-2 number of elements
The nodes may contain non-power-of-2 number of elements. Need to relax
the assertion to avoid possible compiler crash
Fixes #117517
Commit: 1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
https://github.com/llvm/llvm-project/commit/1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
Log Message:
-----------
[X86] vector-interleaved-load-i16-stride-2.ll - regenerate with AVX512 common prefix
Commit: 4d8eb009d8ae4500940d77a64d914eed9a13b92c
https://github.com/llvm/llvm-project/commit/4d8eb009d8ae4500940d77a64d914eed9a13b92c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Remove SPF guard for trunc transforms (#117535)
This shouldn't be necessary anymore now that SPF patterns are
canonicalized to intrinsics.
Commit: 3de21477c49172081e502b47d608e729915f0914
https://github.com/llvm/llvm-project/commit/3de21477c49172081e502b47d608e729915f0914
Author: Viktoriia Bakalova <115406782+VitaNuo at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[clang][codegen] Mention the invariant that LLVM demangler should be … (#117346)
…able to handle mangled names generated by clang.
https://discourse.llvm.org/t/rfc-clang-diagnostic-for-demangling-failures/82835/8
Since we're putting the work on the above RFC on hold, let's leave a
comment in the source code pointing to prior efforts and the suggestion
of further steps.
Commit: f953b5eb72df77fc301aac210eab31c6270ff771
https://github.com/llvm/llvm-project/commit/f953b5eb72df77fc301aac210eab31c6270ff771
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
Log Message:
-----------
[SLP]Relax assertion about subvectors mask size
SubVectorsMask might be less than CommonMask, if the vectors with larger
number of elements are permuted or reused elements are used. Need to
consider this when estimation/building the vector to avoid compiler
crash
Fixes #117518
Commit: b872c4c9939999d8c588ca4e149e2b0b40773ebf
https://github.com/llvm/llvm-project/commit/b872c4c9939999d8c588ca4e149e2b0b40773ebf
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/test/Driver/print-supported-cpus.f90
Log Message:
-----------
[flang][Driver] Fix incorrect condition in test
The conditions in a test did not match the target that was being
requested. This resulted in a test failure when building with
-DTARGETS_TO_BUILD=X86. This is now fixed.
Commit: c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
https://github.com/llvm/llvm-project/commit/c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir] Improve doc in `OpFormatGen.cpp` (NFC) (#117564)
The comment is misleading because attributes do not have
`elidePrintingDefaultValue` bit. It appears that
`elidePrintingDefaultValue` was never merged upstream (see:
https://reviews.llvm.org/D135398 ), but the comment was likely
introduced by mistake in a later revision
(https://reviews.llvm.org/D135993.).
Commit: 99fd1c5536547ed4fc360b16e7fa2e06278707a8
https://github.com/llvm/llvm-project/commit/99fd1c5536547ed4fc360b16e7fa2e06278707a8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libcxx/include/__chrono/duration.h
Log Message:
-----------
[libc++][NFC] Don't add legacy transitive includes in <__chrono/duration.h>
Commit: 20bd029a40faa2ae5383dd742b8a3595b1fe7c31
https://github.com/llvm/llvm-project/commit/20bd029a40faa2ae5383dd742b8a3595b1fe7c31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote fldexp with Zfh. (#117396)
The default expansion tries to create i16 operations after type
legalization.
Fixes #117349
Commit: 3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
https://github.com/llvm/llvm-project/commit/3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)
The 2-pass XDL write VGPR, read by non-XDL SGEMM/DGEMM case
was 1 wait state overly conservative. Previously, for gfx940,
the XDL/non-XDL cases happened to have the same number of cycles
in all cases. Now the XDL consumer case has an additional state for
2 pass sources.
Commit: c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
https://github.com/llvm/llvm-project/commit/c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
Log Message:
-----------
AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)
Confusingly, this is a different hazard to the one on gfx10
with a subtarget feature.
Commit: 27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
https://github.com/llvm/llvm-project/commit/27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
Log Message:
-----------
AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)
Commit: 8a2311c4bf9993230e37dc20b57973dc917f2338
https://github.com/llvm/llvm-project/commit/8a2311c4bf9993230e37dc20b57973dc917f2338
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
[Offload] Introduce offload-tblgen and initial new API implementation (#108413)
Introduce `offload-tblgen` and an initial implementation of a subset of
the new API. The tablegen files are intended to be the single source of
truth for the new API, with the header files, documentation, and others
bits of source all automatically generated.
**TODO** (based on review feedback so far):
- [x] Check in the generated headers
- [x] Add an `offload-generate` target to trigger the generation rather
than building them every time
- [x] Decide how error handling should work
- [x] Finish up new error handling implementation
- [x] Decide naming convention
- [x] Add testing for the new API
- [x] Add tablegen specific testing
- [x] clang-tidy and use llvm:: types when possible
- [x] Add optional code location arguments
- [x] Avoid multiple returns from one function
### offload-tblgen
See the included
[README](https://github.com/callumfare/llvm-project/blob/d80db06491d85444bb6f7e59d8068a22cef3a6b4/offload/new-api/API/README.md)
for more information on how the API definition and generation works. I'm
happy to answer any questions about it and plan to walk through it in a
future LLVM Offload call.
It should be noted that struct definitions have not been fully
implemented/tested as they aren't used by the initial API definitions,
but finishing that off in the future shouldn't be too much work.
The tablegen tooling has been designed to be easily extended with new
backends, using the classes in `RecordTypes.hpp` to abstract over the
tablegen records.
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
$ git clone -b offload_adapter https://github.com/callumfare/unified-runtime.git
$ cd unified-runtime
$ mkdir build
$ cd build
$ cmake .. -GNinja -DUR_BUILD_ADAPTER_OFFLOAD=ON \
-DUR_OFFLOAD_INSTALL_DIR=<offload build dir containing liboffload_new.so> \
-DUR_OFFLOAD_INCLUDE_DIR=<offload build dir containing 'offload' headers directory>
$ ninja urinfo
export LD_LIBRARY_PATH=<offload build dir containing offload plugin libraries>
$ UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
[cuda:gpu][cuda:0] CUDA, NVIDIA GeForce GT 1030 [12030]
# Demo with tracing
$ OFFLOAD_TRACE=1 UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
---> offloadPlatformGet(.NumEntries = 0, .phPlatforms = {}, .pNumPlatforms = 0x7ffd05e4d6e0 (2))-> OFFLOAD_RESULT_SUCCESS
---> offloadPlatformGet(.NumEntries = 2, .phPlatforms = {0x564bf4040220, 0x564bf4040240}, .pNumPlatforms = nullptr)-> OFFLOAD_RESULT_SUCCESS
...
```
### Open questions and future work
* The new API is implemented in a separate library
(`liboffload_new.so`). It could just as easily be part of the existing
`libomptarget` library - I have no strong feelings on which is better.
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: 9cc2502c048b1403ba8ba5cc5a655d867c329d12
https://github.com/llvm/llvm-project/commit/9cc2502c048b1403ba8ba5cc5a655d867c329d12
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-linux.c
Log Message:
-----------
[clang] hexagon: fix link order for libc/builtins (#117057)
When linking programs with `eld`, we get a link error like below:
Error:
/inst/clang+llvm-19.1.0-cross-hexagon-unknown-linux-musl/x86_64-linux-gnu/bin/../target/hexagon-unknown-linux-musl//usr/lib/libc.a(scalbn.lo)(.text.scalbn+0x3c):
undefined reference to `__hexagon_muldf3'
libc has references to the clang_rt builtins library, so the order of
the libraries should be reversed.
Commit: d88ed9357a0e4a49ce908c538ef21c1702c34638
https://github.com/llvm/llvm-project/commit/d88ed9357a0e4a49ce908c538ef21c1702c34638
Author: Raphael Moreira Zinsly <6718397+rzinsly at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
Log Message:
-----------
[NFC][RISCV] Refactor allocation of the stack space (#116625)
Separates the stack allocations from prologue in preparation for the
stack clash protection support.
Commit: e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
https://github.com/llvm/llvm-project/commit/e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
Log Message:
-----------
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
This patch support for intrinsics in clang, as well as assembly
instructions in the backend.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
https://github.com/llvm/llvm-project/commit/6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8ea78002c2637faf56ed5c0c88582fdd4f0ac701
https://github.com/llvm/llvm-project/commit/8ea78002c2637faf56ed5c0c88582fdd4f0ac701
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Add test case for RVV CSRs with cm.push.
The cfi_offset is incorrect for the RVV registers when cm.push
is used.
Commit: 7ad1084b521ea191245c47b4e63e4f97035e3786
https://github.com/llvm/llvm-project/commit/7ad1084b521ea191245c47b4e63e4f97035e3786
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (#117380)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 91af15b7648a10c3edcd9792b3f3487be399233b
https://github.com/llvm/llvm-project/commit/91af15b7648a10c3edcd9792b3f3487be399233b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (#117381)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8997bf8e4636592ca0e4f31747adc02904d47b0c
https://github.com/llvm/llvm-project/commit/8997bf8e4636592ca0e4f31747adc02904d47b0c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (#117382)
OPSEL[3] selects low/high 16 bits of dest write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 70fef78329eb4da338ef8345b5059f9a57ff21a5
https://github.com/llvm/llvm-project/commit/70fef78329eb4da338ef8345b5059f9a57ff21a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (#117383)
OPSEL[0] selects srcword to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 362d8fb2416ca3393b960eb158301d6f06dc5324
https://github.com/llvm/llvm-project/commit/362d8fb2416ca3393b960eb158301d6f06dc5324
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (#117384)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 00770489e4299fe6ab99b1772127d84dfe222ffc
https://github.com/llvm/llvm-project/commit/00770489e4299fe6ab99b1772127d84dfe222ffc
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/InitPreprocessor.cpp
A clang/test/C/C23/n2412.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
Log Message:
-----------
[C23] Fixed the value of BOOL_WIDTH (#117364)
The standard mandates that this returns the width of the type, which is
the number of bits in the value. For bool, that's required to be `1`
explicitly.
Fixes #117348
Commit: 0a140c4248b5eae5c044de4f394852ee7339a5e8
https://github.com/llvm/llvm-project/commit/0a140c4248b5eae5c044de4f394852ee7339a5e8
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
Log Message:
-----------
[AMDGPU] Adds pre-commit test for fmul-select combine (#111107)
This adds the f32/f64/f16/bf16 test cases for below pattern :
`fmul x, select(y, A, B)`
with just one use of select Inst above.
It acts as pre-commit tests for dagCombining above pattern into cheaper
ldexp in case of non-inlline 32 bit-constants. (#111109)
Commit: 29828b26fac3ee744c8f7dcb33cc082dc7c00a02
https://github.com/llvm/llvm-project/commit/29828b26fac3ee744c8f7dcb33cc082dc7c00a02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_offset for RVV CSRs. (#117408)
getCalleeSavedStackSize() already contains RVPushStackSize. Don't
subtract it again.
Commit: d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
https://github.com/llvm/llvm-project/commit/d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
A libc/shared/rpc_opcodes.h
M libc/src/__support/RPC/rpc_client.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc][NFC] Move RPC opcodes to the 'shared/' directory as well
Commit: 1a86d44c80d2a0c603f67ed8bdcccaed830719a3
https://github.com/llvm/llvm-project/commit/1a86d44c80d2a0c603f67ed8bdcccaed830719a3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (#117417)
OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d]
where, c & d i.e. OPSEL[3 : 2] selects which dst_byte to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 3cb28522ba4c2b80fbaf0840377aab4fce985110
https://github.com/llvm/llvm-project/commit/3cb28522ba4c2b80fbaf0840377aab4fce985110
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Reapply "[runtimes] Allow building against an installed LLVM tree"
This relands #86209 which was reverted because ./bin/llvm no longer
accepted test paths in the source tree instead of the build tree. This was
happening because `add_subdirectory(${LLVM_MAIN_SRC_DIR}/utils/llvm-lit`
was called before all tsst suites were registered, and therefore it was
missing the source->build dir mappings.
Original commit message:
I am currently trying to test the LLVM runtimes (including compiler-rt)
against an installed LLVM tree rather than a build tree (since that is
no longer available). Currently, the runtimes build of compiler-rt assumes
that LLVM_BINARY_DIR is writable since it uses configure_file() to write
there during the CMake configure stage. Instead, generate this file inside
CMAKE_CURRENT_BINARY_DIR, which will match LLVM_BINARY_DIR when invoked
from llvm/runtimes/CMakeLists.txt.
I also needed to make a minor change to the hwasan tests: hwasan_symbolize
was previously found in the LLVM_BINARY_DIR, but since it is generated as
part of the compiler-rt build it is now inside the CMake build directory
instead. I fixed this by passing the output directory to lit as
config.compiler_rt_bindir and using llvm_config.add_tool_substitutions().
For testing that we no longer write to the LLVM install directory as
part of testing or configuration, I created a read-only bind mount and
configured the runtimes builds as follows:
```
$ sudo mount --bind --read-only ~/llvm-install /tmp/upstream-llvm-readonly
$ cmake -DCMAKE_BUILD_TYPE=Debug \
-DCMAKE_C_COMPILER=/tmp/upstream-llvm-readonly/bin/clang \
-DCMAKE_CXX_COMPILER=/tmp/upstream-llvm-readonly/bin/clang++ \
-DLLVM_INCLUDE_TESTS=TRUE -DLLVM_ENABLE_ASSERTIONS=TRUE \
-DCOMPILER_RT_INCLUDE_TESTS=TRUE -DCOMPILER_RT_DEBUG=OFF \
-DLLVM_ENABLE_RUNTIMES=compiler-rt \
-DCMAKE_DISABLE_FIND_PACKAGE_LLVM=TRUE \
-DCMAKE_DISABLE_FIND_PACKAGE_Clang=TRUE \
-G Ninja -S ~/upstream-llvm-project/runtimes \
-B ~/upstream-llvm-project/runtimes/cmake-build-debug-llvm-git
```
Pull Request: https://github.com/llvm/llvm-project/pull/114307
Commit: d047bee496e07748f0dd70f52c3b309c66fedab3
https://github.com/llvm/llvm-project/commit/d047bee496e07748f0dd70f52c3b309c66fedab3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "[Offload] Introduce offload-tblgen and initial new API implementation (#108413)"
This reverts commit 8a2311c4bf9993230e37dc20b57973dc917f2338.
Commit: a5dd6463608bb09404e8a898ed337ef0b4a292c4
https://github.com/llvm/llvm-project/commit/a5dd6463608bb09404e8a898ed337ef0b4a292c4
Author: B I Mohammed Abbas <bimohammadabbas at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
Log Message:
-----------
Add extendhfxf2 into compiler rt (#113897)
Retry of pr #109090 and #111099.
Co-authored-by: Alexander Richardson <alexrichardson at google.com>
Commit: ed6749a4055c8b1500b39ebd4a8b981bf25250e8
https://github.com/llvm/llvm-project/commit/ed6749a4055c8b1500b39ebd4a8b981bf25250e8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote frexp with Zfh.
The default expansion tries to create an illegal integer type after
legalization.
Commit: b0bc4674b761a71974e561184d055ac8159fd578
https://github.com/llvm/llvm-project/commit/b0bc4674b761a71974e561184d055ac8159fd578
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
Log Message:
-----------
[X86] Fix bad instregex in VPMOVSX/ZX znver4 512-bit patterns.
The Z size was optional, meaning it matched with the 128-bit SSE instructions as well.
Noticed while triaging the strange perf numbers on #110308
Commit: bb88fd171a6be892cec36969860a9034b48b8656
https://github.com/llvm/llvm-project/commit/bb88fd171a6be892cec36969860a9034b48b8656
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A clang/test/CodeGenHLSL/resource-bindings.hlsl
M llvm/docs/DirectX/DXILResources.rst
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
Log Message:
-----------
[DirectX] Calculate resource binding offsets using the lower bound (#117303)
In the DXIL CreateHandle and CreateHandleFromBinding ops, resource
bindings are
indexed from the beginning of the binding space, not from the binding
itself.
Translate from an index into the binding to one from the beginning of
the space
when lowering to these operations.
Commit: fdf1f69c57ac3667d27c35e097040284edb1f574
https://github.com/llvm/llvm-project/commit/fdf1f69c57ac3667d27c35e097040284edb1f574
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/Generic/cgdata-merge-local.ll
A llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
[CGData][GMF] Skip No Params (#116548)
This update follows up on change #112671 and is mostly a NFC, with the following exceptions:
- Introduced `-global-merging-skip-no-params` to bypass merging when no parameters are required.
- Parameter count is now calculated based on the unique hash count.
- Added `-global-merging-inst-overhead` to adjust the instruction overhead, reflecting the machine instruction size.
- Costs and benefits are now computed using the double data type. Since the finalization process occurs offline, this should not significantly impact build time.
- Moved a sorting operation outside of the loop.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: b0ca543532d13fde8907853f6c9909ad7e68cd9f
https://github.com/llvm/llvm-project/commit/b0ca543532d13fde8907853f6c9909ad7e68cd9f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove dead code in MemProfReader (NFC) (#117607)
The only constructor in current use is the one that takes
IndexedMemProfData. Likewise, the only accessor in current use is
takeMemProfData.
Commit: fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
https://github.com/llvm/llvm-project/commit/fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
R llvm/test/CodeGen/Generic/cgdata-merge-local.ll
R llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
Revert "[CGData][GMF] Skip No Params (#116548)"
This reverts commit fdf1f69c57ac3667d27c35e097040284edb1f574.
Commit: c94d715867ef73d57f6bbe2bd7fbda3328ab1d1d
https://github.com/llvm/llvm-project/commit/c94d715867ef73d57f6bbe2bd7fbda3328ab1d1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
Log Message:
-----------
[RISCV] Add coverage for immediate sinking in switch vs branch cases
This come up in the context of pr 108889. We always end up sinking
the value in the phi if we dispatched via a switch, but not if we'd
dispatched via a branch. This is purely an artifact of current
lowering.
Commit: d733fa1c90e36aa39b111fab6a573eaab62d960b
https://github.com/llvm/llvm-project/commit/d733fa1c90e36aa39b111fab6a573eaab62d960b
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)
We can move the logic from adjustStackForRVV into adjustReg, which
results in the remaining logic being trivially inlined to the two
callers and allows a duplicate copy of the same logic in
eliminateFrameIndex to be pruned.
Commit: 5001f1605893f21b1ae9defd82ee02999164f996
https://github.com/llvm/llvm-project/commit/5001f1605893f21b1ae9defd82ee02999164f996
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (#117418)
OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8e510b8472580388272a0621f79ec0346d9909af
https://github.com/llvm/llvm-project/commit/8e510b8472580388272a0621f79ec0346d9909af
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Log Message:
-----------
[RISCV] Fix a warning
This patch fixes:
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:476:25: error: unused
variable 'ST' [-Werror,-Wunused-variable]
Commit: deab4e9ab26d6e2c095c04821d17c68cca43a174
https://github.com/llvm/llvm-project/commit/deab4e9ab26d6e2c095c04821d17c68cca43a174
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocatable.h
Log Message:
-----------
[flang][cuda][NFC] Add missing default values (#117610)
Make it homogenous with other runtime entry points.
Commit: 96547decd5f12c4357b104d107350c8a14b47650
https://github.com/llvm/llvm-project/commit/96547decd5f12c4357b104d107350c8a14b47650
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
A llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions-obj-test.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/doubles.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/no_flags.ll
Log Message:
-----------
[DirectX] Infrastructure to collect shader flags for each function (#112967)
Currently, ShaderFlagsAnalysis pass represents various module-level
properties as well as function-level properties of a DXIL Module using a
single mask. However, one mask per function is needed for accurate
computation of shader flags mask, such as for entry function metadata
creation.
This change introduces a structure that wraps a sorted vector of
function-shader flag mask pairs that represent function properties
instead of a single shader flag mask that represents module properties
and properties of all functions. The result type of ShaderFlagsAnalysis
pass is changed to newly-defined structure type instead of a single
shader flags mask.
This allows accurate computation of shader flags of an entry function
(and all functions in a library shader) for use during its metadata
generation (DXILTranslateMetadata pass) and its feature flags in DX
container globals construction (DXContainerGlobals pass) based on the
shader flags mask of functions. However, note that the change to
implement propagation of such callee-based shader flags mask computation
is planned in a follow-on PR. Consequently, this PR changes shader flag
mask computation in DXILTranslateMetadata and DXContainerGlobals passes
to simply be a union of module flags and shader flags of all functions,
thereby retaining the existing effect of using a single shader flag
mask.
Commit: 466ff3ed70e50343c9617de318e1b40efa03529d
https://github.com/llvm/llvm-project/commit/466ff3ed70e50343c9617de318e1b40efa03529d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark VPIRInstruction::getInstruction) as const (NFCI).
Split off from https://github.com/llvm/llvm-project/pull/114292.
Commit: 30af6fb163add17a6be515200881afdff91d213a
https://github.com/llvm/llvm-project/commit/30af6fb163add17a6be515200881afdff91d213a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Group together helpers for retrieving various VPBlocks (NFCI).
Group together functions to retrieve various blocks of a VPlan, as
suggested in https://github.com/llvm/llvm-project/pull/114292.
Commit: 9de73b20404f0b2db1cbf70d164cfe0789d5bb94
https://github.com/llvm/llvm-project/commit/9de73b20404f0b2db1cbf70d164cfe0789d5bb94
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-string.test
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
Log Message:
-----------
[DWARF] Fix DWARTTypePrinter unable to print qualified name for DW_TAG_typedef DIE (#117239)
Fix a bug introduced in
https://github.com/llvm/llvm-project/pull/117071.
Ideally the DWARTTypePrinter test should go to
`llvm/unittests/DebugInfo/DWARF/DWARTTypePrinterTest.cpp`.
Commit: fe69a20cc1e46bf8473aaef1be8a1805c80fc9d4
https://github.com/llvm/llvm-project/commit/fe69a20cc1e46bf8473aaef1be8a1805c80fc9d4
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/AArch64/cgdata-merge-crash.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-local.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-no-params.ll
R llvm/test/CodeGen/Generic/cgdata-merge-crash.ll
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
Reland [CGData][GMF] Skip No Params (#116548)
This update follows up on change #112671 and is mostly a NFC, with the following exceptions:
- Introduced `-global-merging-skip-no-params` to bypass merging when no parameters are required.
- Parameter count is now calculated based on the unique hash count.
- Added `-global-merging-inst-overhead` to adjust the instruction overhead, reflecting the machine instruction size.
- Costs and benefits are now computed using the double data type. Since the finalization process occurs offline, this should not significantly impact build time.
- Moved a sorting operation outside of the loop.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: 1df34f12421317a365db96de9b713342c32c13b7
https://github.com/llvm/llvm-project/commit/1df34f12421317a365db96de9b713342c32c13b7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
Log Message:
-----------
[MCA][X86] Add avx512 test coverage for VPMOV truncation instructions
We only had partial VPMOVWB test coverage
Commit: 0988bf8d75de2f55484db02391db5165e7b7d37d
https://github.com/llvm/llvm-project/commit/0988bf8d75de2f55484db02391db5165e7b7d37d
Author: Robert Barinov <robert.barinov at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/tools/llvm-reduce/distinct-dimetadata-nullptr.ll
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
Log Message:
-----------
[LLVM-Reduce] - Null pointer handling during distinct metadata reduction (#117570)
Some distinct metadata nodes, e.g DICompileUnit, have implicit nullptrs
inside them. Iterating over them with dyn_cast leads to a crash, change
the behavior so that the nullptr operands are skipped.
Add the test distinct-metadata-nullptr.ll which will crash if null
pointers are not handled correctly.
Commit: 935da49a4d02316cbd0458d09d5913b6d1cabddc
https://github.com/llvm/llvm-project/commit/935da49a4d02316cbd0458d09d5913b6d1cabddc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Log Message:
-----------
AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)
I haven't figured out how to do anything useful with this yet,
but it seems you are supposed to pass this to the subtarget
constructor.
Commit: ece4e1276e2140d84b05b8c430a0e547a1f23210
https://github.com/llvm/llvm-project/commit/ece4e1276e2140d84b05b8c430a0e547a1f23210
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[mlir][Affine] Split off delinearize parts that depend on last component (#117015)
If we have
%0 = affine.linearize_index disjoint [%a, %b] by (A, B)
%1:3 = affine.delinearize_index %0 into (A, B1, B2)
where B = B1 * B2 (or some mor complex product), we can simplify this to
%0 = affine.linearize_index disjoint [%a] by (A)
%1a:1 = affine.delinearize_index %0 into (A)
%1b:2 = affine.delinearize_index %b into (B1, B2)
This, and more complex cases, prevent us from adding terms together only
to divide them away from each other.
---------
Co-authored-by: Abhishek Varma <abhvarma at amd.com>
Commit: 76f0ff8210d56a050d2679926a2fdddd3a8c16d6
https://github.com/llvm/llvm-project/commit/76f0ff8210d56a050d2679926a2fdddd3a8c16d6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Add an extra check to avoid infinite vectorization attempts
Added extra check for the cost of the buildvector if the -slp-threshold
option is used. Prevents infinite vectorization attempts.
Commit: ab4e06667dbd777f32061ac3fff69328dc787fce
https://github.com/llvm/llvm-project/commit/ab4e06667dbd777f32061ac3fff69328dc787fce
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/test/MC/ELF/relocation.s
Log Message:
-----------
[X86][MC] Add R_X86_64_CODE_6_GOTTPOFF (#117277)
For
add %reg1, name at GOTTPOFF(%rip), %reg2
add name at GOTTPOFF(%rip), %reg1, %reg2
{nf} add %reg1, name at GOTTPOFF(%rip), %reg2
{nf} add name at GOTTPOFF(%rip), %reg1, %reg2
{nf} add name at GOTTPOFF(%rip), %reg
add
`R_X86_64_CODE_6_GOTTPOFF` = 50
if the instruction starts at 6 bytes before the relocation offset. It's
similar to R_X86_64_GOTTPOFF.
Linker can treat `R_X86_64_CODE_6_GOTTPOFF` as `R_X86_64_GOTTPOFF` or
convert the instructions above to
add $name at tpoff, %reg1, %reg2
add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg1, %reg2
{nf} add $name at tpoff, %reg
if the first byte of the instruction at the relocation `offset - 6` is
`0xd5` (namely, encoded w/REX2 prefix) when possible.
Binutils patch:
https://github.com/bminor/binutils-gdb/commit/5bc71c2a6b8efb27089baa1fecded82be4f550a7
Binutils mailthread:
https://sourceware.org/pipermail/binutils/2024-February/132351.html
ABI discussion:
https://groups.google.com/g/x86-64-abi/c/FhEZjCtDLFw/m/VHDjN4orAgAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: 4c91662a519705c2d0b6e002214a3e307f09b373
https://github.com/llvm/llvm-project/commit/4c91662a519705c2d0b6e002214a3e307f09b373
Author: Caslyn Tonelli <6718161+Caslyn at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/src/__support/common.h
Log Message:
-----------
[libc] Resolve multi-line comment error (#117636)
gcc interprets a backslash '\\' as the last char before a new line as a
line continuation character, even in a comment context. This can produce
an "error: multi-line comment [-Werror=comment]".
This removes the line continuation so that the comment can compile with
gcc.
Commit: 1973270fc66680e6894c3ae9395a7e07e7b4d43c
https://github.com/llvm/llvm-project/commit/1973270fc66680e6894c3ae9395a7e07e7b4d43c
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/src/string/memory_utils/op_x86.h
Log Message:
-----------
[libc] suppress string warning in case intrinsics are defined as macros (#117640)
Commit: 32432a6a02fe41fa83fef6605489744957dc1b0a
https://github.com/llvm/llvm-project/commit/32432a6a02fe41fa83fef6605489744957dc1b0a
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
Log Message:
-----------
[libc] suppress math library warnings on windows (#117638)
Commit: 1ea7ced7eebf26aba1938d84ba99e2e6421c503c
https://github.com/llvm/llvm-project/commit/1ea7ced7eebf26aba1938d84ba99e2e6421c503c
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/python/mlir/_mlir_libs/__init__.py
Log Message:
-----------
[mlir][py] Enable disabling loading all registered (#117643)
There is a pending todo about always eagerly loading or not. Make this
behavior optional and give the control to the user in a backwards
compatible manner. This is made optional as there were arguments for
both forms, kept it in form that is backwards compatible.
Commit: 97fe5fa54c2e99dc0fe14fff1940b31bf697eff2
https://github.com/llvm/llvm-project/commit/97fe5fa54c2e99dc0fe14fff1940b31bf697eff2
Author: Kai Luo <gluokai at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/Driver/cuda-no-threadsafe-statics.cu
Log Message:
-----------
[Driver] Pass `--cuda-path` to test (#117415)
My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0 (inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-path' to specify a different CUDA install, pass a different GPU arch with '--cuda-gpu-arch', or pass '--no-cuda-version-check'
```
Fix it by passing `--cuda-path`. Hope this doesn't affect the original
intention of the test.
Commit: cac978331f533c53b3f909dde673bb2d7b2ccede
https://github.com/llvm/llvm-project/commit/cac978331f533c53b3f909dde673bb2d7b2ccede
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
A clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
R llvm/test/CodeGen/DirectX/updateCounter.ll
Log Message:
-----------
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffers (#117608)
Introduces `__builtin_hlsl_buffer_update_counter` clang buildin that is
used to implement the `IncrementCounter` and `DecrementCounter` methods
on `RWStructuredBuffer` and `RasterizerOrderedStructuredBuffer` (see
Note).
The builtin is translated to LLVM intrisic `llvm.dx.bufferUpdateCounter`
or `llvm.spv.bufferUpdateCounter`.
Introduces `BuiltinTypeMethodBuilder` helper in `HLSLExternalSemaSource`
that enables adding methods to builtin types using builder pattern like
this:
```
BuiltinTypeMethodBuilder(Sema, RecordBuilder, "MethodName", ReturnType)
.addParam("param_name", Type, InOutModifier)
.callBuiltin("buildin_name", { BuiltinParams })
.finalizeMethod();
```
Fixes #113513
[First version](llvm/llvm-project#114148) of this PR was reverted
because of build break.
Commit: c2bb056482212a6afa91f6d52274fe0a74b91720
https://github.com/llvm/llvm-project/commit/c2bb056482212a6afa91f6d52274fe0a74b91720
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
Log Message:
-----------
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)
A special case in type legalization wasn't accounting for different
operand numbering between FLDEXP and STRICT_FLDEXP.
AArch64 already asked STRICT_FLDEXP to be promoted, but had no test for
it.
Commit: 2ab84a60ff88279884ca1b2a1655bd9f119bc803
https://github.com/llvm/llvm-project/commit/2ab84a60ff88279884ca1b2a1655bd9f119bc803
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/Analysis/CostModel/X86/fptoi_sat.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/pr114520.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
M llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
Log Message:
-----------
[X86][FP16][BF16] Improve vectorization of fcmp (#116153)
Commit: c1a3960abe5ca316e9a26e87cdc3a7f94e420dc6
https://github.com/llvm/llvm-project/commit/c1a3960abe5ca316e9a26e87cdc3a7f94e420dc6
Author: Daniel Zabawa <daniel.zabawa at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrPredicates.td
A llvm/test/CodeGen/X86/apx/imulzu.ll
Log Message:
-----------
[X86] Add APX imulzu support. (#116806)
Add patterns to select 16b imulzu with -mapx-feature=zu, including
folding of zero-extends of the result. IsDesirableToPromoteOp is changed
to leave 16b multiplies by constant un-promoted, as imulzu will not
cause partial-write stalls.
Commit: 2ed8c5de585491182486f392a5a570cc5c4474df
https://github.com/llvm/llvm-project/commit/2ed8c5de585491182486f392a5a570cc5c4474df
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
A flang/test/Transforms/OpenMP/lower-workshare-nested.mlir
Log Message:
-----------
[flang][OpenMP] Fix handling of nested loop wrappers in LowerWorkshare (#117275)
Commit: ebcaa577158de095f0093025ae1127d211a2a535
https://github.com/llvm/llvm-project/commit/ebcaa577158de095f0093025ae1127d211a2a535
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Log Message:
-----------
[GISel] #undef macros when they are no longer needed. NFC (#117652)
These macros are created inside a function. They should be undefined
before the end of the function.
Commit: bf07a569b73b5f8634cad30fa21c03a1e3d63e0b
https://github.com/llvm/llvm-project/commit/bf07a569b73b5f8634cad30fa21c03a1e3d63e0b
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Remove extra commas of llvm.vp.ctlz (#117542)
Commit: dd7aabf7c041f094ef2124bb5b8fe9434490d266
https://github.com/llvm/llvm-project/commit/dd7aabf7c041f094ef2124bb5b8fe9434490d266
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[TTI][RISCV] Deduplicate type-based VP costing of vpcmp/vpcast (#117520)
Refered to: https://github.com/llvm/llvm-project/pull/115983
Commit: 6633916ef5ab17bae9b2214a9e3327295ce56b5a
https://github.com/llvm/llvm-project/commit/6633916ef5ab17bae9b2214a9e3327295ce56b5a
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Remove getPostRAMutations (#117527)
We are using `PostMachineScheduler` instead of `PostRAScheduler`
since #68696.
The hook `getPostRAMutations` is only used in `PostRAScheduler` so
it is actually dead code for RISC-V now.
Commit: 6657d4bd70523e6852f07f64711fb15bdf7b347a
https://github.com/llvm/llvm-project/commit/6657d4bd70523e6852f07f64711fb15bdf7b347a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
Log Message:
-----------
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
This looks like a rather weird change, so let me explain why this isn't
as unreasonable as it looks. Let's start with the problem it's solving.
```
define signext i32 @overlap_live_ranges(ptr %arg, i32 signext %arg1) { bb:
%i = icmp eq i32 %arg1, 1
br i1 %i, label %bb2, label %bb5
bb2: ; preds = %bb
%i3 = getelementptr inbounds nuw i8, ptr %arg, i64 4
%i4 = load i32, ptr %i3, align 4
br label %bb5
bb5: ; preds = %bb2, %bb
%i6 = phi i32 [ %i4, %bb2 ], [ 13, %bb ]
ret i32 %i6
}
```
Right now, we codegen this as:
```
li a3, 1
li a2, 13
bne a1, a3, .LBB0_2
lw a2, 4(a0)
.LBB0_2:
mv a0, a2
ret
```
In this example, we have two values which must be assigned to a0 per the
ABI (%arg, and the return value). SelectionDAG ensures that all values
used in a successor phi are defined before exit the predecessor block.
This creates an ADDI to materialize the immediate in the entry block.
Currently, this ADDI is not sunk into the tail block because we'd have
to split a critical edges to do so. Note that if our immediate was
anything large enough to require two instructions we *would* split this
critical edge.
Looking at other targets, we notice that they don't seem to have this
problem. They perform the sinking, and tail duplication that we don't.
Why? Well, it turns out for AArch64 that this is entirely an accident of
the existance of the gpr32all register class. The immediate is
materialized into the gpr32 class, and then copied into the gpr32all
register class. The existance of that copy puts us right back into the
two instruction case noted above.
This change essentially just bypasses this emergent behavior aspect of
the aarch64 behavior, and implements the same "always sink immediates"
behavior for RISCV as well.
Commit: 5dd48c4901c60f2a38aa4e78160cc72eafcbbc5b
https://github.com/llvm/llvm-project/commit/5dd48c4901c60f2a38aa4e78160cc72eafcbbc5b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 658db918fe47efc0a3ba0556d58d607f0919f1e3
https://github.com/llvm/llvm-project/commit/658db918fe47efc0a3ba0556d58d607f0919f1e3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 of gfx950. (#117591)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 22503a9df16e8bf320c81ffbd3b4c70de45f8053
https://github.com/llvm/llvm-project/commit/22503a9df16e8bf320c81ffbd3b4c70de45f8053
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c767570eb1d8d11d42b831ac64eae44786782827
https://github.com/llvm/llvm-project/commit/c767570eb1d8d11d42b831ac64eae44786782827
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 of gfx950. (#117593)
OPSEL[0] selects src_word to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: d727b6f7778d98a3c506c6150a5d4f68056c1cee
https://github.com/llvm/llvm-project/commit/d727b6f7778d98a3c506c6150a5d4f68056c1cee
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_fp4_{f|bf}16 on gfx950. (#117594)
These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c3377af4c3646e84f33d4e50846645b1c17f6403
https://github.com/llvm/llvm-project/commit/c3377af4c3646e84f33d4e50846645b1c17f6403
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
Log Message:
-----------
[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515)
Commit: a87d484a97f6ddc7404a2970a764158a5b27e3e5
https://github.com/llvm/llvm-project/commit/a87d484a97f6ddc7404a2970a764158a5b27e3e5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Support v_cvt_scalef32_2xpk16_{bf|fp}6_f32 for gfx950. (#117595)
Scale packed 16-component single-precision float vectors from
two source inputs using the exponent provided by the third
single-precision float input, then convert the values to a packed
32-component FP6 float value.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 5d650a62a35c2f38b112f5ee930654e678bcd5bb
https://github.com/llvm/llvm-project/commit/5d650a62a35c2f38b112f5ee930654e678bcd5bb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_ashr_pk_i8/u8_i32 instructions for gfx950 (#117596)
This patch adds assembly and builtin support for v_ashr_pk_i8/u8_i32
instructions.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: aa7eb5723cb4499f35ed1c5455f668ccc078e7c2
https://github.com/llvm/llvm-project/commit/aa7eb5723cb4499f35ed1c5455f668ccc078e7c2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
A llvm/test/MC/AMDGPU/gfx950_dlops.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_dot2_f32_bf16 instruction for gfx950 (#117597)
v_dot2_f32_bf16 was added in gfx11 along with v_dot2_f16_f16 and v_dot2_bf16_bf16.
All three instructions were part of Dot9 instructions in the compiler.
This patch will split existing dot9 (v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16)
into new dot9 (v_dot2_f16_f16 and v_dot2_bf16_bf16), and dot12 (v_dot2_f32_bf16).
All necessary changes to gfx11 and gfx12 are updated to reflect this change.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 716364ebd6649aeca8658680ebb8b0424d028006
https://github.com/llvm/llvm-project/commit/716364ebd6649aeca8658680ebb8b0424d028006
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
A llvm/test/MC/AMDGPU/gfx950_xdlops.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_xdlops.txt
Log Message:
-----------
AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)
The encoding of v_dot2c_f32_bf16 opcode is same as v_mac_f32 in gfx90a,
both from gfx9 series. This required a new decoderNameSpace GFX950_DOT.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 7fc71f79099b1556a57c9e96f7d62064dcff44d4
https://github.com/llvm/llvm-project/commit/7fc71f79099b1556a57c9e96f7d62064dcff44d4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
Log Message:
-----------
AMDGPU: Support buffer_atomic_pk_add_bf16 for gfx950 (#117599)
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: a5174de8c2244b2651568095e3136dd90df1c869
https://github.com/llvm/llvm-project/commit/a5174de8c2244b2651568095e3136dd90df1c869
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add encodings for minimum3/maximum3 f32 for gfx950 (#117600)
Commit: ae719f07562a2eb74f620b1f6d798d6507760514
https://github.com/llvm/llvm-project/commit/ae719f07562a2eb74f620b1f6d798d6507760514
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add minimum3/maximum3 pkf16 for gfx950 encodings (#117601)
Commit: eb5cda480d2ad81230b2aa3e134e2b603ff90a1c
https://github.com/llvm/llvm-project/commit/eb5cda480d2ad81230b2aa3e134e2b603ff90a1c
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocatable.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/allocatable.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] cuf.allocate: Carry over stream to the runtime call (#117631)
- Update the runtime entry points to accept a stream information
- Update the conversion of `cuf.allocate` to pass correctly the stream
information when present.
Note that the stream is not currently used in the runtime. This will be
done in a separate patch as a design/solution needs to be down together
with the allocators.
Commit: ca184cfc088a843e545e5f04b48813e6f9bfba77
https://github.com/llvm/llvm-project/commit/ca184cfc088a843e545e5f04b48813e6f9bfba77
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/ClangdLSPServer.h
M clang-tools-extra/clangd/ClangdServer.cpp
M clang-tools-extra/clangd/ClangdServer.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/XRefs.h
M clang-tools-extra/clangd/index/Index.cpp
M clang-tools-extra/clangd/index/Index.h
M clang-tools-extra/clangd/index/MemIndex.cpp
M clang-tools-extra/clangd/index/MemIndex.h
M clang-tools-extra/clangd/index/Merge.cpp
M clang-tools-extra/clangd/index/Merge.h
M clang-tools-extra/clangd/index/ProjectAware.cpp
M clang-tools-extra/clangd/index/Ref.h
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/index/SymbolCollector.h
M clang-tools-extra/clangd/index/dex/Dex.cpp
M clang-tools-extra/clangd/index/dex/Dex.h
M clang-tools-extra/clangd/test/type-hierarchy-ext.test
M clang-tools-extra/clangd/test/type-hierarchy.test
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/RenameTests.cpp
Log Message:
-----------
[clangd] Support outgoing calls in call hierarchy (#77556)
Co-authored-by: Quentin Chateau <quentin.chateau at gmail.com>
Commit: d77cab823fc03f6933c3375baaddaae1477bb1d2
https://github.com/llvm/llvm-project/commit/d77cab823fc03f6933c3375baaddaae1477bb1d2
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/clangd/ClangdLSPServer.h
M clang-tools-extra/clangd/ClangdServer.cpp
M clang-tools-extra/clangd/ClangdServer.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/XRefs.h
M clang-tools-extra/clangd/index/Index.cpp
M clang-tools-extra/clangd/index/Index.h
M clang-tools-extra/clangd/index/MemIndex.cpp
M clang-tools-extra/clangd/index/MemIndex.h
M clang-tools-extra/clangd/index/Merge.cpp
M clang-tools-extra/clangd/index/Merge.h
M clang-tools-extra/clangd/index/ProjectAware.cpp
M clang-tools-extra/clangd/index/Ref.h
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/index/SymbolCollector.h
M clang-tools-extra/clangd/index/dex/Dex.cpp
M clang-tools-extra/clangd/index/dex/Dex.h
M clang-tools-extra/clangd/test/type-hierarchy-ext.test
M clang-tools-extra/clangd/test/type-hierarchy.test
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
M clang-tools-extra/clangd/unittests/RenameTests.cpp
Log Message:
-----------
Revert "[clangd] Support outgoing calls in call hierarchy (#77556)" (#117668)
This reverts commit ca184cfc088a843e545e5f04b48813e6f9bfba77.
Commit: 6e57186c0c14702055984f9cfa59be02f0f72356
https://github.com/llvm/llvm-project/commit/6e57186c0c14702055984f9cfa59be02f0f72356
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Format/Format.cpp
Log Message:
-----------
[clang-format][NFC] Clean up RemoveBraces, RemoveSemi, etc.
Commit: bc282605dfe341add6f7ee8234fed2cd55f5656b
https://github.com/llvm/llvm-project/commit/bc282605dfe341add6f7ee8234fed2cd55f5656b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a TargetConstant. (#117639)
Fix all the places I could find that did't do this. We were already
mostly correct for FP_ROUND after
9a976f36615dbe15e76c12b22f711b2e597a8e51, but not STRICT_FP_ROUND.
Commit: 90f5c8b790d8a57eab49320e77d6ce11c6c2d36f
https://github.com/llvm/llvm-project/commit/90f5c8b790d8a57eab49320e77d6ce11c6c2d36f
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
Log Message:
-----------
[LV][NFC] Auto-generate the test cases related to FindLastIV idioms. (#117560)
Pre-commit for #67812
Commit: 5e3f6150b1d490090faf945777985b18db73ea3f
https://github.com/llvm/llvm-project/commit/5e3f6150b1d490090faf945777985b18db73ea3f
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
Log Message:
-----------
[lldb/NativePDB] Don't create parentless blocks (#117581)
In case of an error GetBlock would return a reference to a Block without
adding it to a parent. This doesn't seem like a good idea, and none of
the other plugins do that.
This patch fixes that by propagating errors (well, null pointers...) up
the stack.
I don't know of any specific problem that this solves, but given that
this occurs only when something goes very wrong (e.g. a corrupted PDB
file), it's quite possible noone has run into this situation, so we
can't say the code is correct either. It also gets in the way of a
refactor I'm contemplating.
Commit: 56eb559b1d49ec6fa2d75753078e5b57f4b606c2
https://github.com/llvm/llvm-project/commit/56eb559b1d49ec6fa2d75753078e5b57f4b606c2
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/attr-cpuspecific.c
Log Message:
-----------
[clang][FMV] Fix crash with cpu_specific attribute. (#115762)
When dealing with cpu_specific GlobalDecl,
GetOrCreateMultiVersionResolver should immediately return the already
created llvm function if it exists.
Fixes https://github.com/llvm/llvm-project/issues/115299.
Commit: 1b2c8f104f9c6f26500ab608060bbc6b7f40f5e1
https://github.com/llvm/llvm-project/commit/1b2c8f104f9c6f26500ab608060bbc6b7f40f5e1
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Conversion/TensorToLinalg/TensorToLinalg.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
A mlir/test/Dialect/Linalg/decompose-pad-tensor.mlir
R mlir/test/Dialect/Linalg/generalize-pad-tensor.mlir
M mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
Log Message:
-----------
[mlir][linalg] Extract `GeneralizePadOpPattern` into a standalone transformation (#117329)
Currently, `GeneralizePadOpPattern` is grouped under
`populatePadOpVectorizationPatterns`. However, as noted in #111349, this
transformation "decomposes" rather than "vectorizes" `tensor.pad`. As
such, it functions as:
* a vectorization _pre-processing_ transformation, not
* a vectorization transformation itself.
To clarify its purpose, this PR turns `GeneralizePadOpPattern` into a
standalone transformation by:
* introducing a dedicated `populateDecomposePadPatterns` method,
* adding a `apply_patterns.linalg.decompose_pad` Transform Dialect Op,
* removing it from `populatePadOpVectorizationPatterns`.
In addition, to better reflect its role, it is renamed as "decomposition"
rather then "generalization". This is in line with the recent renaming
of similar ops, i.e. tensor.pack/tensor.unpack Ops in #116439.
Commit: bb8bf858e865ec3119352bdef43c09adb4c93b31
https://github.com/llvm/llvm-project/commit/bb8bf858e865ec3119352bdef43c09adb4c93b31
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/HLFIR/assumed-rank-internal-proc.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
Log Message:
-----------
[flang] add internal_assoc flag to mark variable captured in internal procedure (#117161)
This patch adds a flag to mark hlfir.declare of host variables that are
captured in some internal procedure.
It enables implementing a simple fir.call handling in
fir::AliasAnalysis::getModRef leveraging Fortran language specifications
and without a data flow analysis.
This will allow implementing an optimization for "array =
array_function()" where array storage is passed directly into the hidden
result argument to "array_function" when it can be proven that
arraY_function does not reference "array".
Captured host variables are very tricky because they may be accessed
indirectly in any calls if the internal procedure address was captured
via some global procedure pointer. Without flagging them, there is no
way around doing a complex inter procedural data flow analysis:
- checking that the call is not made to an internal procedure is not
enough because of the possibility of indirect calls made to internal
procedures inside the callee.
- checking that the current func.func has no internal procedure is not
enough because this would be invalid with inlining when an procedure
with internal procedures is inlined inside a procedure without internal
procedure.
Commit: a96ec01e1a269b663ccc1dadc2f4429fd0df887d
https://github.com/llvm/llvm-project/commit/a96ec01e1a269b663ccc1dadc2f4429fd0df887d
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
Log Message:
-----------
[AMDGPU] Optimize out s_barrier_signal/_wait (#116993)
Extend the optimization that converts s_barrier to wave_barrier (nop)
when the number of work items is not larger than wave size.
This handles the "split barrier" form of s_barrier where the barrier
is represented by separate intrinsics (s_barrier_signal/s_barrier_wait).
Note: the version where s_barrier is used in gfx12 (and later split)
has the optimization already, but some front-ends may prefer to use
split intrinsics and this is being addressed by the patch.
Commit: 9acd8e381091765a932d54bc22359cdafa9e75c6
https://github.com/llvm/llvm-project/commit/9acd8e381091765a932d54bc22359cdafa9e75c6
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
Log Message:
-----------
[clangd] Drop requirement for named template parameters (#117565)
... in DefineOutline tweak for function templates. As opposed to class
templates, the name is not required for writing an out-of-line
definition.
Commit: 93caee17add0c7bc6770365b1d3cae93f258d866
https://github.com/llvm/llvm-project/commit/93caee17add0c7bc6770365b1d3cae93f258d866
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fveclib.c
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/IR/VFABIDemangler.h
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/IR/VFABIDemangler.cpp
A llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
A llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)
SLEEF math vector library now supports RISC-V target.
Commit: https://github.com/shibatch/sleef/pull/477
This patch enables the use of auto-vectorization with
subsequent replacement by the corresponding SLEEF function.
Commit: 29062329f3cf0ac8f1ae626e758ca64f82294fbf
https://github.com/llvm/llvm-project/commit/29062329f3cf0ac8f1ae626e758ca64f82294fbf
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
[RISCV] Implement tail call optimization in machine outliner (#115297)
Following up issue #89822, this patch adds opportunity to use tail call
in machine outliner pass.
Also it enables outline patterns with X5(T0) register.
Commit: 3e1b55cafc95d4ef46f302d0fcd695461e376958
https://github.com/llvm/llvm-project/commit/3e1b55cafc95d4ef46f302d0fcd695461e376958
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SDAG] Don't allow implicit trunc in getConstant() (#117558)
Assert that the passed value is a valid unsigned integer value for the
specified type.
For signed values getSignedConstant() / getSignedTargetConstant() should
be used instead.
Commit: 231e63d8162a1c78a973c6e546bea39d04fefd67
https://github.com/llvm/llvm-project/commit/231e63d8162a1c78a973c6e546bea39d04fefd67
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Refactor insertConditions. NFC. (#115476)
This just makes it more obvious that having Parent as the single
predecessor is a special case, instead of checking for it in the middle
of a loop that finds the nearest common dominator of multiple
predecessors.
Commit: 79f59afff966c3abff541535431862885dc0a833
https://github.com/llvm/llvm-project/commit/79f59afff966c3abff541535431862885dc0a833
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
Log Message:
-----------
[mlir][linalg][nfc] Update "pack-dynamic-inner-tile.mlir" (#117533)
Builds on:
* #117329: "Extract GeneralizePadOpPattern into a standalone
transformation".
* #116373: "Update pack-dynamic-inner-tile.mlir".
This update adds vectorization to the "pack-dynamic-inner-tile.mlir"
pipeline.
The pipeline first decomposes `tensor.pack` into `tensor.pad` and then
into `linalg.fill` (https://github.com/llvm/llvm-project/pull/117329).
Next, `linalg.fill` is vectorized, with vector sizes matching the inner
tile sizes of the original `tensor.pack`.
Commit: 36b1811da496a0527aab0de76bd3687ff4880bfa
https://github.com/llvm/llvm-project/commit/36b1811da496a0527aab0de76bd3687ff4880bfa
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/interception_win.h
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] Add a test skeleton for function GetInstructionSize. (#116948)
Was first part of PR #113085.
Commit: 3414993eaffcfa2cb4ff723c8468434d56dff213
https://github.com/llvm/llvm-project/commit/3414993eaffcfa2cb4ff723c8468434d56dff213
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[AMDGPU][SplitModule] Fix potential divide by zero (#117602)
A static analysis tool found that ModuleCost could be zero, so would
perform divide by zero when being printed. Perhaps this is unreachable
in practice, but the fix is straightforward enough and unlikely to be a
performance concern.
Commit: cf602b95d14532fdb97679806bc5ba9d55631875
https://github.com/llvm/llvm-project/commit/cf602b95d14532fdb97679806bc5ba9d55631875
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
A flang/test/Analysis/AliasAnalysis/gen_mod_ref_test.py
A flang/test/Analysis/AliasAnalysis/modref-call-after-inlining.fir
A flang/test/Analysis/AliasAnalysis/modref-call-args.f90
A flang/test/Analysis/AliasAnalysis/modref-call-dummies.f90
A flang/test/Analysis/AliasAnalysis/modref-call-equivalence.f90
A flang/test/Analysis/AliasAnalysis/modref-call-globals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-internal-proc.f90
A flang/test/Analysis/AliasAnalysis/modref-call-locals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-not-fortran.fir
Log Message:
-----------
[flang] handle fir.call in AliasAnalysis::getModRef (#117164)
fir.call side effects are hard to describe in a useful way using
`MemoryEffectOpInterface` because it is impossible to list which memory
location a user procedure read/write without doing a data flow analysis
of its body (even PURE procedures may read from any module variable,
Fortran SIMPLE procedure from F2023 will allow that, but they are far
from common at that point).
Fortran language specifications allow the compiler to deduce
that a procedure call cannot access a variable in many cases
This patch leverages this to extend `fir::AliasAnalysis::getModRef` to
deal with fir.call.
This will allow implementing "array = array_function()" optimization in
a future patch.
Commit: ad7bb652d61e2e8021df03018ea05750abf66b0e
https://github.com/llvm/llvm-project/commit/ad7bb652d61e2e8021df03018ea05750abf66b0e
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/docs/Intrinsics.md
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/len_trim.f90
Log Message:
-----------
[flang] Implement non-standard LNBLNK intrinsic (#117589)
This is defined here
https://gcc.gnu.org/onlinedocs/gfortran/LNBLNK.html. It is just an alias
to LEN_TRIM.
This was requested by a user:
https://discourse.llvm.org/t/unresolved-externals-with-appendend-underscore/83305
Commit: c0192a008c4a2b8afdc2b63526c0483632d81c07
https://github.com/llvm/llvm-project/commit/c0192a008c4a2b8afdc2b63526c0483632d81c07
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/test/Lower/Intrinsics/system.f90
Log Message:
-----------
[flang] implement function form of SYSTEM intrinsic (#117585)
SYSTEM is a gfortran extension which we already supported in subroutine
form. Gfortran also allows it to be called as a function, which was
requested by a user
https://discourse.llvm.org/t/unresolved-externals-with-appendend-underscore/83305/4
Commit: b9e3a769b99e9dafa3e5205dbbef9fae8573e4e2
https://github.com/llvm/llvm-project/commit/b9e3a769b99e9dafa3e5205dbbef9fae8573e4e2
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/task_mergeable.f90
M flang/test/Lower/OpenMP/task.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[flang][mlir][llvm][OpenMP] Add lowering and translation support for mergeable clause on task (#114662)
Add FIR generation and LLVMIR translation support for mergeable clause
on task construct. If mergeable clause is present on a task, the
relevant flag in `ompt_task_flag_t` is set and passed to
`__kmpc_omp_task_alloc`.
Commit: d471c85e654ad0111cdffe588b2b958b62eca29f
https://github.com/llvm/llvm-project/commit/d471c85e654ad0111cdffe588b2b958b62eca29f
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
M mlir/test/Dialect/Arith/int-range-interface.mlir
Log Message:
-----------
[mlir][int-range] Update int range inference for `arith.xori` (#117272)
Previous impl was getting incorrect results for widths > i1 and was
disabled.
While same algorithm can be used for `andi` and `ori` too, without
additional modifications it will produce less precise result.
Commit: 45fdb7755737f10822003a3dd1870ac5a5c0b8eb
https://github.com/llvm/llvm-project/commit/45fdb7755737f10822003a3dd1870ac5a5c0b8eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
Log Message:
-----------
[MCA][X86] Cleanup znver4 instregex patterns for (V)PMOV extension/truncation instructions
Split extension/truncation patterns to simplify matching.
Fix patterns to consistently match SSE/AVX1/AVX2 variants as well.
Add some missing src/dst type variants - there should be no difference in scheduling, its purely based on dst reg width.
Confirmed with Agner/uops.info
Noticed while triaging #110308
Commit: 4a7b56e6e7dd0f83c379ad06b6e81450bc691ba6
https://github.com/llvm/llvm-project/commit/4a7b56e6e7dd0f83c379ad06b6e81450bc691ba6
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
M mlir/include/mlir/IR/Matchers.h
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/CAPI/ir.c
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
Log Message:
-----------
[MLIR][Arith] Add denormal attribute to binary/unary operations (#112700)
Add support for denormal in the Arith dialect (binary and unary
operations).
Denormal are attached to every operation, and they can be of three
different
kinds:
1) ieee, denormal are preserved and processed as defined by IEEE 754
rules.
2) preserve sign, a mode where denormal numbers are flushed to zero, but
the
sign of the zero (+0 or -0) is preserved.
3) positive zero, a mode where all denormal numbers are flushed to
positive zero
(+0), ignoring the sign of the original number.
Denormal refers to both the operands and the result. Currently only
lowering for
ieee is supported.
Commit: 486644723038555a224fd09d462bb5099e64809e
https://github.com/llvm/llvm-project/commit/486644723038555a224fd09d462bb5099e64809e
Author: Vladislav Belov <vladislav.belov at syntacore.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CXXInheritance.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Fix name lookup for dependent bases (#114978)
Currently the following example is a compilation failure:
```cpp
template<typename T> struct A {
typedef int M;
struct B {
typedef void M;
struct C;
};
};
template<typename T> struct A<T>::B::C : A<T> {
M m; // void or int ?
};
```
According to the point 13.8.3.2
```
A dependent base class is a base class that is a dependent type and is not the current instantiation.
Note 2 : A base class can be the current instantiation in the case of a nested class naming an enclosing class as a base.
```
The base class `A` is the current instantiation, because `C` is a nested
class for an enclosing class `A<T>`, it's is the not-dependent base
class and we need to search the names through its scope.
This patch makes this example compile
Commit: ec4c47d9490c90a98f2dda3fc9ff7c51782678f8
https://github.com/llvm/llvm-project/commit/ec4c47d9490c90a98f2dda3fc9ff7c51782678f8
Author: ykiko <ykikoykikoykiko at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
A clang/test/CodeCompletion/keywords-cxx20.cpp
Log Message:
-----------
Add code completion for C++20 keywords. (#107982)
This commit adds code completion for C++20 keywords, fix
https://github.com/llvm/llvm-project/issues/107868.
1. complete `concept` in template context
- [x] `template<typename T> conce^` -> `concept`
- [ ] `conce^`
2. complete `requires`
- [x] constraints in template context: `template<typename T> requi^` ->
`requires`
- [x] requires expression: `int x = requ^` -> `requires (parameters) {
requirements }`
- [x] nested requirement: `requires { requ^ }` -> `requires expression
;`
3. complete coroutine keywords
- [x] `co_await^` in expression: `co_aw^` -> `co_await expression;`
- [x] `co_yield` in function body: `co_yi^` -> `co_yield expression;`
- [x] `co_return` in function body: `co_re^` -> `co_return expression;`
4. specifiers: `char8_t`, `consteval`, `constinit`
Commit: 90df66455b2ff6a3b3754a56afafc05935a05e15
https://github.com/llvm/llvm-project/commit/90df66455b2ff6a3b3754a56afafc05935a05e15
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
Log Message:
-----------
[MCA][X86] Fix throughput of (V)PMOV extension/truncation 512-bit instructions
znver4 512-bit instructions are half rate of 128/256-bit variants (still 1uop though)
Confirmed with Agner/uops.info
Noticed while triaging #110308 and #117579
Commit: 827ebf84e9af7c93a30daf4ed17e99ccef4cf94a
https://github.com/llvm/llvm-project/commit/827ebf84e9af7c93a30daf4ed17e99ccef4cf94a
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang] constexpr built-in elementwise popcount function. (#117473)
Part of #51787.
This patch adds constexpr support for the built-in elementwise popcount
function.
Commit: f94bd3c933076500b9291009d8cb5e1139c52a06
https://github.com/llvm/llvm-project/commit/f94bd3c933076500b9291009d8cb5e1139c52a06
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
R llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
R llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
Revert "[RISCV] Implement tail call optimization in machine outliner" (#117710)
Reverts llvm/llvm-project#115297
Bots are broken
Commit: 6f5e5b630559f2d17bdccfab5dff3a97ac0f8c66
https://github.com/llvm/llvm-project/commit/6f5e5b630559f2d17bdccfab5dff3a97ac0f8c66
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/unittests/IR/AffineMapTest.cpp
Log Message:
-----------
[mlir][unittest][nfc] Simplify `getInversePermutation` (#117698)
Commit: 5322415f92fe44a9dac29c95da5ed434efbbba7e
https://github.com/llvm/llvm-project/commit/5322415f92fe44a9dac29c95da5ed434efbbba7e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Use getSignedConstant() in SelectOptimalAddrMode()
All of these immediates are signed, as the surrounding comments
indicate. This fixes an assertion failure in
CodeGen/Generic/dag-combine-ossfuzz-crash.ll when run with a
powerpc-aix triple.
Commit: eb5d69c9ab5e817aaff967d06c8f358c0844b6b8
https://github.com/llvm/llvm-project/commit/eb5d69c9ab5e817aaff967d06c8f358c0844b6b8
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
A clang/test/AST/ast-dump-cxx2b-deducing-this.cpp
Log Message:
-----------
[Clang] use begin member expr location for call expr with deducing this (#117345)
Fixes #116928
Commit: 65c36179be68dda0d1cc5d7e5c5b312a6b52cc0e
https://github.com/llvm/llvm-project/commit/65c36179be68dda0d1cc5d7e5c5b312a6b52cc0e
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Arena.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/IntervalPartition.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
Log Message:
-----------
[clang][analysis][NFC]add static for internal linkage function (#117481)
Detected by misc-use-internal-linkage
Commit: 46fcdbbc78717767551594d5d9174db0bac1b375
https://github.com/llvm/llvm-project/commit/46fcdbbc78717767551594d5d9174db0bac1b375
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add alias.scope & noalias metadata to test.
Commit: f4379db49683a6b1d3d63b577985312556373c6f
https://github.com/llvm/llvm-project/commit/f4379db49683a6b1d3d63b577985312556373c6f
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mdiv32.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
A llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
Log Message:
-----------
[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instructions with inputs not signed-extended. (#116764)
Two options for clang
-mdiv32: Use div.w[u] and mod.w[u] instructions with input not
sign-extended.
-mno-div32: Do not use div.w[u] and mod.w[u] instructions with input not
sign-extended.
The default is -mno-div32.
Commit: 537343dea4e65ddb837473c9349884e856664ad8
https://github.com/llvm/llvm-project/commit/537343dea4e65ddb837473c9349884e856664ad8
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
R bolt/unittests/Core/MemoryMaps.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
Log Message:
-----------
Revert "[BOLT] DataAggregator support for binaries with multiple text segments (#92815)"
This caused test failures, see comment on the PR:
Failed Tests (2):
BOLT-Unit :: Core/./CoreTests/AArch64/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0
BOLT-Unit :: Core/./CoreTests/X86/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0
> When a binary has multiple text segments, the Size is computed as the
> difference of the last address of these segments from the BaseAddress.
> The base addresses of all text segments must be the same.
>
> Introduces flag 'perf-script-events' for testing. It allows passing perf events
> without BOLT having to parse them using 'perf script'. The flag is used to
> pass a mock perf profile that has two memory mappings for a mock binary
> that has two text segments. The size of the mapping is updated as this
> change `parseMMapEvents` processes all text segments.
This reverts commit 4b71b3782d217db0138b701c4514bd2168ca1659.
Commit: ead3a2f5980e1a713c8d4e18a4c825e1012b3701
https://github.com/llvm/llvm-project/commit/ead3a2f5980e1a713c8d4e18a4c825e1012b3701
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-117393.ll
Log Message:
-----------
[SLP][REVEC] getScalarizationOverhead should not be used when ScalarTy is FixedVectorType. (#117536)
Commit: 59b3630e032d7e92079667891e7cf585c7fe313d
https://github.com/llvm/llvm-project/commit/59b3630e032d7e92079667891e7cf585c7fe313d
Author: Victor Perez <victor.perez at codeplay.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
M mlir/test/Target/SPIRV/intel-ext-ops.mlir
Log Message:
-----------
[MLIR][SPIR-V] Drop commas from split barrier operations ASM format (#116673)
Drop commas from split barrier operations assembly format.
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Depends on #116648, review ec8d35471602cd88aa2ebaf239b698ef3ba353bd
only.
---------
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Commit: 619e4b7154606f315572ba54c0fe6c1f6c8848a0
https://github.com/llvm/llvm-project/commit/619e4b7154606f315572ba54c0fe6c1f6c8848a0
Author: 7FM <chill_dein_leben at gmx.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[MLIR][Arith] SelectOp fix invalid folding (#117555)
The pattern `select %x, true, false => %x` is only valid in case that
the return type is identical to the type of `%x` (i.e., i1). Hence, the
check `isInteger(1)` was replaced with `isSignlessInteger(1)`.
Fixes: https://github.com/llvm/llvm-project/issues/117554
Commit: f4d758634305304c0deb49a4ed3f99180a2488ea
https://github.com/llvm/llvm-project/commit/f4d758634305304c0deb49a4ed3f99180a2488ea
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/TypeUtilities.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/tools/mlir-tblgen/BytecodeDialectGen.cpp
Log Message:
-----------
[mlir] Use `llvm::filter_to_vector`. NFC. (#117655)
This got recently added to SmallVectorExtras:
https://github.com/llvm/llvm-project/pull/117460.
Commit: 4028bb10c3a396023b877d025c5776d207f29f91
https://github.com/llvm/llvm-project/commit/4028bb10c3a396023b877d025c5776d207f29f91
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/Utils/Local.cpp
A llvm/test/Transforms/EarlyCSE/noalias-addrspace.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
Log Message:
-----------
Local: Handle noalias_addrspace in combineMetadata (#103938)
This should act like range.
Previously ConstantRangeList assumed a 64-bit range. Now query from the
actual entries. This also means that the empty range has no bitwidth, so
move asserts to avoid checking the bitwidth of empty ranges.
Commit: ab6677e7d64b4612d6c92877cb1d529f922268d2
https://github.com/llvm/llvm-project/commit/ab6677e7d64b4612d6c92877cb1d529f922268d2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-metadata.ll
M llvm/test/Transforms/LICM/hoisting-preheader-debugloc.ll
Log Message:
-----------
[LICM] Only set AA metadata on hoisted load if it executes. (#117204)
https://github.com/llvm/llvm-project/pull/116220 clarified that
violations of aliasing metadata are UB.
Only set the AA metadata after hoisting a log, if it is guaranteed to
execute in the original loop.
PR: https://github.com/llvm/llvm-project/pull/117204
Commit: 9efdebc5f15e284dc7c58d327057ec8af9eed342
https://github.com/llvm/llvm-project/commit/9efdebc5f15e284dc7c58d327057ec8af9eed342
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExprMember.cpp
M clang/test/SemaCXX/warn-unused-private-field.cpp
Log Message:
-----------
[Clang] Only ignore special methods for unused private fields in BuildFieldReferenceExpr (#116965)
The original code assumed that only special methods might be defined as
defaulted. Since C++20 comparison operators might be defaulted too, and
we *do* want to consider those as using the fields of the class.
Fixes: #116961
Commit: 624e52b1e310c349e21cc0b4f67452b0fa9d1f96
https://github.com/llvm/llvm-project/commit/624e52b1e310c349e21cc0b4f67452b0fa9d1f96
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
Log Message:
-----------
[DebugInfo] Handle trailing empty blocks when seeking prologue_end spot (#117320)
The optimiser will produce empty blocks that are unconditionally
executed according to the CFG -- while it may not be meaningful code,
and won't get a prologue_end position, we need to not crash on this
input.
The fault comes from assuming that there's always a next block with some
instructions in it, that will eventually produce some meaningful control
flow to stop at -- in the given reproducer in issue #117206 this isn't
true, because the function terminates with `unreachable`. Thus, I've
refactored the "get next instruction logic" into a helper that'll step
through all blocks and terminate if there aren't any more.
Reproducer from aeubanks
Commit: db6f627f3fd4072fe1814805653a352694527a91
https://github.com/llvm/llvm-project/commit/db6f627f3fd4072fe1814805653a352694527a91
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AArch64.cpp
A clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
Log Message:
-----------
[clang][SME] Ignore flatten/clang::always_inline statements for callees with mismatched streaming attributes (#116391)
If `__attribute__((flatten))` is used on a function, or
`[[clang::always_inline]]` on a statement, don't inline any callees with
incompatible streaming attributes. Without this check, clang may produce
incorrect code when these attributes are used in code with streaming
functions.
Note: The docs for flatten say it can be ignored when inlining is
impossible: "causes calls within the attributed function to be inlined
unless it is impossible to do so".
Similarly, the (clang-only) `[[clang::always_inline]]` statement
attribute is more relaxed than the GNU `__attribute__((always_inline))`
(which says it should error it if it can't inline), saying only "If a
statement is marked [[clang::always_inline]] and contains calls, the
compiler attempts to inline those calls.". The docs also go on to show
an example of where `[[clang::always_inline]]` has no effect.
Commit: b214ca82daeece1568268ebc0fbcc2eaa649425b
https://github.com/llvm/llvm-project/commit/b214ca82daeece1568268ebc0fbcc2eaa649425b
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir][vector] Rename vector type TD definitions (nfc) (#117150)
Currently, the Vector dialect TD file includes the following "vector"
type definitions:
```mlir
def AnyVector : VectorOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVector : FixedVectorOf<[AnyType]>;
def AnyScalableVector : ScalableVectorOf<[AnyType]>;
```
In short:
* `AnyVector` _excludes_ 0-D vectors.
* `AnyVectorOfAnyRank`, `AnyFixedVector`, and `AnyScalableVector`
_include_ 0-D vectors.
The naming for "groups" that include 0-D vectors is inconsistent and can
be misleading, and `AnyVector` implies that 0-D vectors are included,
which is not the case.
This patch renames these definitions for clarity:
```mlir
def AnyVectorOfNonZeroRank : VectorOfNonZeroRankOf<[AnyType]>;
def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
def AnyFixedVectorOfAnyRank : FixedVectorOfAnyRank<[AnyType]>;
def AnyScalableVectorOfAnyRank : ScalableVectorOfAnyRank<[AnyType]>;
```
Rationale:
* The updated names are more explicit about 0-D vector support.
* It becomes clearer that scalable vectors currently allow 0-D vectors -
this might warrant a revisit.
* The renaming paves the way for adding a new group for "fixed-width
vectors excluding 0-D vectors" (e.g., AnyFixedVector), which I plan to
introduce in a follow-up patch.
Commit: 7577284c4f3cb81a8ac648683bd3af292827391f
https://github.com/llvm/llvm-project/commit/7577284c4f3cb81a8ac648683bd3af292827391f
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/SemaOpenACC/compute-construct-varlist-ast.cpp
Log Message:
-----------
[OpenACC][NFC] Update varlist-ast test to check serialization
I noticed while working on another test that I never used the PCH
trickery to get this to validate that serialization/deserialization
works correctly. It DOES, but we weren't testing it with this test like
the others.
Commit: 80df56e03b0455382cec51557bfc9f099d5c0a6f
https://github.com/llvm/llvm-project/commit/80df56e03b0455382cec51557bfc9f099d5c0a6f
Author: Mark Goncharov <110403898+mga-sc at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
Log Message:
-----------
Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)
This MR fixes failed test `CodeGen/RISCV/compress-opt-select.ll`.
It was failed due to previously merged commit `[TTI][RISCV]
Unconditionally break critical edges to sink ADDI (PR #108889)`.
So, regenerated `compress-opt-select` test.
Commit: f7dc1d0ac83b7c6b691167d8d02561ba0837b631
https://github.com/llvm/llvm-project/commit/f7dc1d0ac83b7c6b691167d8d02561ba0837b631
Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/CXXInheritance.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
Revert "[Clang] Fix name lookup for dependent bases (#114978)" (#117727)
This reverts commit 486644723038555a224fd09d462bb5099e64809e as
requested by the commit author.
Buildbots fail:
* https://lab.llvm.org/buildbot/#/builders/164/builds/4945
* https://lab.llvm.org/buildbot/#/builders/52/builds/4021
Commit: 86f7f089ee6bcf01bf082ca802220b1143a3ade9
https://github.com/llvm/llvm-project/commit/86f7f089ee6bcf01bf082ca802220b1143a3ade9
Author: Miro Bucko <mbucko at meta.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Core/PluginManager.cpp
Log Message:
-----------
Fix return value of 'PluginManager::RegisterPlugin()'. (#114120)
Commit: 88cff867a58247d0c1da19e537eb8801a54ed38e
https://github.com/llvm/llvm-project/commit/88cff867a58247d0c1da19e537eb8801a54ed38e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
Log Message:
-----------
[InstCombine] Add tests for #113301 (NFC)
Commit: ced2fc7819d5ddea616ec330f18e08ff284c1868
https://github.com/llvm/llvm-project/commit/ced2fc7819d5ddea616ec330f18e08ff284c1868
Author: Christopher Bate <cbate at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/docs/Bufferization.md
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Arith/bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-analysis.mlir
A mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-partial.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-force-copy-before-write.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/Bufferization/ops.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
M mlir/test/Dialect/Linalg/bufferize.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
M mlir/test/Dialect/MemRef/normalize-memrefs.mlir
M mlir/test/Dialect/SCF/bufferize.mlir
A mlir/test/Dialect/SCF/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Shape/bufferize.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul24_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matvec_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sampled_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sddmm_lib.mlir
M mlir/test/Dialect/SparseTensor/constant_index_map.mlir
M mlir/test/Dialect/SparseTensor/dense.mlir
M mlir/test/Dialect/SparseTensor/fuse_sparse_pad_with_consumer.mlir
M mlir/test/Dialect/SparseTensor/sorted_coo.mlir
M mlir/test/Dialect/SparseTensor/sparse_1d.mlir
M mlir/test/Dialect/SparseTensor/sparse_2d.mlir
M mlir/test/Dialect/SparseTensor/sparse_3d.mlir
M mlir/test/Dialect/SparseTensor/sparse_affine.mlir
M mlir/test/Dialect/SparseTensor/sparse_batch.mlir
M mlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_fusion.mlir
M mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels_to_iterator.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
M mlir/test/Dialect/SparseTensor/sparse_nd.mlir
M mlir/test/Dialect/SparseTensor/sparse_outbuf.mlir
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
M mlir/test/Dialect/SparseTensor/sparse_parallel_reduce.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_scalars.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm_org.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_index.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
M mlir/test/Dialect/SparseTensor/unused-tensor.mlir
M mlir/test/Dialect/SparseTensor/vectorize_reduction.mlir
M mlir/test/Dialect/Tensor/bufferize.mlir
A mlir/test/Dialect/Tensor/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/bufferize.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
M mlir/test/Integration/Dialect/Tosa/CPU/test-maxpool-dynamic.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/mulf-full.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/muli-full.mlir
Log Message:
-----------
[mlir][bufferization] Fix OneShotBufferize when `defaultMemorySpaceFn` is used (#91524)
As described in issue llvm/llvm-project#91518, a previous PR
llvm/llvm-project#78484 introduced the `defaultMemorySpaceFn` into
bufferization options, allowing one to inform OneShotBufferize that it
should use a specified function to derive the memory space attribute
from the encoding attribute attached to tensor types.
However, introducing this feature exposed unhandled edge cases,
examples of which are introduced by this change in the new test under
`test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir`.
Fixing the inconsistencies introduced by `defaultMemorySpaceFn` is
pretty simple. This change:
- Updates the `bufferization.to_memref` and `bufferization.to_tensor`
operations to explicitly include operand and destination types,
whereas previously they relied on type inference to deduce the
tensor types. Since the type inference cannot recover the correct
tensor encoding/memory space, the operand and result types must be
explicitly included. This is a small assembly format change, but it
touches a large number of test files.
- Makes minor updates to other bufferization functions to handle the
changes in building the above ops.
- Updates bufferization of `tensor.from_elements` to handle memory
space.
Integration/upgrade guide:
In downstream projects, if you have tests or MLIR files that explicitly
use
`bufferization.to_tensor` or `bufferization.to_memref`, then update
them to the new assembly format as follows:
```
%1 = bufferization.to_memref %0 : memref<10xf32>
%2 = bufferization.to_tensor %1 : memref<10xf32>
```
becomes
```
%1 = bufferization.to_memref %0 : tensor<10xf32> to memref<10xf32>
%2 = bufferization.to_tensor %0 : memref<10xf32> to tensor<10xf32>
```
Commit: 2a0162c0193a73ef16aee67dbe66abb9d2e4717c
https://github.com/llvm/llvm-project/commit/2a0162c0193a73ef16aee67dbe66abb9d2e4717c
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll
Log Message:
-----------
[AArch64][SVE] Change the immediate argument in svextq (#115340)
In order to align with `svext` and NEON `vext`/`vextq`, this patch
changes immediate argument in `svextq` such that it refers to elements
of the size of those of the source vector, rather than bytes. The [spec
for this
intrinsic](https://github.com/ARM-software/acle/blob/main/main/acle.md#extq)
is ambiguous about the meaning of this argument, this issue was raised
after there was a differing interpretation for it from the implementers
of the ACLE in GCC.
For example (with our current implementation):
`svextq_f64(zn_f64, zm_f64, 1)` would, for each 128-bit segment of
`zn_f64,` concatenate the highest 15 bytes of this segment with the
first byte of the corresponding segment of `zm_f64`.
After this patch, the behavior of `svextq_f64(zn_f64, zm_f64, 1)` would
be, for each 128-bit vector segment of `zn_f64`, to concatenate the
higher doubleword of this segment with the lower doubleword of the
corresponding segment of `zm_f64`.
The range of the immediate argument in `svextq` would be modified such
that it is:
- [0,15] for `svextq_{s8,u8}`
- [0,7] for `svextq_{s16,u16,f16,bf16}`
- [0,3] for `svextq_{s32,u32,f32}`
- [0,1] for `svextq_{s64,u64,f64}`
Commit: bf440f75b485e4ea7f809dc37df74cac140069fd
https://github.com/llvm/llvm-project/commit/bf440f75b485e4ea7f809dc37df74cac140069fd
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[Clang][NFC] Remove trailing whitespace from Attr{,Docs}.td
Commit: b1a34b80b83156540519110cc798969dcfe1aec9
https://github.com/llvm/llvm-project/commit/b1a34b80b83156540519110cc798969dcfe1aec9
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/PowerPC/gcov_ctr_ref_init.ll
Log Message:
-----------
[NFC][Test] Fix PowerPC test gcov_ctr_ref_init.ll (#117577)
Commit: c55a080c080ed76a9aabe6dcd1966fedc0ecda5a
https://github.com/llvm/llvm-project/commit/c55a080c080ed76a9aabe6dcd1966fedc0ecda5a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Add shuffle coverage for compress, decompress, and repeat idioms
compress is intented to match vcompress from the ISA manual. Note that
deinterleave is a subset of this, and is already tested elsewhere.
decompress is the synthetic pattern defined in same - though we can often
do better than the mentioned iota/vrgather. Note that some of these
can also be expressed as interleave with at least one undef source,
and is already tested elsewhere.
repeat repeats each input element N times in the output. It can be
described as as a interleave operations, but we can sometimes do
better lowering wise.
Commit: 5a3299a684d7d8c40f48d732e5b80a8bd29aa882
https://github.com/llvm/llvm-project/commit/5a3299a684d7d8c40f48d732e5b80a8bd29aa882
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
Log Message:
-----------
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
We should leave these for EXPENSIVE_CHECKS builds. Some of these
were near the top of slowest tests.
Commit: 4ab298b5fbc8f48387062b2dd99ea07127c02e6b
https://github.com/llvm/llvm-project/commit/4ab298b5fbc8f48387062b2dd99ea07127c02e6b
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.h
Log Message:
-----------
[LLDB][ThreadELFCore] Set all the properties of ELFLinuxSigInfo to a non build dependent size (#117604)
On #110065 the changes to LinuxSigInfo Struct introduced some variables
that will differ in size on 32b or 64b. I've rectified this by setting
them all to build independent types.
Commit: 5fd4f32f985f83414d82a1c2c55741e363693352
https://github.com/llvm/llvm-project/commit/5fd4f32f985f83414d82a1c2c55741e363693352
Author: Zhengxing li <zhengxingli at microsoft.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/invalid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
Log Message:
-----------
[HLSL] Implement SV_GroupID semantic (#115911)
Support SV_GroupID attribute.
Translate it into dx.group.id in clang codeGen.
Fixes: #70120
Commit: 78c7024640a5b511685c445f554b7d985a7cf286
https://github.com/llvm/llvm-project/commit/78c7024640a5b511685c445f554b7d985a7cf286
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-default-clause.c
A clang/test/SemaOpenACC/combined-construct-present-ast.cpp
A clang/test/SemaOpenACC/combined-construct-present-clause.c
A clang/test/SemaOpenACC/combined-construct-present-clause.cpp
Log Message:
-----------
[OpenACC] Implement 'present' for combined constructs.
This is another clause where the parsing does all the required
enforcement besides the construct it appertains to, so this patch
removes the restriction and adds sufficient test coverage for combined
constructs.
Commit: 5683fc5cc043d1f43294bc57e04a901ad8cafcf5
https://github.com/llvm/llvm-project/commit/5683fc5cc043d1f43294bc57e04a901ad8cafcf5
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Log Message:
-----------
[gn] port a5dd6463608b
Commit: 752ef93392b2d049064dc77087bf414d69283cfc
https://github.com/llvm/llvm-project/commit/752ef93392b2d049064dc77087bf414d69283cfc
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/MC/AArch64/local-bounds-single-trap.ll
Log Message:
-----------
[NFC][clang] Fix header comment in llvm/test/MC/AArch64/local-bounds-single-trap.ll (#117642)
llvm/test/MC/AArch64/local-bounds-single-trap.ll was introduced in
https://github.com/llvm/llvm-project/pull/65972 to demonstrate that
nomerge did not work properly, which is documented in the header
comment.
https://github.com/llvm/llvm-project/pull/101549 fixed nomerge for trap
builtins and
https://github.com/llvm/llvm-project/commit/ae6dc64ec670891cb15049277e43133d4df7fb4b
updated the test assertions, but not the header comment. This patch
updates the header comment accordingly.
Commit: 5bdcaf1a0804799106bc864215ba03af4b762966
https://github.com/llvm/llvm-project/commit/5bdcaf1a0804799106bc864215ba03af4b762966
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/docs/GitHub.rst
Log Message:
-----------
[github] Document the process for requesting the CI/CD role (#115321)
See https://discourse.llvm.org/t/rfc-proposing-a-new-ci-cd-admin-for-the-project
Commit: 44ef12b020c07d195519d0613d21f3b8ab29a22d
https://github.com/llvm/llvm-project/commit/44ef12b020c07d195519d0613d21f3b8ab29a22d
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A libcxx/test/std/containers/sequences/vector/addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_copy.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_size_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.special/swap.addressof.compile.pass.cpp
Log Message:
-----------
[libc++] Refactor tests for hijacked address operator in vector (#117457)
This reduces the amount of boilerplate needed to implement the tests.
Commit: e57b327be27bd185595a3383dfac90ec6651c123
https://github.com/llvm/llvm-project/commit/e57b327be27bd185595a3383dfac90ec6651c123
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
Log Message:
-----------
AMDGPU: Legalize fminimum and fmaximum f32 for gfx950 (#117634)
Select to minimum3/maximum3. Leave f16/v2f16 for later
since it's complicated by only having the vector version.
Commit: f5e92eb04b5d9b708d38e3616df998ecdf9afc20
https://github.com/llvm/llvm-project/commit/f5e92eb04b5d9b708d38e3616df998ecdf9afc20
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
Log Message:
-----------
AMDGPU: Handle f32 minimum3/maximum3 pattern for gfx950 (#117737)
Commit: 7221bc74bc6b038b40c00d5111555ea87b326bf3
https://github.com/llvm/llvm-project/commit/7221bc74bc6b038b40c00d5111555ea87b326bf3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
Log Message:
-----------
AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (#117738)
Commit: 815069c701d62b58b8dbb6e902931f9eb5185db4
https://github.com/llvm/llvm-project/commit/815069c701d62b58b8dbb6e902931f9eb5185db4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for: v_cvt_scalef32_[f16|f32]_[bf8|fp8] (#117739)
OPSEL[1:0] collectively decide which byte to read
from src input.
Builtin takes additional imm argument which
represents index (with valid values:[0:3]) of src
byte read. Out of bounds checks will added in next
patch.
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Inst{13} i.e. OPSEL[2] is ignored in
asm syntax and opsel[z] is meaningless
for v_cvt_scalef32_f32_{fp|bf}8
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 803bd812b16d1454b8fc0d6d66d7da793408b34d
https://github.com/llvm/llvm-project/commit/803bd812b16d1454b8fc0d6d66d7da793408b34d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_{fp8|bf8}_f32 for gfx950 (#117740)
OPSEL[3] determines low/high 16 bits of word to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c9562b181cafafba104cccd7334ace1fd6aee5ac
https://github.com/llvm/llvm-project/commit/c9562b181cafafba104cccd7334ace1fd6aee5ac
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
Log Message:
-----------
[gn] port 3cb28522ba4c
Commit: c71418574f1bb9e4678428901775c8b633cded09
https://github.com/llvm/llvm-project/commit/c71418574f1bb9e4678428901775c8b633cded09
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/complex/generic/CMakeLists.txt
M libc/src/pthread/CMakeLists.txt
M libc/src/setjmp/riscv/CMakeLists.txt
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/stdfix/CMakeLists.txt
M libc/src/string/CMakeLists.txt
M libc/src/threads/CMakeLists.txt
M libc/test/src/math/smoke/LdExpTest.h
Log Message:
-----------
[libc] suppress more clang-cl warnings (#117718)
- migrate more `-O3` to `${libc_opt_high_flag}`
- workaround a issue with `LLP64` in test. The overflow testing is
guarded by a constexpr but the literal overflow itself will still
trigger warnings.
Notice that for math smoke test, for some reasons, the
`${libc_opt_high_flag}` will be passed into `lld-link` which confuses
the linker so there are still some warnings leftover there. I can
investigate more when I have time.
Commit: 0719b6d936d628c4c1765a9e700387ddd77759b9
https://github.com/llvm/llvm-project/commit/0719b6d936d628c4c1765a9e700387ddd77759b9
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
R clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RWBuffer-AST.hlsl
R clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
A clang/test/AST/HLSL/TypedBuffers-AST.hlsl
Log Message:
-----------
[HLSL][NFC] Refactor resource buffers AST tests (#117659)
This is a test-only change. This PR merges 5 tests for structured
buffers ASTs into one file with multiple run lines and check prefixes
because these tests have a lot of common output. It also renames
RWBuffer-AST.hlsl to TypedBuffers-AST.hlsl and makes it ready to include
testing of other typed buffers as well.
Fixes #115412
Commit: 46a08579f2b86e39b367b83ff4ca0e92302d2168
https://github.com/llvm/llvm-project/commit/46a08579f2b86e39b367b83ff4ca0e92302d2168
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/GVN/noalias.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-loads.ll
M llvm/test/Transforms/NewGVN/noalias.ll
Log Message:
-----------
[Local] Only intersect alias.scope,noalias & parallel_loop if inst moves (#117716)
Preserve !alias.scope, !noalias and !mem.parallel_loop_access metadata
on the replacement instruction, if it does not move. In that case, the
program would be UB, if the aliasing property encoded in the metadata
does not hold. This makes use of the clarification re aliasing metadata
implying UB if the property does not hold: #116220
Same as #115868, but for !alias.scope, !noalias and
!mem.parallel_loop_access.
PR: https://github.com/llvm/llvm-project/pull/117716
Commit: cefc1b0c211fcc3f5528b72d5883f0c390d63e71
https://github.com/llvm/llvm-project/commit/cefc1b0c211fcc3f5528b72d5883f0c390d63e71
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/aa-recursion-assertion-failure.ll
M llvm/test/Transforms/MergedLoadStoreMotion/st_sink_debuginvariant.ll
M llvm/test/Transforms/NewGVN/2010-03-31-RedundantPHIs.ll
M llvm/test/Transforms/NewGVN/2010-05-08-OneBit.ll
M llvm/test/Transforms/NewGVN/2011-04-27-phioperands.ll
M llvm/test/Transforms/NewGVN/2012-05-22-PreCrash.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/completeness.ll
M llvm/test/Transforms/NewGVN/crash.ll
M llvm/test/Transforms/NewGVN/deadstore.ll
M llvm/test/Transforms/NewGVN/eliminate-ssacopy.ll
M llvm/test/Transforms/NewGVN/metadata-nonnull.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-move-block.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
M llvm/test/Transforms/NewGVN/pr25440.ll
M llvm/test/Transforms/NewGVN/pr31594.ll
M llvm/test/Transforms/NewGVN/pr31613.ll
M llvm/test/Transforms/NewGVN/pr31682.ll
M llvm/test/Transforms/NewGVN/pr32403.ll
M llvm/test/Transforms/NewGVN/pr32838.ll
M llvm/test/Transforms/NewGVN/pr32845.ll
M llvm/test/Transforms/NewGVN/pr32897.ll
M llvm/test/Transforms/NewGVN/pr32934.ll
M llvm/test/Transforms/NewGVN/pr33014.ll
M llvm/test/Transforms/NewGVN/pr33086.ll
M llvm/test/Transforms/NewGVN/pr33116.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33204.ll
M llvm/test/Transforms/NewGVN/pr33432.ll
M llvm/test/Transforms/NewGVN/pr33720.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr35074.ll
M llvm/test/Transforms/NewGVN/pr42422-phi-of-ops.ll
M llvm/test/Transforms/NewGVN/pr43441.ll
M llvm/test/Transforms/NewGVN/pre-new-inst-xfail.ll
M llvm/test/Transforms/NewGVN/predicates.ll
M llvm/test/Transforms/NewGVN/refine-stores.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` from some regression tests [NFC] (#117292)
This PR removes tests with `br i1 undef` under
`llvm/tests/Transforms/MemCpyOpt, MergedLoadStoreMotion, NewGVN`.
Commit: 5ce981e76da4094efd055ded54d1f756b1286f18
https://github.com/llvm/llvm-project/commit/5ce981e76da4094efd055ded54d1f756b1286f18
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__vector/vector.h
M libcxx/test/std/containers/sequences/vector/vector.cons/exceptions.pass.cpp
Log Message:
-----------
[libc++] Refactor vector move constructor with allocator (#116449)
This PR simplifies the implementation of std::vector's move constructor
with an alternative allocator by invoking __init_with_size() instead of
calling assign(), which ultimately calls __assign_with_size(). The
advantage of using __init_with_size() lies in its internal use of
an exception guard, which simplifies the code. Furthermore, from a
semantic standpoint, it is more intuitive for a constructor to call
an initialization function than an assignment function.
Commit: 9118d3a564f271006b0d8aed0983f7ba025e77a0
https://github.com/llvm/llvm-project/commit/9118d3a564f271006b0d8aed0983f7ba025e77a0
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
Log Message:
-----------
gn build: Fix port of 3cb28522ba4c
COMPILER_RT_EXEC_OUTPUT_DIR is expected to be the path where
hwasan_symbolize is installed, i.e. the bin subdirectory of the
build directory, but we were incorrectly setting it to the install
location of the runtime libraries. Fix it.
Commit: 105b7803ea22823a2fca2a82ee843d0884e9cbf3
https://github.com/llvm/llvm-project/commit/105b7803ea22823a2fca2a82ee843d0884e9cbf3
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port f9dca5bdbb0f
Commit: 8458bbe5947db75041579c7c1a0f7f79c8e992d9
https://github.com/llvm/llvm-project/commit/8458bbe5947db75041579c7c1a0f7f79c8e992d9
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__split_buffer
Log Message:
-----------
[libc++] Fix capacity increase issue with `shrink_to_fit` for `__split_buffer` (#117720)
This PR fixes the issue where `__split_buffer::shrink_to_fit` may
unexpectedly increase the capacity, similar to the issue for
`std::vector` in #97895. The fix follows the same approach
used in #97895 for `std::vector`.
Commit: 003b48e0cbbb69a9a1ca9ff1a6d3bda30d0c6121
https://github.com/llvm/llvm-project/commit/003b48e0cbbb69a9a1ca9ff1a6d3bda30d0c6121
Author: Raul Tambre <raul at tambre.ee>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/test/AArch64/data-at-0-offset.c
M bolt/test/AArch64/double_jump.cpp
M bolt/test/R_ABS.pic.lld.cpp
M bolt/test/X86/double-jump.test
M bolt/test/X86/dwarf5-df-inlined-subroutine-gc-sections-range.test
M bolt/test/X86/jmp-optimization.test
M bolt/test/X86/match-functions-with-call-graph.test
M bolt/test/pie.test
M bolt/test/runtime/X86/instrumentation-indirect.c
M bolt/test/runtime/bolt-reserved.cpp
Log Message:
-----------
[BOLT][test] enable GNU extensions, use C++ compiler, remove unnecessary target (#117043)
1. With a Clang that doesn't default to GNU extensions they need to be enabled explicitly.
2. The X86 directory lit config sets it already, there's no reason for this test to do it by itself.
3. The C frontend executable will fail if there's for example a Clang resource file for the C++ mode that sets C++-specific options:
```
+ /home/tambre/dev/llvm/build/bin/clang --target=x86_64-unknown-linux-gnu -fPIE -fuse-ld=lld -Wl,--unresolved-symbols=ignore-all -pie -fPIC -shared /home/tambre/dev/llvm/bolt/test/R_ABS.pic.lld.cpp -o /home/tambre/dev/llvm/build/tools/bolt/test/Output/R_ABS.pic.lld.cpp.tmp.so -Wl,-q -fuse-ld=lld
clang: warning: argument unused during compilation: '-pie' [-Wunused-command-line-argument]
error: invalid argument '-std=c23' not allowed with 'C++'
```
Commit: 2d90af59084d842a343f9acf6ae7c1e61991873c
https://github.com/llvm/llvm-project/commit/2d90af59084d842a343f9acf6ae7c1e61991873c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Parser/unparse.cpp
A flang/test/Parser/OpenMP/bind-clause.f90
Log Message:
-----------
[flang][OpenMP] Add unparsing of BIND clause argument (#117776)
Currently the argument of the BIND clause is not printed. This is likely
an omission in the original implementation.
Commit: 1b68b33ac0b3c2c8bd2ab89fec4f516f622cebdf
https://github.com/llvm/llvm-project/commit/1b68b33ac0b3c2c8bd2ab89fec4f516f622cebdf
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge (#117649)
This test (copied from https://github.com/llvm/llvm-project/pull/83470)
demonstrates that UBSan does not add the nomerge annotation. This is
significant because it can result in them being merged by the backend,
even when -ubsan-unique-traps is enabled.
N.B. https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011.
https://github.com/llvm/llvm-project/pull/101549 fixed that limitation
("It sets nomerge flag for the node if the instruction has nomerge
arrtibute."); planned upcoming work
(https://github.com/llvm/llvm-project/pull/117651) will add nomerge for
ubsan.
Commit: dde7f4d024d071d883cfb7812f31866e767b6ab9
https://github.com/llvm/llvm-project/commit/dde7f4d024d071d883cfb7812f31866e767b6ab9
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A llvm/test/CodeGen/X86/ubsan-trap-merge.ll
A llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
Log Message:
-----------
[NFC][clang] Add ubsan-trap-merge.ll test to show absence of nomerge considered harmful (#117657)
These testcases demonstrate that ubsan intrinsics are merged in the
backend iff nomerge is missing from ubsantrap intrinsics.
This is based on the observation and testcase by Vitaly Buka in
https://github.com/llvm/llvm-project/pull/83470.
Commit: 81349b84eb0fd2d64f836ddbf3e28638d4a254b8
https://github.com/llvm/llvm-project/commit/81349b84eb0fd2d64f836ddbf3e28638d4a254b8
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
Log Message:
-----------
[sanitizer] Use /tmp/ not /tmp/dir/ in tests (#117759)
Tests fail if the user doesn't own /tmp/dir/. On hosts with multiple
users running the test suite, who owns /tmp/dir/ can become a race.
Commit: c8bdb31ff66e8934060c60816c57925fdec42a2c
https://github.com/llvm/llvm-project/commit/c8bdb31ff66e8934060c60816c57925fdec42a2c
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
R clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
Revert "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge" (#117804)
Reverts llvm/llvm-project#117649
Reason: buildbot breakage:
https://lab.llvm.org/buildbot/#/builders/144/builds/12581
Commit: 8ffe63fb556915c041e8e9bc2d1bf4325f12ba26
https://github.com/llvm/llvm-project/commit/8ffe63fb556915c041e8e9bc2d1bf4325f12ba26
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
Log Message:
-----------
[nfc][asan] Fix typo in comment
Commit: 5add295fd77e29f090515668f95d362d98583856
https://github.com/llvm/llvm-project/commit/5add295fd77e29f090515668f95d362d98583856
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use IndexedMemProfRecord in MemProfReader (NFC) (#117613)
IndexedMemProfRecord contains a complete package of the MemProf
profile, including frames, call stacks, and records. This patch
replaces the three member variables of MemProfReader with
IndexedMemProfRecord.
This transition significantly simplies both the constructor and the
final "take" method:
MemProfReader(IndexedMemProfData MemProfData)
: MemProfData(std::move(MemProfData)) {}
IndexedMemProfData takeMemProfData() { return std::move(MemProfData); }
Commit: 36a46d85e75e3be35c6b62002717f531b86d8368
https://github.com/llvm/llvm-project/commit/36a46d85e75e3be35c6b62002717f531b86d8368
Author: Omar Hossam <moar.ahmed at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
A libc/src/sys/mman/linux/process_mrelease.cpp
A libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
A libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
[libc] Implement process_mrelease. (#117503)
This PR addresses #110124.
Commit: 9fde1a498f2dc97a737a3564cb427c6f2a7bfe6c
https://github.com/llvm/llvm-project/commit/9fde1a498f2dc97a737a3564cb427c6f2a7bfe6c
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
Log Message:
-----------
[HLSL] Forward arguments in BuiltinTypeMethodBuilder::callBuiltin. NFC (#117789)
Introduce BuiltinTypeMethodBuilder::PlaceHolder values and use them in
the callBuiltin method in order to specify how we want to forward
arguments and pass the resource handle to builtins.
Commit: 09e7477c0f1f192d3e5bb9735301c2deec9a3d96
https://github.com/llvm/llvm-project/commit/09e7477c0f1f192d3e5bb9735301c2deec9a3d96
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
Log Message:
-----------
[memprof] Add a default constructor to Frame (#117790)
This patch adds a default constructor to Frame along with a use in
FrameIdConverter.
The real intent is to facilitate deserialization of YAML-based MemProf
format. Note that the YAML parser default-constructs a struct and
then populates one field at a time.
Commit: 7ae61a36f94679370b9c1b4b1a13999d23d38a0c
https://github.com/llvm/llvm-project/commit/7ae61a36f94679370b9c1b4b1a13999d23d38a0c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/detected_or.h
M libcxx/include/module.modulemap
Log Message:
-----------
[libc++] Add __detected_or_t and use it to implement some of the allocator traits aliases (#115654)
This simplifies the implementation a bit, since we don't need a lot of
the `__has_x` classes anymore. We just need two template aliases to
implement the `allocator_traits` aliases now.
Commit: 39601a6e5484de183bf525b7d0624e7890ccd8ab
https://github.com/llvm/llvm-project/commit/39601a6e5484de183bf525b7d0624e7890ccd8ab
Author: AdityaK <hiraditya at msn.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/SimplifyCFG/switch-branch-fold-indirectbr-102351.ll
Log Message:
-----------
Bail out jump threading on indirect branches only (#117778)
Remove check for PHI in pred as pointed out in #103688
Reduced the testcase to remove redundant phi in pred
Fixes: #102351
Commit: 47dbf359041299c5f19f82e7204c6c9675b6e69a
https://github.com/llvm/llvm-project/commit/47dbf359041299c5f19f82e7204c6c9675b6e69a
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A clang/test/CodeGen/ubsan-trap-merge.c
Log Message:
-----------
Reapply "[NFC][clang] Add ubsan-trap-merge.c test to show absence of nomerge" (#117804) (#117805)
This reverts commit c8bdb31ff66e8934060c60816c57925fdec42a2c.
It was reverted because I forgot to update the auto-generated assertions
after adding the target triple.
Original commit message:
This test (copied from https://github.com/llvm/llvm-project/pull/83470)
demonstrates that UBSan does not add the nomerge annotation. This is
significant because it can result in them being merged by the backend,
even when -ubsan-unique-traps is enabled.
N.B. https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011.
https://github.com/llvm/llvm-project/pull/101549 fixed that limitation
("It sets nomerge flag for the node if the instruction has nomerge
arrtibute."); planned upcoming work
(https://github.com/llvm/llvm-project/pull/117651) will add nomerge for
ubsan.
Commit: e1af76cad265694f1799d46de455f18c931ae2b7
https://github.com/llvm/llvm-project/commit/e1af76cad265694f1799d46de455f18c931ae2b7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 7ae61a36f946
Commit: 3372303188df0f7f8ac26e7ab610cf8b0f716d42
https://github.com/llvm/llvm-project/commit/3372303188df0f7f8ac26e7ab610cf8b0f716d42
Author: lntue <lntue at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/syscall.h.def
M libc/newhdrgen/yaml/sys/mman.yaml
M libc/spec/linux.td
M libc/src/sys/mman/CMakeLists.txt
M libc/src/sys/mman/linux/CMakeLists.txt
R libc/src/sys/mman/linux/process_mrelease.cpp
R libc/src/sys/mman/process_mrelease.h
M libc/test/src/sys/mman/linux/CMakeLists.txt
R libc/test/src/sys/mman/linux/process_mrelease_test.cpp
Log Message:
-----------
Revert "[libc] Implement process_mrelease." (#117807)
Reverts llvm/llvm-project#117503
Commit: 3a8b28f69837f8502c7bce798509f8dadb314dcc
https://github.com/llvm/llvm-project/commit/3a8b28f69837f8502c7bce798509f8dadb314dcc
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan] Add ioctl interceptor (#117569)
Commit: 3359806817d5d3a600e3f0bdae60ac3df1c85e7f
https://github.com/llvm/llvm-project/commit/3359806817d5d3a600e3f0bdae60ac3df1c85e7f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
Log Message:
-----------
[mlir][LLVM][MemRef] Lower assume_alignment with operand bundles (#117800)
Now that LLVM allows a operand bundle on assume calls to directly
specify alignment assumptions, change the lowering of
memref.assume_alignment to use that feature instead of the ptrtoint
method.
This makes LLVM's job easier and prevents issues when dealing with
cases where ptrtoint isn't a desired operation (like those with poiner
provenance)
Commit: e84614833e52ce9a7bebfa8d0d1af3298b6977b9
https://github.com/llvm/llvm-project/commit/e84614833e52ce9a7bebfa8d0d1af3298b6977b9
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/div.ll
Log Message:
-----------
[LLVM][NVPTX] Add support for div.full instruction (#116482)
This commit adds NVPTX support for div.full PTX instruction with test
under div.ll. [For more information, see PTX
ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-div)
Commit: 06d24da1312aa5c0c615a3b6c4dffe1c104e0cf3
https://github.com/llvm/llvm-project/commit/06d24da1312aa5c0c615a3b6c4dffe1c104e0cf3
Author: B I Mohammed Abbas <bimohammadabbas at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M compiler-rt/test/builtins/Unit/extendhfxf2_test.c
M compiler-rt/test/builtins/Unit/fp_test.h
Log Message:
-----------
Fix extendhfxf2 test (#117665)
Fix changes in #113897
Co-authored-by: Alex Richardson <alexrichardson at google.com>
Commit: a94cec521202b00d18eaa55d9a5a4616097f5abf
https://github.com/llvm/llvm-project/commit/a94cec521202b00d18eaa55d9a5a4616097f5abf
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
Revert "[libc++] Remove workaround which allows setting _LIBCPP_OVERRIDABLE_FUNC_VIS externally (#113139)" (#117779)
This reverts commit 2e686d6d17c4cc7608510a856055e6ca79fcb917.
See https://github.com/llvm/llvm-project/issues/117571
Commit: 43b6b78771e9ab4da912b574664e713758c43110
https://github.com/llvm/llvm-project/commit/43b6b78771e9ab4da912b574664e713758c43110
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
Log Message:
-----------
[RISCV][GISel] Use libcalls for f32/f64 G_FCMP without F/D extensions. (#117660)
LegalizerHelp only supported f128 libcalls and incorrectly assumed that
the destination register for the G_FCMP was s32.
Commit: 06514c550105b3111c23751421265c318bd69ac6
https://github.com/llvm/llvm-project/commit/06514c550105b3111c23751421265c318bd69ac6
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/IR/AffineMap.h
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/test/Dialect/Linalg/fusion-elementwise.mlir
Log Message:
-----------
[MLIR][Linalg] Fix linalg crash during elementwise op fusion (#117667)
`isOpOperandCanBeDroppedAfterFusedLinalgs` crashes when `indexingMaps`
is empty. This can occur when `producer` only has DPS init operands and
`consumer ` only has a single DPS input operand (all operands are
ignored and nothing gets added to `indexingMaps`). This is because
`concatAffineMaps` wasn't handling the maps being empty properly.
Similar to `canOpOperandsBeDroppedImpl`, I added an early return when
the maps are of size zero. Additionally, `concatAffineMaps`'s
declaration comment says it returns an empty map when `maps` is empty
but it has no way to get the `MLIRContext` needed to construct the empty
affine map when the array is empty. So, I changed this to take the
context.
__NOTE: concatAffineMaps now takes an MLIRContext to be able to
construct an empty map in the case where `maps` is empty.__
---------
Signed-off-by: Ian Wood <ianwood2024 at u.northwestern.edu>
Co-authored-by: Quinn Dawkins <quinn.dawkins at gmail.com>
Commit: 5147e5941d40ae89b6ecab89aa36f8f5def28f1e
https://github.com/llvm/llvm-project/commit/5147e5941d40ae89b6ecab89aa36f8f5def28f1e
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
A llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/lib/DebugInfo/GSYM/CMakeLists.txt
A llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-dsym.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-exe.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-obj.test
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
Log Message:
-----------
[GSYM] Callsites: Add data format support and loading from YAML (#109781)
This PR adds support in the gSYM format for call site information and
adds support for loading call sites from a YAML file. The support for
YAML input is mostly for testing purposes - so we have a way to test the
functionality.
Note that this data is not currently used in the gSYM tooling - the
logic to use call sites will be added in a later PR.
The reason why we need call site information in gSYM files is so that we
can support better call stack function disambiguation in the case where
multiple functions have been merged due to optimization (linker ICF).
When resolving a merged function on the callstack, we can use the call
site information of the calling function to narrow down the actual
function that is being called, from the set of all merged functions.
See [this
RFC](https://discourse.llvm.org/t/rfc-extending-gsym-format-with-call-site-information-for-merged-function-disambiguation/80682)
for more details on this change.
Commit: 62584f32eb786e4c455092e653a58182e8ffe4dc
https://github.com/llvm/llvm-project/commit/62584f32eb786e4c455092e653a58182e8ffe4dc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scalef32_pk_f32_{fp8|bf8} for gfx950 (#117741)
OPSEL[0] determines low/high 16 bits of src0 to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 4527894143a2749d826769e78ab4e0f50782b188
https://github.com/llvm/llvm-project/commit/4527894143a2749d826769e78ab4e0f50782b188
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950 (#117742)
OPSEL[3] determines low/high 16 bits of word to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 2b9e947d4346ad03328a31f90b9056837c042d1b
https://github.com/llvm/llvm-project/commit/2b9e947d4346ad03328a31f90b9056837c042d1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & Codegen support for v_cvt_scale_fp4<->f32 for gfx950 (#117743)
OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d]
where, c & d i.e. OPSEL[3 : 2] selects which dst_byte to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: eeb76880f3489f1e7e6224a26ec4abc7f6da4e34
https://github.com/llvm/llvm-project/commit/eeb76880f3489f1e7e6224a26ec4abc7f6da4e34
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{f|bf}16_fp4 for gfx950 (#117744)
OPSEL ASM Syntax for v_cvt_scalef32_pk_{f|bf}16_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 0f4fcca546a489f50535086a313f8c054ea41791
https://github.com/llvm/llvm-project/commit/0f4fcca546a489f50535086a313f8c054ea41791
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk32_f32_[fp|bf]6 for gfx950 (#117745)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 991dcbc468763953f4b4e65fa3448e147cba5bba
https://github.com/llvm/llvm-project/commit/991dcbc468763953f4b4e65fa3448e147cba5bba
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & codegen support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 for gfx950 (#117747)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 065dc93d9626930b48f8e88b1e0a18c746951ce0
https://github.com/llvm/llvm-project/commit/065dc93d9626930b48f8e88b1e0a18c746951ce0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (#117793)
OPSEL[0] selects src_word to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: c8ee1ee0571c5e49bee42983a8b9d8db0243c001
https://github.com/llvm/llvm-project/commit/c8ee1ee0571c5e49bee42983a8b9d8db0243c001
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (#117794)
These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
OPSEL ASM OPSEL Syntax: opsel:[a,b,c,d]
a & b are meaningless, c & d together decides byte to write in dst reg.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 175e0dd4223b7678f660519a9342282e8b226093
https://github.com/llvm/llvm-project/commit/175e0dd4223b7678f660519a9342282e8b226093
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
Log Message:
-----------
[MachineLateInstrsCleanup] Minor fixing (NFC). (#117816)
With cb57b7a7, MachineLateInstrsCleanup switched to using a map to keep
track of kill flags to remedy compile time regressions seen with huge
functions. It seems that the comment above clearKillsForDef() became stale with
that commit, and also that one of the arguments to it became unused,
both of which this patch fixes.
Commit: d3c103b80e6e8b001c2a22bd2f7afbdcf1f7b70a
https://github.com/llvm/llvm-project/commit/d3c103b80e6e8b001c2a22bd2f7afbdcf1f7b70a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (#117795)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: e335563806e0466f33ecce80a9fd5a39a3aead47
https://github.com/llvm/llvm-project/commit/e335563806e0466f33ecce80a9fd5a39a3aead47
Author: David Truby <david.truby at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M flang/unittests/Runtime/CMakeLists.txt
M flang/unittests/Runtime/CommandTest.cpp
Log Message:
-----------
[NFC][flang] Fix execute_command_line test for odd environments (#117714)
One of the execute_command_line tests currently runs `cat` on an invalid
file and checks its return value, but since we don't control `cat` or
the user's path, the return value might not be reliably stable on a
per-platform basis. For example, if `git` is installed on Windows in
certain configurations it adds a directory to the path containing a
`cat` with a different set of error codes to the default Windows one.
This patch changes the test to use the `not` binary built by LLVM for
testing purposes, which should always return 1 on any platform
regardless of the user's environment.
Commit: 34a8bb0da33ce95aa4dec61ad24fbf4049176189
https://github.com/llvm/llvm-project/commit/34a8bb0da33ce95aa4dec61ad24fbf4049176189
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_sr_{f16|bf16}_f32 instructions (#117796)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: f87cabea26c3bcfdf9315c3ade2bf830692ddb3d
https://github.com/llvm/llvm-project/commit/f87cabea26c3bcfdf9315c3ade2bf830692ddb3d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (#117797)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 2ff2e871f5e632ea493efaf4f2192f8b18a54ab1
https://github.com/llvm/llvm-project/commit/2ff2e871f5e632ea493efaf4f2192f8b18a54ab1
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
Log Message:
-----------
[mlir][bufferization] Remove remaining dialect conversion-based infra parts (#114155)
This commit removes the last remaining components of the dialect
conversion-based bufferization passes.
Note for LLVM integration: If you depend on these components, migrate to
One-Shot Bufferize or copy them to your codebase.
Commit: 76715787f4c1e23a618bccdb81049456526f7b42
https://github.com/llvm/llvm-project/commit/76715787f4c1e23a618bccdb81049456526f7b42
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_pk_fp4 instructions (#117798)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: f2129ca94c47875b5f915abc9d7dfb02a7445fe6
https://github.com/llvm/llvm-project/commit/f2129ca94c47875b5f915abc9d7dfb02a7445fe6
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
Log Message:
-----------
[lldb][NFC] Whitespace fix for mis-indented block
This mis-indented block makes a FC change I'm about
to propose look larger than it is when clang-formatted.
Commit: 4d2bc0adc63cf90111d849911ccdddaa0d886e60
https://github.com/llvm/llvm-project/commit/4d2bc0adc63cf90111d849911ccdddaa0d886e60
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
Log Message:
-----------
[BOLT] Extract comparator for sorting functions by index into helper function (#116217)
This change extracts the comparator for sorting functions by index into
a helper function `compareBinaryFunctionByIndex()`
Not sure why the comparator used in
`BinaryContext::getSortedFunctions()` is not same as the other two
places. I think they should use the same comparator, so I also change
`BinaryContext::getSortedFunctions()` to use
`compareBinaryFunctionByIndex()` for sorting functions.
Commit: 3433e4140d18865fe784061a3cd029c5980f4e2f
https://github.com/llvm/llvm-project/commit/3433e4140d18865fe784061a3cd029c5980f4e2f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Bridge.cpp
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Detect constant on the rhs of data transfer (#117806)
When the rhs expression has some constants and a device symbol, an
implicit data transfer needs to be generated for the device symbol and
the computation with the constant is done on the host.
Commit: 0f0c0c36e3e90b4cb04004ed9c930f3863a36422
https://github.com/llvm/llvm-project/commit/0f0c0c36e3e90b4cb04004ed9c930f3863a36422
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/and-implied-by-operands.ll
M llvm/test/Transforms/ConstraintElimination/or.ll
Log Message:
-----------
[ConstraintElim] Extend `checkOrAndOpImpliedByOther` to handle and/or expr trees. (#117123)
This patch extends `checkOrAndOpImpliedByOther` to handle and/or trees.
Limitation: At least one of the operands of root and/or instruction
should be an icmp. That is, this patch doesn't support expressions like
`(cmp1 & cmp2) & (cmp3 & cmp4)`.
Closes https://github.com/llvm/llvm-project/issues/117107.
Compile-time impact:
http://llvm-compile-time-tracker.com/compare.php?from=69cc3f096ccbdef526bbd5a065a25c95122e87ee&to=919416d2c4c71e3b9fe533af2c168a36c7893be5&stat=instructions%3Au
Commit: ea58410d0fd75c9dc6d395bba15e939ed7c35cb1
https://github.com/llvm/llvm-project/commit/ea58410d0fd75c9dc6d395bba15e939ed7c35cb1
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/test/CodeGen/builtins-wasm.c
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
A llvm/test/CodeGen/WebAssembly/thread_pointer.ll
Log Message:
-----------
[WebAssembly] Implement %llvm.thread.pointer intrinsic (#117817)
We can simply use the `__tls_base` global for this which is guaranteed
to be non-zero and unique per thread.
Fixes: #117433
Commit: dd4844722d98a97edd180e20abd4e65e1e2dd9d7
https://github.com/llvm/llvm-project/commit/dd4844722d98a97edd180e20abd4e65e1e2dd9d7
Author: antangelo <contact at antangelo.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/IntrinsicLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
Log Message:
-----------
[SelectionDAG] Add generic implementation for @llvm.expect.with.probability when optimizations are disabled (#117459)
Handle \@llvm.expect.with.probability in SelectionDAGBuilder, FastISel,
and IntrinsicLowering in the same way \@llvm.expect is handled, where
the value is passed through as-is. This can be reached if the intrinsic
is used without optimizations, where it would otherwise be properly
transformed out.
Fixes #115411 for SelectionDAG. A similar patch is likely needed for
GlobalISel.
Commit: 73d1abb018fdd60664b49c3418572c2e04e18d41
https://github.com/llvm/llvm-project/commit/73d1abb018fdd60664b49c3418572c2e04e18d41
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/test/ELF/pack-dyn-relocs-tls-x86-64.s
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
Log Message:
-----------
[X86][LLD] Handle R_X86_64_CODE_4_GOTTPOFF relocation type (#116634)
For
mov name at GOTTPOFF(%rip), %reg
add name at GOTTPOFF(%rip), %reg
add
`R_X86_64_CODE_4_GOTTPOFF` = 44
in #116633.
Linker can treat `R_X86_64_CODE_4_GOTTPOFF` as `R_X86_64_GOTTPOFF` or
convert the instructions above to
mov $name, %reg
add $name, %reg
if the first byte of the instruction at the relocation `offset - 4` is
`0xd5` (namely, encoded w/REX2 prefix) when possible.
Binutils patch: https://github.com/bminor/binutils-gdb/commit/a533c8df598b5ef99c54a13e2b137c98b34b043c
Binutils mailthread: https://sourceware.org/pipermail/binutils/2023-December/131463.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/ACwD-UQXVDs/m/vrgTenKyFwAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: fad5ed6e908aafe03e47032611a6e836bbcc4d5a
https://github.com/llvm/llvm-project/commit/fad5ed6e908aafe03e47032611a6e836bbcc4d5a
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/test/ELF/invalid/x86-64-tlsdesc-gd.s
M lld/test/ELF/x86-64-tlsdesc-gd.s
Log Message:
-----------
[X86][LLD] Handle R_X86_64_CODE_4_GOTPC32_TLSDESC relocation type (#116909)
For
lea name at tlsdesc(%rip), %reg
add
R_X86_64_CODE_4_GOTPC32_TLSDESC = 45
in #116908.
Linker can treat R_X86_64_CODE_4_GOTPC32_TLSDESC as
R_X86_64_GOTPC32_TLSDESC or convert the instruction above to
mov $name at tpoff, %reg
if the first byte of the instruction at the relocation offset - 4 is
0xd5 (namely, encoded w/REX2 prefix) when possible.
Binutils patch: https://github.com/bminor/binutils-gdb/commit/a533c8df598b5ef99c54a13e2b137c98b34b043c
Binutils mailthread: https://sourceware.org/pipermail/binutils/2023-December/131463.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/ACwD-UQXVDs/m/vrgTenKyFwAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: b5825963f0f0d5e3fb8a0c0914bc5a27aa16440e
https://github.com/llvm/llvm-project/commit/b5825963f0f0d5e3fb8a0c0914bc5a27aa16440e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Materialize box when needed (#117810)
Materialize the box when the src comes from a embox or rebox operation.
This was done in the case of transfer to a descriptor but not when
transferring from a descriptor.
Commit: f9a39dfd18a1d428b5ec2ce38ad3b50ec6988e70
https://github.com/llvm/llvm-project/commit/f9a39dfd18a1d428b5ec2ce38ad3b50ec6988e70
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
Log Message:
-----------
[ORC] Fix typo in comment: instruction is ldr literal, not adr. NFC.
Commit: cc113102c6ea3d9d3d016c0804fee0c154f98ce1
https://github.com/llvm/llvm-project/commit/cc113102c6ea3d9d3d016c0804fee0c154f98ce1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/GSYM/BUILD.gn
Log Message:
-----------
[gn build] Port 5147e5941d40
Commit: 508448280a4fc8d1e29c5ccf883836aac0f11ec9
https://github.com/llvm/llvm-project/commit/508448280a4fc8d1e29c5ccf883836aac0f11ec9
Author: Helmut Januschka <helmut at januschka.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy] Enhance modernize-use-starts-ends-with to handle substr patterns (#116033)
Enhances the modernize-use-starts-ends-with check to detect additional patterns
using substr that can be replaced with starts_with() (C++20).
This enhancement improves code readability and can be more efficient by avoiding
temporary string creation.
Commit: 38a3cce90a2cc54ea9ad6bbdd63ccd61c32cfac9
https://github.com/llvm/llvm-project/commit/38a3cce90a2cc54ea9ad6bbdd63ccd61c32cfac9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
Log Message:
-----------
[RISCV][GISel] Copy fneg test cases from SelectionDAG into float/double-arith.ll. NFC
The test cases use fcmp which was not fully supported before
43b6b78771e9ab4da912b574664e713758c43110.
Commit: 90a776fbdb35ef6ac6f28a19937e88abd2e4611b
https://github.com/llvm/llvm-project/commit/90a776fbdb35ef6ac6f28a19937e88abd2e4611b
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
Log Message:
-----------
[clang][RISCV] __riscv_v_intrinsic macro doesn't need zve32x (#117356)
This macro is used to check if compiler supports RVV intrinsics, so it
should be defined no matter vector is enabled or not.
Resolved https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/376
Commit: 74449ab86b8bc8d7388ede0cc7fc3a679da0c567
https://github.com/llvm/llvm-project/commit/74449ab86b8bc8d7388ede0cc7fc3a679da0c567
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/lib/Serialization/ASTReader.cpp
M clang/test/Modules/explicit-build-missing-files.cpp
M clang/test/Modules/load_failure.c
M clang/test/Modules/mismatch-diagnostics.cpp
M clang/test/Modules/module-feature.m
M clang/test/Modules/pr62359.cppm
M clang/test/Modules/prebuilt-implicit-modules.m
M clang/test/PCH/arc.m
M clang/test/PCH/no-validate-pch.cl
M clang/test/PCH/pch-dir.c
Log Message:
-----------
[Serialization] Downgrade inconsistent flags from erros to warnings (#115416)
There were many many "voices" about the too strict flags checking in
modules. Although they rarely challenge this, maybe due to they respect
to the compiler implementation details. But from my point of view, there
are cases it is "fine" to have different flags. Especially we're too
conservative to mark almost language options in
`clang/include/clang/Basic/LangOptions.def` as incompatible options (see
the comments in the front of the file).
In my understanding, this should come from PCH initially since it is
natural to ask your headers to be compiled with the same flags with your
TU. And then, when Apple and Google goes to implement clang module, they
don't challenge it too since they have a closed world where they have a
strong control over the ecosystem so that they can make it consistent.
Yes, consistency is great and ODR violation are awful. But this is the
world we're living today. This is the C++'s ecosystem in the open ended
world. Image a situation that we're using a third party module and we
add a new option to our library, then the build bails out! THIS IS SUPER
ANNOYING. And makes it non practical to make a modular C++ ecosystem.
(
This was discussed many times in SG15. And the consensus is, the build
systems should generate different BMI based on different flags. But this
manner can't avoid ODR violation completely and it would add the times
of module files that need to be built, which may kill the benefit of
faster compilation of modules.
However, I think the build systems may need to do the similar things in
the end of the day. Considering libc++'s hardening mechanism
(https://libcxx.llvm.org/Hardening.html). So the conclusion of the
paragraph is, although this seems related to build systems, I think they
are actually unrelated story.
)
I think we should give our users a chance to disable such checks. It is
theoretically unsafe. But we've done our job to tell the users that it
**MAY** be bad. Then I feel it is C++-ish to give users more freedom
even if they may shoot their foot.
This shouldn't change any thing. Users who want previous behavior can
get it easily by `-Werror=`.
Commit: 4a7dbede6badd27ce2ad07984134d5d25a2bbada
https://github.com/llvm/llvm-project/commit/4a7dbede6badd27ce2ad07984134d5d25a2bbada
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Support `svukte` extension (#115657)
This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564,
https://lf-riscv.atlassian.net/browse/RVS-2977
The spec states that the `svukte` depends on `sv39`, but we don't have
`sv39` yet, so I didn't add it to the implied list.
Commit: 99de065b850b6e1c5461325998a40c6925d7ee9e
https://github.com/llvm/llvm-project/commit/99de065b850b6e1c5461325998a40c6925d7ee9e
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSerializationKinds.td
M clang/lib/Serialization/ASTReader.cpp
M clang/test/Modules/explicit-build-missing-files.cpp
M clang/test/Modules/load_failure.c
M clang/test/Modules/mismatch-diagnostics.cpp
M clang/test/Modules/module-feature.m
M clang/test/Modules/pr62359.cppm
M clang/test/Modules/prebuilt-implicit-modules.m
M clang/test/PCH/arc.m
M clang/test/PCH/no-validate-pch.cl
M clang/test/PCH/pch-dir.c
Log Message:
-----------
Revert "[Serialization] Downgrade inconsistent flags from erros to warnings (#115416)"
This reverts commit 74449ab86b8bc8d7388ede0cc7fc3a679da0c567.
See the post commit message in
https://github.com/llvm/llvm-project/pull/115416
Commit: 512defe603dd0c82fb49bc6a3e1e8481ac0f6f9e
https://github.com/llvm/llvm-project/commit/512defe603dd0c82fb49bc6a3e1e8481ac0f6f9e
Author: antangelo <contact at antangelo.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
Log Message:
-----------
[NFC][GISel][AArch64] Pre-commit baseline tests for translation of @llvm.expect.with.probability (#117842)
Pre-commit of tests for generic GlobalISel translation of
`@llvm.expect.with.probability` for when optimizations are not enabled
Commit: 301c8e60474e09e0e537316cef6218c14562a9b9
https://github.com/llvm/llvm-project/commit/301c8e60474e09e0e537316cef6218c14562a9b9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add support for v_cvt_scalef32_sr instructions (#117820)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 265e209ceba8c330403d77f46a33b8e138c5633f
https://github.com/llvm/llvm-project/commit/265e209ceba8c330403d77f46a33b8e138c5633f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_sr_{bf8|fp8}_{f16|bf16|f32} (#117821)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: 142b33c58b26aae4d27f3f063eb492256beda3a6
https://github.com/llvm/llvm-project/commit/142b33c58b26aae4d27f3f063eb492256beda3a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
Log Message:
-----------
AMDGPU: Allocate different registers for vdst & src in v_cvt_scalef32* (#117822)
For multipass instructions, overlap on VDST and SRC’s
would result in HW race & undefined results.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 62dc8f3069cb08f9c955435e03a30c59228c6bb6
https://github.com/llvm/llvm-project/commit/62dc8f3069cb08f9c955435e03a30c59228c6bb6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
Log Message:
-----------
AMDGPU: Add builtins & codegen support for bitop3_b{16|32} of gfx950. (#117823)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 561565720954a2de31ac8dfdb4fdd02ce1780030
https://github.com/llvm/llvm-project/commit/561565720954a2de31ac8dfdb4fdd02ce1780030
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
Log Message:
-----------
AMDGPU: Builtin & CodeGen support for v_cvt_sr_{bf16|f16}_f32 instructions (#117824)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: a2c3e0c4cb08e9cf26f4a745777295e1eb562e1b
https://github.com/llvm/llvm-project/commit/a2c3e0c4cb08e9cf26f4a745777295e1eb562e1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
A clang/test/SemaOpenCL/builtins-amdgcn-wave32-func-attr.cl
Log Message:
-----------
AMDGPU/clang: Add global_load_lds size check support for gfx950 (#117825)
Co-authored-by: Shilei Tian <shilei.tian at amd.com>
Commit: d9c4e9ffe78c34db247b164aa46eea2625b08d3a
https://github.com/llvm/llvm-project/commit/d9c4e9ffe78c34db247b164aa46eea2625b08d3a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/MC/AMDGPU/mai-gfx950-err.s
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
Log Message:
-----------
AMDGPU: Verify f8f6f4 formats in assembler (#117826)
Verify the register widths of the corresponding operands match
the floating point format expected size.
Commit: 61a23646c977f5530829742fdf5b901b7d9815a2
https://github.com/llvm/llvm-project/commit/61a23646c977f5530829742fdf5b901b7d9815a2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
M llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
A llvm/test/CodeGen/Generic/sjlj-eh-prepare.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
M llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll
M llvm/test/CodeGen/X86/sjlj-eh.ll
Log Message:
-----------
[SjLjEHPrepare] Configure call sites correctly (#117656)
After 9fe78db4, the pass inserts `store volatile i32 -1, ptr %call_site`
before all invoke instruction except the one in the entry block, which
has the effect of bypassing landing pads on exceptions.
When configuring the call site for a potentially throwing instruction
check that it is not `InvokeInst` -- they are handled by earlier code.
Commit: bc1e0c53a281822e08df89a02b02b6b0db222087
https://github.com/llvm/llvm-project/commit/bc1e0c53a281822e08df89a02b02b6b0db222087
Author: Josh Stone <jistone at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M compiler-rt/test/profile/Linux/binary-id-offset.c
Log Message:
-----------
[profile] Make the binary-id-offset.c test more robust (#117647)
Using a `--section-start` address in the test was causing link errors on
some targets. Now it uses a linker script to move the note after `.bss`,
which should still have the kind of memory offset we're looking for.
This is a follow-up to #114907 to fix buildbot errors.
Commit: 0d15d46362bd6ab5a9a2165805adaab13a7689f4
https://github.com/llvm/llvm-project/commit/0d15d46362bd6ab5a9a2165805adaab13a7689f4
Author: Thurston Dang <thurston at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/CodeGen/bounds-checking.c
M clang/test/CodeGen/catch-undef-behavior.c
M clang/test/CodeGen/ubsan-trap-merge.c
M llvm/test/CodeGen/X86/ubsan-trap-merge.ll
M llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
Log Message:
-----------
[ubsan] Change ubsan-unique-traps to use nomerge instead of counter (#117651)
https://github.com/llvm/llvm-project/pull/65972 (continuation of
https://reviews.llvm.org/D148654) had considered adding nomerge to
ubsantrap, but did not proceed with that because of
https://github.com/llvm/llvm-project/issues/53011. Instead, it added a
counter (based on TrapBB->getParent()->size()) to each ubsantrap call.
However, this counter is not guaranteed to be unique after inlining, as
shown by https://github.com/llvm/llvm-project/pull/83470, which can
result in ubsantraps being merged by the backend.
https://github.com/llvm/llvm-project/pull/101549 has since fixed the
nomerge limitation ("It sets nomerge flag for the node if the
instruction has nomerge arrtibute."). This patch therefore takes
advantage of nomerge instead of using the counter, guaranteeing that the
ubsantraps are not merged.
This patch is equivalent to
https://github.com/llvm/llvm-project/pull/83470 but also adds nomerge
and updates tests (https://github.com/llvm/llvm-project/pull/117649:
ubsan-trap-merge.c; https://github.com/llvm/llvm-project/pull/117657:
ubsan-trap-merge.ll, ubsan-trap-nomerge.ll; catch-undef-behavior.c).
Commit: 40d0058e6ad16d4716192a0e331ac58a6ed9def3
https://github.com/llvm/llvm-project/commit/40d0058e6ad16d4716192a0e331ac58a6ed9def3
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
A llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor reduction intrinsics (#116854)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.reduce.1D -> 5D variants, supporting both Tile
and Im2Col modes.
* These intrinsics optionally support cache_hints as indicated by the
boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in
cp-async-bulk-tensor-reduce.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 24eb2ae0a1803f0279facaca50001a1900d6bb85
https://github.com/llvm/llvm-project/commit/24eb2ae0a1803f0279facaca50001a1900d6bb85
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
Log Message:
-----------
[NVPTX] Fix a warning
This patch fixes:
llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp:452:3:
error: default label in switch which covers all enumeration values
[-Werror,-Wcovered-switch-default]
Commit: 6934870a134ce9000752f0613295596fb876e5c6
https://github.com/llvm/llvm-project/commit/6934870a134ce9000752f0613295596fb876e5c6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
AMDGPU: Remove FeatureCvtFP8VOP1Bug from gfx950 (#117827)
Commit: b4a16a78c2626d56864d4d6c0f9b2779e293914a
https://github.com/llvm/llvm-project/commit/b4a16a78c2626d56864d4d6c0f9b2779e293914a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/bitop3.ll
Log Message:
-----------
AMDGPU: Match and Select BITOP3 on gfx950 (#117843)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 53c0a25db7a0469f6d47e130d5a0e8f7a88b9585
https://github.com/llvm/llvm-project/commit/53c0a25db7a0469f6d47e130d5a0e8f7a88b9585
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
Log Message:
-----------
[LoongArch] Use div.w/mod.w to eliminate unnecessary sign-extend for sdiv/srem i32. (#117298)
Commit: 3618c9930f70b13b4e678ac04cb9f813056d560c
https://github.com/llvm/llvm-project/commit/3618c9930f70b13b4e678ac04cb9f813056d560c
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[MISched] Use right boundary when trying latency heuristics (#116592)
We may do bottom-up or bidirectional scheduling but previously we
assume we are doing top-down scheduling, which may cause some issues.
Commit: 6c7b988e64b60cff7e9f3777dfcc2b2511ee48c6
https://github.com/llvm/llvm-project/commit/6c7b988e64b60cff7e9f3777dfcc2b2511ee48c6
Author: 루밀LuMir <rpfos at naver.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M clang/tools/clang-format/git-clang-format
Log Message:
-----------
[clang-format] Add mjs to default_extensions in git-clang-format (#117730)
Commit: 50dfb0772b3995c6e5543600b2813f56d0736442
https://github.com/llvm/llvm-project/commit/50dfb0772b3995c6e5543600b2813f56d0736442
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV] Support f32/f64 libcalls for sin/cos/pow/log/log2/log10/exp/exp2
Test cases copied from SelectionDAG.
Commit: c00e53208db638c35499fc80b555f8e14baa35f0
https://github.com/llvm/llvm-project/commit/c00e53208db638c35499fc80b555f8e14baa35f0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-26 (Tue, 26 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Add YAML-based deserialization for MemProf profile (#117829)
This patch adds YAML-based deserialization for MemProf profile.
It's been painful to write tests for MemProf passes because we do not
have a text format for the MemProf profile. We would write a test
case in C++, run it for a binary MemProf profile, and then finally run
a test written in LLVM IR with the binary profile.
This patch paves the way toward YAML-based MemProf profile.
Specifically, it adds new class YAMLMemProfReader derived from
MemProfReader. For now, it only adds a function to parse StringRef
pointing to YAML data. Subseqeunt patches will wire it to
llvm-profdata and read from a file.
The field names are based on various printYAML functions in MemProf.h.
I'm not aiming for compatibility with the format used in printYAML,
but I don't see a point in changing the field names.
Commit: e636434bdf74cf40071b776ef05aafbf161ce4cd
https://github.com/llvm/llvm-project/commit/e636434bdf74cf40071b776ef05aafbf161ce4cd
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
Log Message:
-----------
[BasicAA][LAA] Don't use same-block phis in cross iteration mode (#116802)
In 4de3184f07fd8c548125d315dd306d4afa7c9698 we exposed BasicAA's
cross-iteration mode for use in LAA, so we can handle selects with equal
conditions correctly (where the select condition is not actually equal
across iterations).
However, if we replace the selects with equivalent phis, the issue still
exists. In the phi case, we effectively still have an assumption that
the condition(s) that control which phi arg is used will be the same
across iterations. Fix this by disabling this phi handling in
cross-iteration mode.
(I'm not entirely sure whether this is also needed when BasicAA enables
cross-iteration mode during internal phi recursion, but I wouldn't be
surprised if that's the case.)
Commit: 204d7153629db22c44a313733a5469cd6f7056df
https://github.com/llvm/llvm-project/commit/204d7153629db22c44a313733a5469cd6f7056df
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][vector] Add more tests for ConvertVectorToLLVM (11/n) (#117160)
Adds tests with scalable vectors for the Vector-To-LLVM conversion pass.
Covers the following Ops:
* `vector.splat`.
In addition:
* Removed `@make_fixed_vector_of_scalable_vect`, which duplicated
`@broadcast_vec2d_from_scalar_scalable` (and wasn't grouped with other
tests for `vector.broadcast`).
* Moved `@vector_bitcast_2d` near other tests for `vector.bitcast` and
added a variant with scalable vectors.
Commit: 4dfa0216ba7849fde270f27e2358d4327fac988d
https://github.com/llvm/llvm-project/commit/4dfa0216ba7849fde270f27e2358d4327fac988d
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/string.c
M clang/test/Analysis/string.cpp
A clang/test/Analysis/string_notnullterm.c
Log Message:
-----------
[clang][analyzer] Bring checker 'alpha.unix.cstring.NotNullTerminated' out of alpha (#113899)
Commit: 072387042021b0f74c24c617b940fe8157f9f1a5
https://github.com/llvm/llvm-project/commit/072387042021b0f74c24c617b940fe8157f9f1a5
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/Socket.h
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
Log Message:
-----------
[lldb] Add timeout argument to Socket::Accept (#117691)
Allows us to stop waiting for a connection if it doesn't come in a
certain amount of time. Right now, I'm keeping the status quo (infitnite
wait) in the "production" code, but using smaller (finite) values in
tests. (A lot of these tests create "loopback" connections, where a
really short wait is sufficient: on linux at least even a poll (0s wait)
is sufficient if the other end has connect()ed already, but this doesn't
seem to be the case on Windows, so I'm using a 1s wait in these cases).
Commit: e8a01e75e6b17e84710e7cc3bfb70d95a3a696a2
https://github.com/llvm/llvm-project/commit/e8a01e75e6b17e84710e7cc3bfb70d95a3a696a2
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/include/lldb/Symbol/Block.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
Log Message:
-----------
[lldb] Make sure Blocks always have a parent (#117683)
It's basically true already (except for a brief time during
construction). This patch makes sure the objects are constructed with a
valid parent and enforces this in the type system, which allows us to
get rid of some nullptr checks.
Commit: 7e312c3b90cad9358d863b9b74de75d4da632845
https://github.com/llvm/llvm-project/commit/7e312c3b90cad9358d863b9b74de75d4da632845
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
Revert "[memprof] Add YAML-based deserialization for MemProf profile (#117829)"
This reverts commit c00e53208db638c35499fc80b555f8e14baa35f0.
It looks like this breaks building LLVM on macOS and some other
platform/compiler combos
https://lab.llvm.org/buildbot/#/builders/23/builds/5252
https://green.lab.llvm.org/job/llvm.org/job/clang-san-iossim/5356/console
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/lib/ProfileData/MemProfReader.cpp:34:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/MemProfReader.h:24:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/InstrProfReader.h:22:
In file included from /Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/InstrProfCorrelator.h:21:
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:1173:36: error: implicit instantiation of undefined template 'llvm::yaml::MissingTrait<unsigned long>'
char missing_yaml_trait_for_type[sizeof(MissingTrait<T>)];
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:961:7: note: in instantiation of function template specialization 'llvm::yaml::yamlize<unsigned long>' requested here
yamlize(*this, Val, Required, Ctx);
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:883:11: note: in instantiation of function template specialization 'llvm::yaml::IO::processKey<unsigned long, llvm::yaml::EmptyContext>' requested here
this->processKey(Key, Val, true, Ctx);
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/ProfileData/MIBEntryDef.inc:55:1: note: in instantiation of function template specialization 'llvm::yaml::IO::mapRequired<unsigned long>' requested here
MIBEntryDef(AccessHistogram = 27, AccessHistogram, uintptr_t)
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/lib/ProfileData/MemProfReader.cpp:77:8: note: expanded from macro 'MIBEntryDef'
Io.mapRequired(KeyStr.str().c_str(), MIB.Name); \
^
/Users/ec2-user/jenkins/workspace/llvm.org/clang-san-iossim/llvm-project/llvm/include/llvm/Support/YAMLTraits.h:310:8: note: template is declared here
struct MissingTrait;
^
1 error generated.
Commit: 17b87853c3b07b8e1c7f000c3818efab7fdd8883
https://github.com/llvm/llvm-project/commit/17b87853c3b07b8e1c7f000c3818efab7fdd8883
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/source/Host/windows/MainLoopWindows.cpp
Log Message:
-----------
[lldb] Fix premature MainLoop wakeup on windows (#117756)
The windows system APIs only take milliseconds. Make sure we round the
sleep interval (in nanoseconds) upwards.
Commit: 427be0767523b6e0f4004a421892f463d62446ac
https://github.com/llvm/llvm-project/commit/427be0767523b6e0f4004a421892f463d62446ac
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mlamcas.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
A llvm/test/Transforms/AtomicExpand/LoongArch/atomicrmw-expand.ll
Log Message:
-----------
[LoongArch] Support amcas[_db].{b/h/w/d} instructions. (#114189)
Two options for clang: -mlamcas & -mno-lamcas.
Enable or disable amcas[_db].{b/h} instructions.
The default is -mno-lamcas.
Only works on LoongArch64.
Commit: eb001820b47176fc3e7bc643525c6352b76dcd1d
https://github.com/llvm/llvm-project/commit/eb001820b47176fc3e7bc643525c6352b76dcd1d
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/temp/temp.deduct.guide/p3.cpp
Log Message:
-----------
[Clang] prevent errors for deduction guides using deduced type aliases (#117450)
Fixes #54909
---
Clang incorrectly produces diagnostics for alias templates in deduction
guides, treating them as separate from their underlying types. This
issue arises because Clang doesn't properly handle
`TypeAliasTemplateDecl` when comparing template names for equality in
the context of deduction guides, resulting in diagnostics that don't
align with the C++ standard. As the C++ standard specifies - _an alias
template is considered a synonym for its underlying type_
With this change, Clang now correctly resolves alias templates to their
underlying types in deduction guides, ensuring compliance with the C++
standard.
Commit: 74392bde2e603c8ca3f0956d4c55ba181fe9989b
https://github.com/llvm/llvm-project/commit/74392bde2e603c8ca3f0956d4c55ba181fe9989b
Author: Maurice Heumann <MauriceHeumann at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Headers/intrin.h
Log Message:
-----------
[X86] Consistently use __inline__ keyword in intrin.h (#117856)
Using `inline` instead of `__inline__` may cause duplicate symbol errors in some scenarios.
This fixes #117854
Commit: 712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
https://github.com/llvm/llvm-project/commit/712ef7d0baf9b7b6c2a3f01f0c02305a0e0160e9
Author: David Green <david.green at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
Log Message:
-----------
[AArch64][GlobalISel] Fix smull and umull intrinsics.
These were the wrong way around somehow, with aarch64_neon_umull being converted
to G_SMULL.
Commit: 345b3319c8544a0124aed9602c31f8793228ab63
https://github.com/llvm/llvm-project/commit/345b3319c8544a0124aed9602c31f8793228ab63
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
Log Message:
-----------
[AMDGPU][SplitModule] Fix unintentional integer division (#117586)
A static analysis tool warned that a division was always being performed
in integer division, so was either 0.0 or 1.0.
This doesn't seem intentional, so has been fixed to return a true ratio
using floating-point division. This in turn showed a bug where a
comparison against this ratio was incorrect.
Commit: 1fccba5ca1997db13cfa88f788b7acb8cc300b48
https://github.com/llvm/llvm-project/commit/1fccba5ca1997db13cfa88f788b7acb8cc300b48
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
Log Message:
-----------
[AArch64][PAC] Eliminate excessive MOVs when computing blend (#115185)
As function calls do not generally preserve X16 and X17, it is beneficial
to allow AddrDisc operand of BLRA instruction to reside in these
registers and make use of this condition when computing the
discriminator.
This can save up to two MOVs in cases such as loading a (signed) virtual
function pointer via a (signed) pointer to vtable, for example
ldr x9, [x16]
mov x8, x16
mov x17, x8
movk x17, #34646, lsl #48
blraa x9, x17
can be simplified to
ldr x8, [x16]
movk x16, #34646, lsl #48
blraa x8, x16
Commit: c979ec05642f292737d250c6682d85ed49bc7b6e
https://github.com/llvm/llvm-project/commit/c979ec05642f292737d250c6682d85ed49bc7b6e
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Reland - [Offload] Introduce offload-tblgen and initial new API implementation (#108413) (#117704)
Relands changes from #108413 - this was reverted due to build issues.
The problem was just that the `offload-tblgen` tool was behind recent
changes to tablegen that ensure `const` records. This has been fixed and
the PR is otherwise identical.
___
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
# From the runtime build directory
$ ninja LibomptUnitTests
$ OFFLOAD_TRACE=1 ./offload/unittests/OffloadAPI/offload.unittests
```
### Open questions and future work
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: fc5c89900f2a4b50e0f3a88ef7c89115d93684f4
https://github.com/llvm/llvm-project/commit/fc5c89900f2a4b50e0f3a88ef7c89115d93684f4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
A llvm/test/Transforms/SimpleLoopUnswitch/pr117537.ll
Log Message:
-----------
[SimpleLoopUnswitch] Fix LCSSA phi node invalidation
Fixes https://github.com/llvm/llvm-project/issues/117537.
Commit: 0cb5846a68cc5c5e519b2c80ab106e7e4fc6eedb
https://github.com/llvm/llvm-project/commit/0cb5846a68cc5c5e519b2c80ab106e7e4fc6eedb
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "Reland - [Offload] Introduce offload-tblgen and initial new API implementation (#108413) (#117704)"
This reverts commit c979ec05642f292737d250c6682d85ed49bc7b6e.
This showed failures in the post-merge CI.
Commit: f6f2929fc6fa39f62e2c3109b7a1b0f866c1c17b
https://github.com/llvm/llvm-project/commit/f6f2929fc6fa39f62e2c3109b7a1b0f866c1c17b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx2.s
Log Message:
-----------
[X86] Fix HSW/BDW masked store schedules
Vector masked stores don't use Port5 or Port 7.
Confirmed by augner/uops.info
Commit: 124b1f8d85af71e512e6dc6250c8bfa370a33d48
https://github.com/llvm/llvm-project/commit/124b1f8d85af71e512e6dc6250c8bfa370a33d48
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
Log Message:
-----------
[X86] Fix HSW/BDW shift/rotate by CL schedules
This is just Port06 not Port0156 - fixes reported thoughputs
Confirmed by augner/uops.info
Commit: 37aebcf4e60e5c913e3d99675548b3e2c631398b
https://github.com/llvm/llvm-project/commit/37aebcf4e60e5c913e3d99675548b3e2c631398b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/barrier_output.s
Log Message:
-----------
[X86] Cleanup SFENCE/MFENCE schedules
Remove unnecessary overrides.
UOp + Port usage confirmed by augner/uops.info
Commit: e874c8fc27bbc0e340691d5b5d01c7a1bd365890
https://github.com/llvm/llvm-project/commit/e874c8fc27bbc0e340691d5b5d01c7a1bd365890
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
[SelectOpt] Refactor to prepare for support more select-like operations (#117582)
* Enables conversion of several select-like instructions within one
group
* Any number of auxiliary instructions depending on the same condition
can be in between select-like instructions
* After splitting the basic block, move select-like instructions into
the relevant basic blocks and optimise them
* Make it easier to add support shift-base select-like instructions and
also any mixture of zext/sext/not instructions
Commit: 7b2a708a27da1cbdf16b912aa2c98e9718256596
https://github.com/llvm/llvm-project/commit/7b2a708a27da1cbdf16b912aa2c98e9718256596
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
M llvm/unittests/AsmParser/AsmParserTest.cpp
Log Message:
-----------
AsmParser: parse zeroinitializer, poison constants (#117809)
LLParser::parseConstantValue is missing support for parsing
zeroinitializer and poison constants. Fix this.
Commit: 284d4e0a7a789848b7af7f85158ccf522d70c6f0
https://github.com/llvm/llvm-project/commit/284d4e0a7a789848b7af7f85158ccf522d70c6f0
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/unittests/debugserver/RNBSocketTest.cpp
Log Message:
-----------
[lldb] Fix RNBSocketTest for #117691
Commit: 2eb40aadda48e4470bd1bf2cba90a7d593690a6b
https://github.com/llvm/llvm-project/commit/2eb40aadda48e4470bd1bf2cba90a7d593690a6b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/Analysis/MemorySSA/loop-unswitch.ll
M llvm/test/Analysis/MemorySSA/pr40037.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr46574.ll
M llvm/test/Analysis/MemorySSA/simple_loop_unswitch_nontrivial.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-13-SingleEntryPHI.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-27-DeadSwitchCase.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-Unreachable.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-tl.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-12-ExitDomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-13-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-18-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2008-06-02-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2010-11-18-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-06-02-CritSwitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-09-26-EHCrash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-04-02-IndirectBr.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-05-20-Phi.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2015-09-18-Addrspace.ll
M llvm/test/Transforms/SimpleLoopUnswitch/LIV-loop-condtion.ll
M llvm/test/Transforms/SimpleLoopUnswitch/cleanuppad.ll
M llvm/test/Transforms/SimpleLoopUnswitch/copy-metadata.ll
M llvm/test/Transforms/SimpleLoopUnswitch/crash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-behavior.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-cost.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-skip-selects-in-guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/preserve-analyses.ll
Log Message:
-----------
[SimpleLoopUnswitch] Use loop-mssa in more tests (NFC)
We had a lot of -verify-memoryssa tests that did not actually use
MemorySSA, because they were not using the loop-mssa adaptor.
Commit: f30f7a084c93bb7ef4983cda583985b56ad123d2
https://github.com/llvm/llvm-project/commit/f30f7a084c93bb7ef4983cda583985b56ad123d2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-half-conversions.ll
Log Message:
-----------
[X86] canonicalizeShuffleWithOp - initial support for shuffle(cvt(x),cvt(y)) -> cvt(shuffle(x,y))
Initial support is just for UNPCKL(CVTPH2PS(X),CVTPH2PS(Y)) -> CVTPH2PS(UNPCKL(X,Y))
Making this more general for other shuffles/conversions will have to be done carefully as we have to handle changes in src/dst element width, so I just handled the CVTPH2PS regression case.
Fixes #83414
Commit: dddeec4becabf71d4067080bcc2c09a9e67c3025
https://github.com/llvm/llvm-project/commit/dddeec4becabf71d4067080bcc2c09a9e67c3025
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/cxx-uninitialized-object-unguarded-access.cpp
A clang/test/Analysis/void-call-exit-modelling.c
Log Message:
-----------
[analyzer] Avoid out-of-order node traversal on void return (#117863)
The motivating example: https://compiler-explorer.com/z/WjsxYfs43
```C++
#include <stdlib.h>
void inf_loop_break_callee() {
void* data = malloc(10);
while (1) {
(void)data; // line 3
break; // -> execution continues on line 3 ?!!
}
}
```
To correct the flow steps in this example (see the fixed version in the
added test case) I changed two things in the engine:
- Make `processCallExit` create a new StmtPoint only for return
statements. If the last non-jump statement is not a return statement,
e.g. `(void)data;`, it is no longer inserted in the exploded graph after
the function exit.
- Skip the purge program points. In the example above, purge
points are still inserted after the `break;` executes. Now, when the bug
reporter is looking for the next statement executed after the function
execution is finished, it will ignore the purge program points, so it
won't confusingly pick the `(void)data;` statement.
CPP-5778
Commit: 318c69de52b61d64d5ea113dc2e9f307f7fd4d51
https://github.com/llvm/llvm-project/commit/318c69de52b61d64d5ea113dc2e9f307f7fd4d51
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
Reland "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)"
The issue with slow compile-time was caused by an assert in
AArch64RegisterInfo.cpp. The assert invokes 'checkAllSuperRegsMarked'
after adding all the reserved registers. This call gets very expensive
after adding the _HI registers due to the way the function searches
in the 'Exception' list, which is expected to be a small list but isn't
(the patch added 190 _HI regs).
It was possible to rewrite the code in such a way that the _HI registers
are marked as reserved after the check. This makes the problem go away
entirely and restores compile-time to what it was before (tested for
`check-runtimes`, which previously showed a ~5x slowdown).
This reverts commits:
1434d2ab215e3ea9c5f34689d056edd3d4423a78
2704647fb7986673b89cef1def729e3b022e2607
Commit: 66126c350f45617c10274cc36828bb1ec7ddbae4
https://github.com/llvm/llvm-project/commit/66126c350f45617c10274cc36828bb1ec7ddbae4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port 318c69de52b6
Commit: a807bbea6f48b368388cd796782724e3a53f58a0
https://github.com/llvm/llvm-project/commit/a807bbea6f48b368388cd796782724e3a53f58a0
Author: Victor Perez <victor.perez at codeplay.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUToLLVMSPV/CMakeLists.txt
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
Log Message:
-----------
[MLIR][GPUToLLVMSPV] Use `llvm.func` attributes to convert `gpu.shuffle` (#116967)
Use `llvm.func`'s `intel_reqd_sub_group_size` attribute instead of
SPIR-V environment attributes in the `gpu.shuffle` conversion pattern.
This metadata is needed to check the semantics of the operation are
supported, i.e., it has a constant width and its value is equal to the
sub-group size.
As the pass also converts `gpu.func` to `llvm.func`, adding a
discardable attribute of name `intel_reqd_sub_group_size` attribute to
the latter is enough for this pattern to work.
We no longer have a notion of "default" sub-group size, so this
attribute needs to be set in the parent function for `gpu.shuffle`
operations to be converted.
Drop dependency on the SPIR-V dialect as we no longer require creating
attributes from this dialect to lower `gpu.shuffle` instances.
---------
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Commit: 89b31c9c32f2cd2c038fe2b12d9c66a53c779fc1
https://github.com/llvm/llvm-project/commit/89b31c9c32f2cd2c038fe2b12d9c66a53c779fc1
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/declare-target-interface.f90
Log Message:
-----------
[Flang][OpenMP] Fix a crash for declare target in an interface (#117709)
This is a point fix for the crash in #116426. Leaving the bug open to
further explore declare target issues for interfaces.
Commit: 5eeb3fef61bf5542c3fdcb71622fc4e826527789
https://github.com/llvm/llvm-project/commit/5eeb3fef61bf5542c3fdcb71622fc4e826527789
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
R clang-tools-extra/CODE_OWNERS.TXT
A clang-tools-extra/Maintainers.txt
Log Message:
-----------
Rename CODE_OWNERS -> Maintainers (#114544)
Commit: 43ee6f7a01fca8cf08e1029c54acc23240b86fca
https://github.com/llvm/llvm-project/commit/43ee6f7a01fca8cf08e1029c54acc23240b86fca
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
Log Message:
-----------
[AlwaysInline] Avoid unnecessary BFI fetches (#117750)
AlwaysInliner doesn't use BFI itself, it only updates it. If BFI is not
already computed, it will spend time to first compute it, and then
update it. This is not necessary: If BFI is not available in the first
place, there is no need to update it.
This is mainly relevant in debug builds for IR that has a lot of
alwaysinline functions.
Commit: 8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
https://github.com/llvm/llvm-project/commit/8d6c73cbf53bd6eb410ac08836e7b128d4a99a16
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
Log Message:
-----------
[OpenACC] enable 'deviceptr' for combined constructs.
This is another clause whose implementation is identical for combined
constructs as with compute constructs, so this adds tests and enables
it.
Commit: 198fb5ed4ac7d096da03ea4a0a27832d18b1350f
https://github.com/llvm/llvm-project/commit/198fb5ed4ac7d096da03ea4a0a27832d18b1350f
Author: Samira Bazuzi <bazuzi at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
Log Message:
-----------
[clang][dataflow] Add captured parameters to ReferencedDecls for lamb… (#117771)
…da call operators.
This doesn't require that they be used in the operator's body, unlike
other ReferencedDecls. This is most obviously different from captured
local variables, which can be captured but will not appear in
ReferencedDecls unless they appear in the operator's body.
This difference simplifies the collection of the captured parameters,
but probably could be eliminated if desirable.
Commit: f67ba5855278401728413431216dda5d370ac2e0
https://github.com/llvm/llvm-project/commit/f67ba5855278401728413431216dda5d370ac2e0
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
Log Message:
-----------
[Clang] replace 'bitfield' with 'bit-field' for consistency (#117881)
Fixes #117711
Commit: 38049dc8eef0dca7e82c25e4012228a9a135e255
https://github.com/llvm/llvm-project/commit/38049dc8eef0dca7e82c25e4012228a9a135e255
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
Log Message:
-----------
[libc] Handle differing wavefront sizes correctly in the AMDHSA loader (#117788)
Summary:
The AMDGPU backend can handle wavefront sizes of 32 and 64, with the
native hardware preferring one or the other. The user can override the
hardware with `-mwavefrontsize64` or `-mwavefrontsize32` which
previously wasn't handled. We need to know the wavefront size to know
how much memory to allocate and how to index the RPC buffer. There isn't
a good way to do this with ROCm so we just use the LLVM support for
offloading to check this from the image.
Commit: 32ff209b87a84890a1487b4e0bbb4a7645d31645
https://github.com/llvm/llvm-project/commit/32ff209b87a84890a1487b4e0bbb4a7645d31645
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Analysis/Consumed.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
Log Message:
-----------
[Clang] skip consumed analysis for consteval conditions in control-flow terminators (#117403)
Fixes #117385
---
These changes extend the work done in #116513. The changes add
additional handling to ensure correct behavior by skipping further
checks when a **CFG** contains a `consteval` condition, where no
_explicit expression_ is present, which is required to proceed with
consumed analyses.
Commit: e98396f4846bfcaabe2c2ee568aab4b78655f307
https://github.com/llvm/llvm-project/commit/e98396f4846bfcaabe2c2ee568aab4b78655f307
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
Reapply [memprof] Add YAML-based deserialization for MemProf profile (#117829)
This patch adds YAML-based deserialization for MemProf profile.
It's been painful to write tests for MemProf passes because we do not
have a text format for the MemProf profile. We would write a test
case in C++, run it for a binary MemProf profile, and then finally run
a test written in LLVM IR with the binary profile.
This patch paves the way toward YAML-based MemProf profile.
Specifically, it adds new class YAMLMemProfReader derived from
MemProfReader. For now, it only adds a function to parse StringRef
pointing to YAML data. Subseqeunt patches will wire it to
llvm-profdata and read from a file.
The field names are based on various printYAML functions in MemProf.h.
I'm not aiming for compatibility with the format used in printYAML,
but I don't see a point in changing the field names.
This iteration works around the unavailability of
ScalarTraits<uintptr_t> on macOS.
Commit: 611f5b8ff913c21cfd85b0f4170ab880838a4c9e
https://github.com/llvm/llvm-project/commit/611f5b8ff913c21cfd85b0f4170ab880838a4c9e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A llvm/test/Transforms/GVN/setjmp.ll
Log Message:
-----------
[GVN] Add test for #116668 (NFC)
Commit: d668304998344d40c5a0b512fd0c0cb91e8d534c
https://github.com/llvm/llvm-project/commit/d668304998344d40c5a0b512fd0c0cb91e8d534c
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
Log Message:
-----------
[lld][MachO] Support `-allowable_client` (#117155)
Closes #117113.
Follow-up to #114638.
Commit: 969b7658fe34cf7638e1385d813e765a4c61dfc7
https://github.com/llvm/llvm-project/commit/969b7658fe34cf7638e1385d813e765a4c61dfc7
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
Log Message:
-----------
[OpenACC] Enable 'wait' for combined constructs
Once again a situation where the combined and compute do the exact same
thing as far as Sema/AST/etc is concerned, so this patch adds tests and
enables it.
Commit: 24593f1814dc02c7404526674838ccfb1c61d780
https://github.com/llvm/llvm-project/commit/24593f1814dc02c7404526674838ccfb1c61d780
Author: Saleem Abdulrasool <compnerd at compnerd.org>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M lldb/cmake/modules/LLDBConfig.cmake
Log Message:
-----------
[lldb] build: cleanup extraneous include paths (#117615)
Clean up some unnecessary include paths. The use of `LibXml2::LibXml2`
with `target_link_libraries` on `libLLDBHost` ensures that the header
search path is properly propagated.
Commit: 8358437bbb5b06d9aebc2940475a5a4d86c091c9
https://github.com/llvm/llvm-project/commit/8358437bbb5b06d9aebc2940475a5a4d86c091c9
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl]: Print stack-trace on crash (#117896)
Call `llvm::sys::PrintStackTraceOnErrorSignal` at the start of main to
1. Print a strack trace on crash
2. Disable the assertion failed popup in Windows Debug Builds
Other tools (for example clang-check or clang-query) already do this.
This fixes debug build bots on windows hanging (waiting for the popup to
be dismissed) and ultimately getting terminated due to timeout.
Commit: b71704436e61057a5bd6426915c368e5d76cb7de
https://github.com/llvm/llvm-project/commit/b71704436e61057a5bd6426915c368e5d76cb7de
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Simplify generated code for validateOperandClass (#117889)
Implement the register operand handling in validateOperandClass with a
table lookup instead of a potentially huge switch.
Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
Commit: 2f02b5af6ecb973d3a7faad9b0daff22646e724d
https://github.com/llvm/llvm-project/commit/2f02b5af6ecb973d3a7faad9b0daff22646e724d
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy][modernize-use-starts-ends-with] Fix operator rewriting false negative (#117837)
In C++20, `operator!=` can be rewritten by negating `operator==`. This
is the case for `std::string`, where `operator!=` is not provided hence
relying on this rewriting.
Cover this case by matching `binaryOperation` and adding one case to
`isNegativeComparison`.
Commit: 1e3e199ed9f214594e358eb0c7892cdedc703f7a
https://github.com/llvm/llvm-project/commit/1e3e199ed9f214594e358eb0c7892cdedc703f7a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[Sema] Migrate away from PointerUnion::{is,get} (NFC) (#117498)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: c29e895ad2bce8ca36debd8ef09d0540dabc99b6
https://github.com/llvm/llvm-project/commit/c29e895ad2bce8ca36debd8ef09d0540dabc99b6
Author: knickish <knickish at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
Log Message:
-----------
[M68k] Handle 16 bit MOVs to and from CCR (#114714)
Builds on @TechnoElf 's CCR MOV pr
https://github.com/llvm/llvm-project/pull/107591 and adds some tests.
Fixes https://github.com/llvm/llvm-project/issues/106210.
---------
Co-authored-by: TechnoElf <technoelf at undertheprinter.com>
Commit: 991154d0fbc951e2b999589a95dabc7deff7acd1
https://github.com/llvm/llvm-project/commit/991154d0fbc951e2b999589a95dabc7deff7acd1
Author: Krzysztof Pszeniczny <kpszeniczny at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionImport.cpp
Log Message:
-----------
[LTO] Use .at instead of .lookup to avoid copies. (NFC) (#117888)
`DenseMap::lookup` returns by value (because it default-creates the
returned value if the key isn't present in the map), which means that we
do a lot of copying here. Since we assert that something is present in
the returned value two lines below this call, it's safe to use `.at`
here instead.
Copying and then destroying dense maps here is responsible for 60% of
the time spent in LTO indexing in a large internal build.
Commit: b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
https://github.com/llvm/llvm-project/commit/b185b8512b2c7bf92ba87ea260a7b94d71dec4ee
Author: Bill Wendling <morbo at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/test/Sema/builtin-counted-by-ref.c
Log Message:
-----------
[Clang] Improve Sema diagnostic performance for __builtin_counted_by_ref (#116719)
Implement the sema checks with a placeholder. We then check for that
placeholder in all of the places we care to emit a diagnostic.
Fixes: #115520
Commit: a4751804985554815899b5dc1544e27139bacdc4
https://github.com/llvm/llvm-project/commit/a4751804985554815899b5dc1544e27139bacdc4
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
Log Message:
-----------
[PowerPC] Use setbc for values from vector compare conditions (#114858)
For P10 use the setbc instruction to get int values from vector compare
summary condition results.
Commit: 9d55e862d938c17a5e3f970326139c53b9aaf37e
https://github.com/llvm/llvm-project/commit/9d55e862d938c17a5e3f970326139c53b9aaf37e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Fix warnings on MSVC
MSVC doesn't seem to count a use in static_assert as a use.
Commit: 35a5c7129a32f7eedf2d1913447c53cee96eab13
https://github.com/llvm/llvm-project/commit/35a5c7129a32f7eedf2d1913447c53cee96eab13
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
Log Message:
-----------
[OpenACC] Add tests forgotten in 969b7658fe
Commit: bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
https://github.com/llvm/llvm-project/commit/bbbaeb5584b5f1ab38cc86a9e8ed64ec1dc926b6
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
Log Message:
-----------
[OpenACC] Enable 'attach' clause for combined constructs
Once again, this clause has the same implementation for compute
constructs as combined, so this adds the tests and enables it.
Commit: 87503fa51c8d726510d48e707a7d2885a5b5936c
https://github.com/llvm/llvm-project/commit/87503fa51c8d726510d48e707a7d2885a5b5936c
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
Log Message:
-----------
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
This reverts commit e9c49901a43f5b16c3df416460b7e4dbdd24ce03.
Current AMDGPURegBankSelect does nothing different then RegBankSelect.
Revert to using generic RegBankSelect in preparation for adding new
regbankselect passes. New AMDGPURegBankSelect, that will use uniformity
analysis for regbank select decisions, will not subclass RegBankSelect.
Revert regression tests to use regbankselect since amdgpu-regbankselect
will be used by new pass and behavior will be different.
Commit: 2e9469885d4572a2eedf2669190742c9e3272e6a
https://github.com/llvm/llvm-project/commit/2e9469885d4572a2eedf2669190742c9e3272e6a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 87503fa51c8d
Commit: dae9cf3816bbb2b4589d258a82e6ac90fad71485
https://github.com/llvm/llvm-project/commit/dae9cf3816bbb2b4589d258a82e6ac90fad71485
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
Log Message:
-----------
[RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC
Improves coverage for more configurations.
Commit: d7643e86100a3515660dc807c88eea79bf755016
https://github.com/llvm/llvm-project/commit/d7643e86100a3515660dc807c88eea79bf755016
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support f32/f64 llvm.exp10 intrinsics.
Commit: 1bc9de247477b58a14547a31047d1c9a365e2d5d
https://github.com/llvm/llvm-project/commit/1bc9de247477b58a14547a31047d1c9a365e2d5d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC
Commit: 92a15dd7482ff4e1fae7a07f888564e5b1d53eee
https://github.com/llvm/llvm-project/commit/92a15dd7482ff4e1fae7a07f888564e5b1d53eee
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][LLVM] Plumb range attributes on parameters and results through (#117801)
We've had the ability to define LLVM's `range` attribute through
#llvm.constant_range for some time, and have used this for some GPU
intrinsics. This commit allows using `llvm.range` as a parameter or
result attribute on function declarations and definitions.
Commit: 3ce8b7d2205507c91f1609337382ad950f3be805
https://github.com/llvm/llvm-project/commit/3ce8b7d2205507c91f1609337382ad950f3be805
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove inline call stacks (#117833)
Now that MemProf format version 1 has been removed, nobody uses:
- IndexedAllocationInfo::CallStack
- IndexedMemProfRecord::CallSites
This patch removed the dead struct fields.
You might notice that IndexedMemProfRecord::{clear,merge} do not
mention CallSiteIds at all. I think it's an oversight. clear doesn't
matter at the moment because we call it during serialization to reduce
memory footprint. merge is simply not as well tested as it should be.
I'll follow up with a separate patch to address these issues.
Commit: 82b437944e53afeb25dd85507664e2a980ddfe07
https://github.com/llvm/llvm-project/commit/82b437944e53afeb25dd85507664e2a980ddfe07
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use "using" directives in unit tests (NFC) (#117852)
This tests uses existing "using" directives to shorten unit tests.
- llvm::memprof::hashCallStack -> hashCallStack
- testing::Pair -> Pair
- testing::ElementsAreArray -> ElementsAre
- testing::Contains -> UnorderedElementsAre
Commit: 801c4bd8eea9ba8f7490b164aad0fc6b67cbb9b1
https://github.com/llvm/llvm-project/commit/801c4bd8eea9ba8f7490b164aad0fc6b67cbb9b1
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-27 (Wed, 27 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/AArch64/data-at-0-offset.c
M bolt/test/AArch64/double_jump.cpp
M bolt/test/R_ABS.pic.lld.cpp
M bolt/test/X86/double-jump.test
M bolt/test/X86/dwarf5-df-inlined-subroutine-gc-sections-range.test
M bolt/test/X86/jmp-optimization.test
M bolt/test/X86/match-functions-with-call-graph.test
M bolt/test/pie.test
M bolt/test/runtime/X86/instrumentation-indirect.c
M bolt/test/runtime/bolt-reserved.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
R bolt/unittests/Core/MemoryMaps.cpp
R clang-tools-extra/CODE_OWNERS.TXT
A clang-tools-extra/Maintainers.txt
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SanitizerCoverage.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/Analysis/FlowSensitive/ASTOps.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticASTKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/Consumed.cpp
M clang/lib/Analysis/FlowSensitive/ASTOps.cpp
M clang/lib/Analysis/FlowSensitive/Arena.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp
M clang/lib/Analysis/IntervalPartition.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Headers/intrin.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseHLSL.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCodeComplete.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Core/BugReporter.cpp
M clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/test/AST/ByteCode/c23.c
R clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RWBuffer-AST.hlsl
R clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
R clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
A clang/test/AST/HLSL/TypedBuffers-AST.hlsl
A clang/test/AST/ast-dump-cxx2b-deducing-this.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/copy-elision.cpp
M clang/test/Analysis/cxx-uninitialized-object-unguarded-access.cpp
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/string.c
M clang/test/Analysis/string.cpp
A clang/test/Analysis/string_notnullterm.c
A clang/test/Analysis/void-call-exit-modelling.c
A clang/test/C/C23/n2412.c
M clang/test/CXX/temp/temp.deduct.guide/p3.cpp
A clang/test/CodeCompletion/keywords-cxx20.cpp
A clang/test/CodeGen/AArch64/sme-inline-callees-streaming-attrs.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
M clang/test/CodeGen/attr-cpuspecific.c
M clang/test/CodeGen/bounds-checking.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/builtins-wasm.c
M clang/test/CodeGen/catch-undef-behavior.c
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
A clang/test/CodeGen/ubsan-trap-merge.c
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
A clang/test/CodeGenHLSL/resource-bindings.hlsl
A clang/test/CodeGenHLSL/semantics/SV_GroupID.hlsl
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/Driver/cuda-no-threadsafe-statics.cu
M clang/test/Driver/fveclib.c
M clang/test/Driver/hexagon-toolchain-linux.c
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mdiv32.c
A clang/test/Driver/loongarch-mlamcas.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Modules/compare-record.c
M clang/test/Modules/odr_hash.cpp
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
M clang/test/Sema/builtin-counted-by-ref.c
M clang/test/Sema/constant_builtins_vector.cpp
M clang/test/SemaCXX/constexpr-return-non-void-cxx2b.cpp
M clang/test/SemaCXX/warn-unused-private-field.cpp
A clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M clang/test/SemaHLSL/Semantics/entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/invalid_entry_parameter.hlsl
M clang/test/SemaHLSL/Semantics/valid_entry_parameter.hlsl
A clang/test/SemaOpenACC/combined-construct-attach-ast.cpp
A clang/test/SemaOpenACC/combined-construct-attach-clause.c
A clang/test/SemaOpenACC/combined-construct-attach-clause.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/combined-construct-deviceptr-clause.cpp
A clang/test/SemaOpenACC/combined-construct-present-ast.cpp
A clang/test/SemaOpenACC/combined-construct-present-clause.c
A clang/test/SemaOpenACC/combined-construct-present-clause.cpp
A clang/test/SemaOpenACC/combined-construct-wait-ast.cpp
A clang/test/SemaOpenACC/combined-construct-wait-clause.c
A clang/test/SemaOpenACC/combined-construct-wait-clause.cpp
M clang/test/SemaOpenACC/compute-construct-varlist-ast.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
A clang/test/SemaOpenCL/builtins-amdgcn-wave32-func-attr.cl
M clang/tools/clang-format/git-clang-format
M clang/tools/clang-repl/ClangRepl.cpp
M clang/unittests/Analysis/FlowSensitive/ASTOpsTest.cpp
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/interception_win.h
M compiler-rt/lib/interception/tests/interception_win_test.cpp
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/tests/sanitizer_libc_test.cpp
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
M compiler-rt/test/builtins/Unit/fp_test.h
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
M compiler-rt/test/profile/Linux/binary-id-offset.c
M flang/docs/Intrinsics.md
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td
M flang/include/flang/Runtime/CUDA/allocatable.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/Transforms/AddAliasTags.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/unparse.cpp
M flang/runtime/CUDA/allocatable.cpp
A flang/test/Analysis/AliasAnalysis/gen_mod_ref_test.py
A flang/test/Analysis/AliasAnalysis/modref-call-after-inlining.fir
A flang/test/Analysis/AliasAnalysis/modref-call-args.f90
A flang/test/Analysis/AliasAnalysis/modref-call-dummies.f90
A flang/test/Analysis/AliasAnalysis/modref-call-equivalence.f90
A flang/test/Analysis/AliasAnalysis/modref-call-globals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-internal-proc.f90
A flang/test/Analysis/AliasAnalysis/modref-call-locals.f90
A flang/test/Analysis/AliasAnalysis/modref-call-not-fortran.fir
M flang/test/Driver/print-supported-cpus.f90
M flang/test/Fir/CUDA/cuda-allocate.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
A flang/test/Fir/struct-return-aarch64.fir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/HLFIR/assumed-rank-internal-proc.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/Intrinsics/len_trim.f90
M flang/test/Lower/Intrinsics/system.f90
R flang/test/Lower/OpenMP/Todo/task_mergeable.f90
A flang/test/Lower/OpenMP/declare-target-interface.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
A flang/test/Parser/OpenMP/bind-clause.f90
A flang/test/Transforms/OpenMP/lower-workshare-nested.mlir
M flang/unittests/Runtime/CMakeLists.txt
M flang/unittests/Runtime/CommandTest.cpp
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/shared/rpc.h
A libc/shared/rpc_opcodes.h
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/common.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/complex/generic/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
M libc/src/pthread/CMakeLists.txt
M libc/src/setjmp/riscv/CMakeLists.txt
M libc/src/setjmp/x86_64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/stdfix/CMakeLists.txt
M libc/src/string/CMakeLists.txt
M libc/src/string/memory_utils/op_x86.h
M libc/src/threads/CMakeLists.txt
M libc/test/integration/startup/gpu/CMakeLists.txt
A libc/test/integration/startup/gpu/rpc_lane_test.cpp
M libc/test/src/math/smoke/LdExpTest.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/CMakeLists.txt
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/include/CMakeLists.txt
M libcxx/include/__chrono/duration.h
M libcxx/include/__config
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__split_buffer
A libcxx/include/__type_traits/detected_or.h
M libcxx/include/__vector/vector.h
M libcxx/include/module.modulemap
A libcxx/test/std/containers/sequences/vector/addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_copy.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/assign_move.addressof.compile.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/exceptions.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.cons/move.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/emplace.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_iter_iter.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_rvalue.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_size_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_value.addressof.compile.pass.cpp
R libcxx/test/std/containers/sequences/vector/vector.special/swap.addressof.compile.pass.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/Options.td
M lld/MachO/Writer.cpp
M lld/test/ELF/invalid/x86-64-tlsdesc-gd.s
M lld/test/ELF/pack-dyn-relocs-tls-x86-64.s
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
M lld/test/ELF/x86-64-tlsdesc-gd.s
R lld/test/MachO/Inputs/liballowable_client.dylib
M lld/test/MachO/allowable-client.s
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Host/Socket.h
M lldb/include/lldb/Symbol/Block.h
M lldb/source/Core/PluginManager.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/Function.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/TestingSupport/Host/SocketTestUtilities.cpp
M lldb/unittests/debugserver/RNBSocketTest.cpp
M lldb/unittests/tools/lldb-server/tests/TestClient.cpp
M llvm/Maintainers.md
M llvm/docs/DirectX/DXILResources.rst
M llvm/docs/GitHub.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
A llvm/include/llvm/DebugInfo/GSYM/CallSiteInfo.h
M llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/ConstantRangeList.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Metadata.h
A llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/VFABIDemangler.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/IntrinsicLowering.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SjLjEHPrepare.cpp
M llvm/lib/DebugInfo/GSYM/CMakeLists.txt
A llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/ConstantRangeList.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/VFABIDemangler.cpp
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
R llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.h
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kRegisterInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
M llvm/test/Analysis/CostModel/X86/fptoi_sat.ll
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
M llvm/test/Analysis/MemorySSA/loop-unswitch.ll
M llvm/test/Analysis/MemorySSA/pr40037.ll
M llvm/test/Analysis/MemorySSA/pr40749_2.ll
M llvm/test/Analysis/MemorySSA/pr43641.ll
M llvm/test/Analysis/MemorySSA/pr46574.ll
M llvm/test/Analysis/MemorySSA/simple_loop_unswitch_nontrivial.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
A llvm/test/CodeGen/AArch64/cgdata-merge-crash.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-local.ll
A llvm/test/CodeGen/AArch64/cgdata-merge-no-params.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
R llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/ptrauth-call.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-extq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
A llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
A llvm/test/CodeGen/AMDGPU/bitop3.ll
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx950.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
A llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions-obj-test.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/double-extensions.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/doubles.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/no_flags.ll
A llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll
R llvm/test/CodeGen/DirectX/updateCounter.ll
A llvm/test/CodeGen/Generic/builtin-expect-with-probability.ll
R llvm/test/CodeGen/Generic/cgdata-merge-crash.ll
A llvm/test/CodeGen/Generic/sjlj-eh-prepare.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
A llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
A llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
A llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/PowerPC/gcov_ctr_ref_init.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc-quad.ll
A llvm/test/CodeGen/PowerPC/vcmp-setbc.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/compress-opt-select.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
A llvm/test/CodeGen/RISCV/machine-outliner-call.ll
M llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
M llvm/test/CodeGen/RISCV/machine-outliner-leaf-descendants.ll
M llvm/test/CodeGen/RISCV/machine-outliner-patchable.ll
M llvm/test/CodeGen/RISCV/machine-outliner-position.mir
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
A llvm/test/CodeGen/RISCV/machineoutliner-x5.mir
M llvm/test/CodeGen/RISCV/machineoutliner.mir
A llvm/test/CodeGen/RISCV/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
M llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
A llvm/test/CodeGen/WebAssembly/thread_pointer.ll
A llvm/test/CodeGen/X86/apx/imulzu.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll
M llvm/test/CodeGen/X86/pr114520.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/sjlj-eh.ll
A llvm/test/CodeGen/X86/ubsan-trap-merge.ll
A llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
M llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
M llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
M llvm/test/MC/AArch64/local-bounds-single-trap.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx950_dlops.s
M llvm/test/MC/AMDGPU/gfx950_err.s
A llvm/test/MC/AMDGPU/gfx950_xdlops.s
M llvm/test/MC/AMDGPU/mai-gfx950-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_xdlops.txt
M llvm/test/MC/ELF/relocation.s
M llvm/test/MC/RISCV/attribute-arch.s
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
A llvm/test/Transforms/AtomicExpand/LoongArch/atomicrmw-expand.ll
M llvm/test/Transforms/ConstraintElimination/and-implied-by-operands.ll
M llvm/test/Transforms/ConstraintElimination/or.ll
A llvm/test/Transforms/EarlyCSE/noalias-addrspace.ll
M llvm/test/Transforms/GVN/noalias.ll
A llvm/test/Transforms/GVN/setjmp.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
M llvm/test/Transforms/JumpThreading/thread-loads.ll
M llvm/test/Transforms/LICM/hoist-metadata.ll
M llvm/test/Transforms/LICM/hoisting-preheader-debugloc.ll
A llvm/test/Transforms/LoopVectorize/RISCV/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
M llvm/test/Transforms/MemCpyOpt/aa-recursion-assertion-failure.ll
M llvm/test/Transforms/MergedLoadStoreMotion/st_sink_debuginvariant.ll
M llvm/test/Transforms/NewGVN/2010-03-31-RedundantPHIs.ll
M llvm/test/Transforms/NewGVN/2010-05-08-OneBit.ll
M llvm/test/Transforms/NewGVN/2011-04-27-phioperands.ll
M llvm/test/Transforms/NewGVN/2012-05-22-PreCrash.ll
M llvm/test/Transforms/NewGVN/basic-cyclic-opt.ll
M llvm/test/Transforms/NewGVN/completeness.ll
M llvm/test/Transforms/NewGVN/crash.ll
M llvm/test/Transforms/NewGVN/deadstore.ll
M llvm/test/Transforms/NewGVN/eliminate-ssacopy.ll
M llvm/test/Transforms/NewGVN/metadata-nonnull.ll
M llvm/test/Transforms/NewGVN/noalias.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-move-block.ll
M llvm/test/Transforms/NewGVN/phi-of-ops-simplification-dependencies.ll
M llvm/test/Transforms/NewGVN/pr25440.ll
M llvm/test/Transforms/NewGVN/pr31594.ll
M llvm/test/Transforms/NewGVN/pr31613.ll
M llvm/test/Transforms/NewGVN/pr31682.ll
M llvm/test/Transforms/NewGVN/pr32403.ll
M llvm/test/Transforms/NewGVN/pr32838.ll
M llvm/test/Transforms/NewGVN/pr32845.ll
M llvm/test/Transforms/NewGVN/pr32897.ll
M llvm/test/Transforms/NewGVN/pr32934.ll
M llvm/test/Transforms/NewGVN/pr33014.ll
M llvm/test/Transforms/NewGVN/pr33086.ll
M llvm/test/Transforms/NewGVN/pr33116.ll
M llvm/test/Transforms/NewGVN/pr33187.ll
M llvm/test/Transforms/NewGVN/pr33204.ll
M llvm/test/Transforms/NewGVN/pr33432.ll
M llvm/test/Transforms/NewGVN/pr33720.ll
M llvm/test/Transforms/NewGVN/pr34430.ll
M llvm/test/Transforms/NewGVN/pr35074.ll
M llvm/test/Transforms/NewGVN/pr42422-phi-of-ops.ll
M llvm/test/Transforms/NewGVN/pr43441.ll
M llvm/test/Transforms/NewGVN/pre-new-inst-xfail.ll
M llvm/test/Transforms/NewGVN/predicates.ll
M llvm/test/Transforms/NewGVN/refine-stores.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
A llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-117393.ll
M llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-13-SingleEntryPHI.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2006-06-27-DeadSwitchCase.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-Unreachable.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-05-09-tl.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-12-ExitDomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-13-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-07-18-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2007-08-01-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2008-06-02-DomInfo.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2010-11-18-LCSSA.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-06-02-CritSwitch.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2011-09-26-EHCrash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-04-02-IndirectBr.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2012-05-20-Phi.ll
M llvm/test/Transforms/SimpleLoopUnswitch/2015-09-18-Addrspace.ll
M llvm/test/Transforms/SimpleLoopUnswitch/LIV-loop-condtion.ll
M llvm/test/Transforms/SimpleLoopUnswitch/cleanuppad.ll
M llvm/test/Transforms/SimpleLoopUnswitch/copy-metadata.ll
M llvm/test/Transforms/SimpleLoopUnswitch/crash.ll
M llvm/test/Transforms/SimpleLoopUnswitch/exponential-behavior.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-cost.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-freeze.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch-skip-selects-in-guards.ll
M llvm/test/Transforms/SimpleLoopUnswitch/nontrivial-unswitch.ll
A llvm/test/Transforms/SimpleLoopUnswitch/pr117537.ll
M llvm/test/Transforms/SimpleLoopUnswitch/preserve-analyses.ll
M llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
M llvm/test/Transforms/SimplifyCFG/switch-branch-fold-indirectbr-102351.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-string.test
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-dsym.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-exe.yaml
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-callsite-info-obj.test
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/barrier_output.s
A llvm/test/tools/llvm-reduce/distinct-dimetadata-nullptr.ll
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
M llvm/unittests/AsmParser/AsmParserTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDieTest.cpp
M llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/GSYM/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
M mlir/docs/Bufferization.md
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/Bufferize.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/AffineMap.h
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Matchers.h
M mlir/include/mlir/Interfaces/TilingInterface.td
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/GPUToLLVMSPV/CMakeLists.txt
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/lib/Conversion/TensorToLinalg/TensorToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/TypeUtilities.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
M mlir/lib/Target/LLVMIR/AttrKindDetail.h
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/python/mlir/_mlir_libs/__init__.py
M mlir/test/CAPI/ir.c
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/Arith/bufferize.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-analysis.mlir
A mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize-partial.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-force-copy-before-write.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/Bufferization/ops.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize.mlir
M mlir/test/Dialect/Linalg/bufferize.mlir
M mlir/test/Dialect/Linalg/canonicalize.mlir
A mlir/test/Dialect/Linalg/decompose-pad-tensor.mlir
M mlir/test/Dialect/Linalg/fusion-elementwise.mlir
R mlir/test/Dialect/Linalg/generalize-pad-tensor.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir
M mlir/test/Dialect/MemRef/normalize-memrefs.mlir
M mlir/test/Dialect/SCF/bufferize.mlir
A mlir/test/Dialect/SCF/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/Dialect/Shape/bufferize.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul24_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_matvec_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sampled_matmul_lib.mlir
M mlir/test/Dialect/SparseTensor/GPU/gpu_sddmm_lib.mlir
M mlir/test/Dialect/SparseTensor/constant_index_map.mlir
M mlir/test/Dialect/SparseTensor/dense.mlir
M mlir/test/Dialect/SparseTensor/fuse_sparse_pad_with_consumer.mlir
M mlir/test/Dialect/SparseTensor/sorted_coo.mlir
M mlir/test/Dialect/SparseTensor/sparse_1d.mlir
M mlir/test/Dialect/SparseTensor/sparse_2d.mlir
M mlir/test/Dialect/SparseTensor/sparse_3d.mlir
M mlir/test/Dialect/SparseTensor/sparse_affine.mlir
M mlir/test/Dialect/SparseTensor/sparse_batch.mlir
M mlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_fusion.mlir
M mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
M mlir/test/Dialect/SparseTensor/sparse_kernels_to_iterator.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
M mlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
M mlir/test/Dialect/SparseTensor/sparse_nd.mlir
M mlir/test/Dialect/SparseTensor/sparse_outbuf.mlir
M mlir/test/Dialect/SparseTensor/sparse_pack.mlir
M mlir/test/Dialect/SparseTensor/sparse_parallel_reduce.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm.mlir
M mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir
M mlir/test/Dialect/SparseTensor/sparse_scalars.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm.mlir
M mlir/test/Dialect/SparseTensor/sparse_sddmm_org.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_chain.mlir
M mlir/test/Dialect/SparseTensor/sparse_vector_index.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm_bsr.mlir
M mlir/test/Dialect/SparseTensor/unused-tensor.mlir
M mlir/test/Dialect/SparseTensor/vectorize_reduction.mlir
M mlir/test/Dialect/Tensor/bufferize.mlir
A mlir/test/Dialect/Tensor/one-shot-bufferize-encodings.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/bufferize.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
M mlir/test/Integration/Dialect/Tosa/CPU/test-maxpool-dynamic.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/mulf-full.mlir
M mlir/test/Integration/Dialect/Vector/CPU/AMX/muli-full.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/intel-ext-ops.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/tools/mlir-tblgen/BytecodeDialectGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/unittests/IR/AffineMapTest.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
M runtimes/CMakeLists.txt
Log Message:
-----------
Merge branch 'main' into users/kparzysz/spr/m10-grainsize
Compare: https://github.com/llvm/llvm-project/compare/43f008a7f8b7...801c4bd8eea9
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