[all-commits] [llvm/llvm-project] e3cf2d: AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard

[Pravin Jagtap via All-commits]

  Branch: refs/heads/users/arsenm/gfx950/cvt_scale_hazard
  Home:   https://github.com/llvm/llvm-project
  Commit: e3cf2d758fe3e186ac5a4e22d15b76e3af9097a4
      https://github.com/llvm/llvm-project/commit/e3cf2d758fe3e186ac5a4e22d15b76e3af9097a4
  Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
  Date:   2024-11-27 (Wed, 27 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll

  Log Message:
  -----------
  AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard

gfx950 SP changes doc says:
No 4 clk forwarding on opcodes that convert from
F32/F16->F8 or F32/F16->F4. Must insert a NOP or
instruction writing some other destination VREG
after a conversion to F4/F8 since it writes either
low/high half or bytes.

Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Co-authored-by: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>



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