[all-commits] [llvm/llvm-project] 1290e9: [lldb] Fix ELF core debugging (#117070)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Nov 25 11:53:47 PST 2024
Branch: refs/heads/users/alexey-bataev/spr/slpadd-cost-estimation-for-gather-node-reshuffling
Home: https://github.com/llvm/llvm-project
Commit: 1290e95849aaad2fbd813aa15da667b2103ecc64
https://github.com/llvm/llvm-project/commit/1290e95849aaad2fbd813aa15da667b2103ecc64
Author: Kazuki Sakamoto <sakamoto at splhack.org>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
Log Message:
-----------
[lldb] Fix ELF core debugging (#117070)
DynamicLoader does not use ProcessElfCore NT_FILE entries to get
UUID. Use GetModuleSpec to get UUID from Process.
Commit: 2704647fb7986673b89cef1def729e3b022e2607
https://github.com/llvm/llvm-project/commit/2704647fb7986673b89cef1def729e3b022e2607
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
Revert "Fix up MCPlusBuilder.cpp to account for W0_HI on AArch64"
This reverts commit 576865a50e6ccb74196c9491fa79575d6d7f0b0b.
Depends on #114827 that was reverted.
Commit: 094ef38b122357840265b1b0e17c065bdf150971
https://github.com/llvm/llvm-project/commit/094ef38b122357840265b1b0e17c065bdf150971
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
Log Message:
-----------
[gn build] Port 028d41d7cf16
Commit: 0ffdaf445e72a152cc0707c9885046e55127af31
https://github.com/llvm/llvm-project/commit/0ffdaf445e72a152cc0707c9885046e55127af31
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port 1434d2ab215e
Commit: 8f50321256ecc1e7d433ca00baff47bd8a8bc81e
https://github.com/llvm/llvm-project/commit/8f50321256ecc1e7d433ca00baff47bd8a8bc81e
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
A libcxx/src/.clang-tidy
Log Message:
-----------
[libc++] Add a .clang-tidy file to libcxx/src
This disables `readability-identifier-naming` for the source files,
since names don't have to by _Uglified in the source files. We currently
don't enforce clang-tidy in the source files, so this is only useful to
avoid a bunch of warnings when using an editor that shows the results of
clang-tidy.
Commit: 24ced771cc4eb6ff8429eb085f0ffbef0e906d07
https://github.com/llvm/llvm-project/commit/24ced771cc4eb6ff8429eb085f0ffbef0e906d07
Author: Renat Idrisov <4032256+parsifal-47 at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[MLIR] RemoveDeadValues: Allowing IRs with global constants to get dead values removed (#116519)
This change is related to discussion:
https://discourse.llvm.org/t/question-on-criteria-for-acceptable-ir-in-removedeadvaluespass/83131
I do not know the original reason to disallow the optimization on
modules with global private constant. Please let me know what am I
missing, I will be happy to make it better. Thank you!
CC: @Wheest
---------
Co-authored-by: Renat Idrisov <parsifal-47 at users.noreply.github.com>
Commit: ccb4702038900d82d1041ff610788740f5cef723
https://github.com/llvm/llvm-project/commit/ccb4702038900d82d1041ff610788740f5cef723
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
A llvm/test/ThinLTO/X86/Inputs/memprof-old-alloc-context-summary.bc
A llvm/test/ThinLTO/X86/memprof-old-alloc-context-summary.ll
Log Message:
-----------
[MemProf] Use radix tree for alloc contexts in bitcode summaries (#117066)
Leverage the support added to represent allocation contexts in a more
compact way via a radix tree in the indexed profile to similarly reduce
sizes of the bitcode summaries.
For a large target, this reduced the size of the per-module summaries by
about 18% and in the distributed combined index files by 28%.
Commit: fdb050a5024320ec29d2edf3f2bc686c3a84abaa
https://github.com/llvm/llvm-project/commit/fdb050a5024320ec29d2edf3f2bc686c3a84abaa
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
R llvm/test/ThinLTO/X86/Inputs/memprof-old-alloc-context-summary.bc
R llvm/test/ThinLTO/X86/memprof-old-alloc-context-summary.ll
Log Message:
-----------
Revert "[MemProf] Use radix tree for alloc contexts in bitcode summaries" (#117395)
Reverts llvm/llvm-project#117066
This is causing some build bot failures that need investigation.
Commit: b4e000e6005bd0f11240133aa335efcbb8424a23
https://github.com/llvm/llvm-project/commit/b4e000e6005bd0f11240133aa335efcbb8424a23
Author: Tom Lin <tom91136 at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/LTO.cpp
M lld/MachO/Options.td
A lld/test/MachO/ltopasses-extension.ll
Log Message:
-----------
[LLD][MachO] Enable plugin support for LTO (#115690)
Add new CLI options for feature parity with ELF w.r.t pass plugins.
Most of the changes are ported directly from
https://github.com/llvm/llvm-project/commit/0c86198b279a98c8550fde318b59ed3ca0ca5045.
With this change, it is now possible to load and run external pass
plugins during the LTO phase.
Commit: d121d71fc7fcb8c969959147f5f58b31f9c6b251
https://github.com/llvm/llvm-project/commit/d121d71fc7fcb8c969959147f5f58b31f9c6b251
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M libc/src/__support/block.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/src/__support/freetrie.h
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/__support/freelist_malloc_test.cpp
M libc/test/src/__support/freelist_test.cpp
M libc/test/src/__support/freestore_test.cpp
M libc/test/src/__support/freetrie_test.cpp
Log Message:
-----------
[libc][NFC] Remove template arguments from Block (#117386)
Commit: 9edbe566bfaff6af03c309ebbb229e6e9a717de3
https://github.com/llvm/llvm-project/commit/9edbe566bfaff6af03c309ebbb229e6e9a717de3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
R llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
A llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Move rvv-cfi-info.ll to rvv directory. NFC
Commit: aa5dc539e91824cbc224214e69d62d46db21af6e
https://github.com/llvm/llvm-project/commit/aa5dc539e91824cbc224214e69d62d46db21af6e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrFragments.td
Log Message:
-----------
[X86] Fix the type of X86ISD::UMUL (#117377)
Same as SMUL, UMUL produces one result + flags, not two results + flags.
Commit: 776476c282bca71d5b856e80e0a88fbd6f3ccdd2
https://github.com/llvm/llvm-project/commit/776476c282bca71d5b856e80e0a88fbd6f3ccdd2
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/Bitcode/Writer/CMakeLists.txt
M llvm/lib/ProfileData/MemProf.cpp
A llvm/test/ThinLTO/X86/Inputs/memprof-old-alloc-context-summary.bc
A llvm/test/ThinLTO/X86/memprof-old-alloc-context-summary.ll
Log Message:
-----------
Reapply "[MemProf] Use radix tree for alloc contexts in bitcode summaries" (#117395) (#117404)
This reverts commit fdb050a5024320ec29d2edf3f2bc686c3a84abaa, and
restores ccb4702038900d82d1041ff610788740f5cef723, with a fix for build
bot failures.
Specifically, add ProfileData to the dependences of the BitWriter
library, which was causing shared library builds of LLVM to fail.
Reproduced the failure with a shared library build and confirmed this
change fixes that build failure.
Commit: beff2bacae76fe25c86c5bf7bccb2cbef93de047
https://github.com/llvm/llvm-project/commit/beff2bacae76fe25c86c5bf7bccb2cbef93de047
Author: Kasper Nielsen <kasper0406 at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
A mlir/test/get_darwin_real_python.py
M mlir/test/lit.cfg.py
Log Message:
-----------
[MLIR, Python] Make it easy to run tests with ASan on mac (#115524)
There are two things that make running MLIR tests with ASan on a mac
tedious:
1. The `DYLD_INSERT_LIBRARIES` environment variable needs to be set to
point to `libclang_rt.asan_osx_dynamic.dylib`
2. Mac is wrapping Python, which means that the `DYLD_INSERT_LIBRARIES`
environment variable is not being respected in the Python tests. The
solution is to find and use a non-wrapped Python binary.
With the above two changes, ASan works out of the box on mac's by
setting the `-DLLVM_USE_SANITIZER=Address` cmake flag.
I have stolen most of the code in this PR from other LLVM projects. It
may be a good idea to reconcile it somewhere.
Commit: dd8d85dba6e8f74a55fb5053107797e21894a0c6
https://github.com/llvm/llvm-project/commit/dd8d85dba6e8f74a55fb5053107797e21894a0c6
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Ignore lambda invocation with arguments (#117394)
Fixed a bug that UncountedLambdaCapturesChecker would emit a warning on
a lambda capture when the lambda is invoked with arguments.
LocalVisitor::VisitCallExpr was not tolerating a lambda invocation with
more than 1 arguments.
Commit: 5802367ddb46bcdeb0befeffbc99a1d72a5d9082
https://github.com/llvm/llvm-project/commit/5802367ddb46bcdeb0befeffbc99a1d72a5d9082
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M flang/include/flang/Runtime/CUDA/allocatable.h
A flang/include/flang/Runtime/CUDA/memmove-function.h
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/runtime/CUDA/CMakeLists.txt
M flang/runtime/CUDA/allocatable.cpp
A flang/runtime/CUDA/memmove-function.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Fir/CUDA/cuda-allocate.fir
Log Message:
-----------
[flang][cuda] Add support for allocate with source (#117388)
Add support for allocate statement with CUDA device variable and a
source.
Commit: a0153eaa65e718f16fd22b4b784e0f8153f695d4
https://github.com/llvm/llvm-project/commit/a0153eaa65e718f16fd22b4b784e0f8153f695d4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[memprof] Fix builds under EXPENSIVE_CHECKS
memprof::Version1 has been removed, so the whole block of code is
dead.
Commit: 7a56dc724594691efce13d771902478544696182
https://github.com/llvm/llvm-project/commit/7a56dc724594691efce13d771902478544696182
Author: Félix-Antoine Constantin <60141446+felix642 at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/Analysis.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
A llvm/test/CodeGen/X86/tailcall-nofpclass.ll
Log Message:
-----------
[Clang] Attribute NoFPClass should not prevent tail call optimization. (#116741)
Fixes #111950
Commit: b3909f4298fd3679dc24483c6e5d455058955d84
https://github.com/llvm/llvm-project/commit/b3909f4298fd3679dc24483c6e5d455058955d84
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
Log Message:
-----------
[MLIR] Drop assumption of a surrounding builtin.func in promoteIfSingleIteration (#116323)
Drop assumption of a surrounding builtin.func in
promoteIfSingleIteration.
Fixes https://github.com/llvm/llvm-project/issues/116042
Commit: 4a0b8c3e7d4e9031181400d48ffcdf703bccce35
https://github.com/llvm/llvm-project/commit/4a0b8c3e7d4e9031181400d48ffcdf703bccce35
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
Log Message:
-----------
[MLIR][Affine] Drop assumptions of surrounding builtin.func op in Utils/LoopUtils (#116324)
Drop assumptions of surrounding builtin.func op in affine LoopUtils and
Utils. There are use cases of affine fusion or affine transformation in
other func-like ops.
In the context of https://github.com/llvm/llvm-project/issues/116042
Commit: be750200ec03a195f29b53b099bcf075a5289708
https://github.com/llvm/llvm-project/commit/be750200ec03a195f29b53b099bcf075a5289708
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/test/Dialect/Affine/affine-data-copy.mlir
Log Message:
-----------
[MLIR] Fix unchecked use of memref memory space attr in affine data copy generate (#116763)
Fix unchecked use of memref memory space attr in affine data copy
generate. In the case of memory accesses without a memory space
attribute or those other than integer attributes, the pass treats them
as slow memory spaces.
Fixes https://github.com/llvm/llvm-project/issues/116536
Commit: 132de3a71f581dcb008a124d52c83ccca8158d98
https://github.com/llvm/llvm-project/commit/132de3a71f581dcb008a124d52c83ccca8158d98
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp
M mlir/test/Dialect/Affine/affine-loop-invariant-code-motion.mlir
Log Message:
-----------
[MLIR] Fix arbitrary checks in affine LICM (#116469)
Fix arbitrary checks and hardcoding/specialcasing in affine LICM. Drop
unnecessary (too much) debug logging.
This pass is still unsound due to not handling aliases. This will have
to be handled later.
Commit: d1cca3133a6eea845c312b17379ad93f57aa7dd7
https://github.com/llvm/llvm-project/commit/d1cca3133a6eea845c312b17379ad93f57aa7dd7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
Log Message:
-----------
AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (#117260)
This was a bit annoying because these introduce a new special case
encoding usage. op_sel is repurposed as a subset of dpp controls,
and is eligible for VOP3->VOP1 shrinking. For some reason fi also
uses an enum value, so we need to convert the raw boolean to 1 instead
of -1.
The 2 registers are swapped, so this has 2 defs. Ideally the builtin
would return a pair, but that's difficult so return a vector instead.
This would make a hypothetical builtin that supports v2f16 directly
uglier.
Commit: 33c2b20f3de893001568157dc3602d8762d139fc
https://github.com/llvm/llvm-project/commit/33c2b20f3de893001568157dc3602d8762d139fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
Log Message:
-----------
AMDGPU: Define new sched model for gfx950 (#117261)
A few instructions changed rate.
Commit: b078b882b96922d15b565873e06e1a28514f16e7
https://github.com/llvm/llvm-project/commit/b078b882b96922d15b565873e06e1a28514f16e7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (#117262)
Increase from 11 wait states to 19
Commit: 8cb6c9907c4cdcba073be664988ff81e6d689d32
https://github.com/llvm/llvm-project/commit/8cb6c9907c4cdcba073be664988ff81e6d689d32
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
Log Message:
-----------
AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (#117263)
These have an additional wait state compared to gfx940.
Commit: db08d78c3e368ffbc8bef1b806d2c7179a5ccbf9
https://github.com/llvm/llvm-project/commit/db08d78c3e368ffbc8bef1b806d2c7179a5ccbf9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (#117283)
Read by sgemm/dgemm in srcc after v_mfma_f64_16x16x4_f64 increases from 9 to 17
wait states.
Commit: 85601fd78f4cbf0ce5df74c5926183035f859572
https://github.com/llvm/llvm-project/commit/85601fd78f4cbf0ce5df74c5926183035f859572
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (#117284)
Increase in wait states from 11 to 19. The index for smfmac counts as like srcA/srcB.
Commit: 9d8a11fb3924a8176ff9959684ca1cebe1c0143f
https://github.com/llvm/llvm-project/commit/9d8a11fb3924a8176ff9959684ca1cebe1c0143f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/MemProf.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove verifyIndexedMemProfRecord and verifyFunctionProfileData (#117412)
This patch removes two functions to verify the consistency between:
- IndexedAllocationInfo::CallStack
- IndexedAllocationInfo::CSId
Now that MemProf format Version 1 has been removed,
IndexedAllocationInfo::CallStack doesn't participate in either
serialization or deserialization, so we don't care about the
consistency between the two fields in IndexAllocationInfo.
Subsequent patches will remove uses of the old field and eventually
remove the field.
Commit: 68f7b075c07197803625431ba92c337af7470c85
https://github.com/llvm/llvm-project/commit/68f7b075c07197803625431ba92c337af7470c85
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/test/CodeGen/Generic/machine-function-splitter.ll
Log Message:
-----------
[BasicBlockSections] Allow mixing of -basic-block-sections with MFS. (#117076)
This PR allows mixing `-basic-block-sections` with
`-enable-machine-function-splitter`. The strategy is to let
`-basic-block-sections` take precedence over functions with profiles.
Commit: 19ddafafdf131aed40abbdaf5af1fb7b59c1e8ac
https://github.com/llvm/llvm-project/commit/19ddafafdf131aed40abbdaf5af1fb7b59c1e8ac
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Analysis/MemoryBuiltins.cpp
A llvm/test/Instrumentation/BoundsChecking/negative.ll
Log Message:
-----------
[llvm] Fix ObjectSizeOffsetVisitor behavior in exact mode upon negati… (#116955)
…ve offset
In Exact mode, the approximation of returning (0,0) is invalid. It only
holds in min/max mode.
Commit: 3a31427224d4fa49d7ef737b21f6027dc4928ecf
https://github.com/llvm/llvm-project/commit/3a31427224d4fa49d7ef737b21f6027dc4928ecf
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/www/cxx_status.html
Log Message:
-----------
[Clang] Add C++26 approved in the Poland WG21 meeting
Commit: dbb21df2a21591964e1581ba7561f49114fd8fb1
https://github.com/llvm/llvm-project/commit/dbb21df2a21591964e1581ba7561f49114fd8fb1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
Log Message:
-----------
[X86] vector-shuffle-avx512.ll - regenerate TERNLOG comments
Commit: 1e31a4529244ead9f12abed524f33a48515abee2
https://github.com/llvm/llvm-project/commit/1e31a4529244ead9f12abed524f33a48515abee2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
M llvm/test/CodeGen/X86/vector-shuffle-v48.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] lowerShuffleWithPERMV - commute VPERMV3 shuffles so any load is on the RHS
This helps ensure we lower to VPERMI2/T2 instructions that we can commute the index arg to VPERMT2/I2.
Prep work for #79799
Commit: 590913983c87b33fb04014124be161cbad33a6e3
https://github.com/llvm/llvm-project/commit/590913983c87b33fb04014124be161cbad33a6e3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
Log Message:
-----------
[VPlan] Simplify and unify code in verifyEVLRecipe using all_of. (NFCI)
Use all_of instead of explicit loop to reduce indentation, also properly
check VPScalarCastRecipe operand.
Commit: 08e6566d7a310ace0660cbf3fbeb3f1c0c283295
https://github.com/llvm/llvm-project/commit/08e6566d7a310ace0660cbf3fbeb3f1c0c283295
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Func/Transforms/FuncConversions.cpp
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][Func] Support 1:N result type conversions in `func.call` conversion (#117413)
This commit adds support for 1:N result type conversions for `func.call`
ops. In that case, argument materializations to the original result type
should be inserted (via `replaceOpWithMultiple`).
This commit is in preparation of merging the 1:1 and 1:N conversion
drivers.
Commit: 4a8329cd7d038d8cdfa9b4cc784ab0e402ecb774
https://github.com/llvm/llvm-project/commit/4a8329cd7d038d8cdfa9b4cc784ab0e402ecb774
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M libcxx/include/__memory_resource/synchronized_pool_resource.h
M libcxx/include/future
M libcxx/include/memory_resource
M libcxx/include/syncstream
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Granularize <mutex> includes (#117068)
Commit: aaa0dd2f05ff957a171a87e78578dddc59fc49c2
https://github.com/llvm/llvm-project/commit/aaa0dd2f05ff957a171a87e78578dddc59fc49c2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M libcxx/utils/ci/buildkite-pipeline.yml
Log Message:
-----------
[libc++][NFC] Remove a bunch of unused environment variables from the CI configs
Commit: 56feea7307d8db752f7c98af3a7fa1dd7fc72391
https://github.com/llvm/llvm-project/commit/56feea7307d8db752f7c98af3a7fa1dd7fc72391
Author: Ingo Müller <ingomueller at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
M mlir/python/requirements.txt
Log Message:
-----------
[mlir][python] Update minimal version of pybind11 to 2.10. (#117314)
This PR updates the minimal required version of pybind11 from 2.9.0 to
2.10.0. New new version is almost 2.5 years old, which is half a year
less than the previous version. This change is necessary to support the
changes introduced in #115307, which does not compile with pybind11
v.2.9.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 01e75646a5d4977a9e441e3db1042df0beccc4bb
https://github.com/llvm/llvm-project/commit/01e75646a5d4977a9e441e3db1042df0beccc4bb
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinDialectBytecode.td
M mlir/include/mlir/IR/BuiltinLocationAttributes.td
M mlir/include/mlir/IR/Location.h
M mlir/lib/AsmParser/LocationParser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/BuiltinDialectBytecode.cpp
M mlir/lib/IR/Location.cpp
M mlir/test/IR/locations.mlir
Log Message:
-----------
[mlir] Add FileRange location type. (#80213)
This location type represents a contiguous range inside a file. It is
effectively a pair of FileLineCols. Add new type and make FileLineCol a
view for case where it matches existing previous one.
The location includes filename and optional start line & col, and end
line & col. Considered common cases are file:line, file:line:col,
file:line:start_col to file:line:end_col and general range within same
file. In memory its encoded as trailing objects. This keeps the memory
requirement the same as FileLineColLoc today (makes the rather common
File:Line cheaper) at the expense of extra work at decoding time. Kept the unsigned
type.
There was the option to always have file range be castable to
FileLineColLoc. This cast would just drop other fields. That may result
in some simpler staging. TBD.
This is a rather minimal change, it does not yet add bindings (C or
Python), lowering to LLVM debug locations etc. that supports end line:cols.
---------
Co-authored-by: River Riddle <riddleriver at gmail.com>
Commit: aa2d084f9a68f041a42e4df84e11d769a7be34a6
https://github.com/llvm/llvm-project/commit/aa2d084f9a68f041a42e4df84e11d769a7be34a6
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format][NFC] Reformat testcases added in 0ff8b7916050
Commit: 70bd80dc51b62453210f6203c31ea826dd0675c2
https://github.com/llvm/llvm-project/commit/70bd80dc51b62453210f6203c31ea826dd0675c2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
Log Message:
-----------
[X86] combineTargetShuffle - commute VPERMV3 shuffles so any load is on the RHS
This helps ensure we lower to VPERMI2/T2 instructions that we can commute the index arg to VPERMT2/I2.
Similar to 1e31a4529244ead9f12abed524f33a48515abee2 to handle cases where the one use load appears after further folding (keep the lowerShuffleWithPERMV version as this can handle the non-VLX widening case as well).
Commit: b0e7383e59a100da60c043fd9aca3484c5ed332f
https://github.com/llvm/llvm-project/commit/b0e7383e59a100da60c043fd9aca3484c5ed332f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
Log Message:
-----------
Reapply [flang][OpenMP] Avoid early returns, NFC #117231 (#117325)
Two PRs were merged at the same time: one that modified `maybeApplyToV`
function, and shortly afterwards, this (the reverted) one that had the
old definition.
During the merge both definitions were retained leading to compilation
errors.
Reapply the reverted PR (1a08b15589) with the duplicate removed.
Commit: d3ce069572cb565da613df9828ac54f7edb2fc00
https://github.com/llvm/llvm-project/commit/d3ce069572cb565da613df9828ac54f7edb2fc00
Author: David Green <david.green at arm.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-vector-splat.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize ptr shuffle vector to s64 (#116013)
This converts all ptr element shuffle vectors to s64, so that the
existing vector legalization handling can lower them as needed. This
prevents a lot of fallbacks that currently try to generate things like
`<2 x ptr> G_EXT`.
I'm not sure if bitcast/inttoptr/ptrtoint is intended to be necessary
for vectors of pointers, but it uses buildCast for the casts, which now
generates a ptrtoint/inttoptr.
Commit: 2f69f9a95068fc85de18dc26f35d160a40343286
https://github.com/llvm/llvm-project/commit/2f69f9a95068fc85de18dc26f35d160a40343286
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/test/MC/AMDGPU/ds.s
M llvm/test/MC/AMDGPU/invalid-instructions-spellcheck.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/mimg-err.s
M llvm/test/MC/AMDGPU/mimg.s
M llvm/test/MC/AMDGPU/regression/bug28165.s
M llvm/test/MC/AMDGPU/regression/bug28413.s
M llvm/test/MC/AMDGPU/smrd.s
M llvm/test/MC/AMDGPU/sopk.s
A llvm/test/MC/AMDGPU/unknown-target-cpu.s
M llvm/test/MC/AMDGPU/vintrp.s
M llvm/test/MC/AMDGPU/vop1.s
M llvm/test/MC/AMDGPU/vop2.s
M llvm/test/MC/AMDGPU/vop3-convert.s
M llvm/test/MC/AMDGPU/vop3-errs.s
M llvm/test/MC/AMDGPU/vop3.s
M llvm/test/MC/AMDGPU/vop_dpp.s
M llvm/test/MC/AMDGPU/vop_sdwa.s
M llvm/test/MC/AMDGPU/vopc.s
Log Message:
-----------
AMDGPU: Stop running assembler tests with default cpu (#117421)
It does not make sense to assemble for the default target.
Add one that shows the behavior. It is treated as a tahiti
alias without instructions which were later removed, and needs
to be treated as wave64. We should probably turn this into a hard
error though.
Commit: 8b087d64222276090702fb70dec5939eb22a017c
https://github.com/llvm/llvm-project/commit/8b087d64222276090702fb70dec5939eb22a017c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/test/MC/AMDGPU/unknown-target-cpu.s
Log Message:
-----------
AMDGPU: Move default wavesize hack for disassembler (#117422)
You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.
Commit: cd20fc07720520856c385a12b0daa26b9d8a8e44
https://github.com/llvm/llvm-project/commit/cd20fc07720520856c385a12b0daa26b9d8a8e44
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/test/MC/AMDGPU/wave_any.s
Log Message:
-----------
AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)
This is a refinement for the existing hack. With this,
the default target will have neither wavefrontsize feature
present, unless it was explicitly specified. That is,
getWavefrontSize() == 64 no longer implies +wavefrontsize64.
getWavefrontSize() == 32 does imply +wavefrontsize32.
Continue to assume the value is 64 with no wavesize feature.
This maintains the codegenable property without any code
that directly cares about the wavesize needing to worry about it.
Introduce an isWaveSizeKnown helper to check if we know the
wavesize is accurate based on having one of the features explicitly
set, or a known target-cpu.
I'm not sure what's going on in wave_any.s. It's testing what
happens when both wavesizes are enabled, but this is treated
as an error in codegen. We now treat wave32 as the winning
case, so some cases that were previously printed as vcc are now
vcc_lo.
Commit: 1944d192bd43bfc02e1701801c4b061007238014
https://github.com/llvm/llvm-project/commit/1944d192bd43bfc02e1701801c4b061007238014
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
Log Message:
-----------
AMDGPU: Use isWave[32|64] instead of comparing size value (#117411)
Commit: 94bde8cdc39ff7e9c59ee0cd5edda882955242aa
https://github.com/llvm/llvm-project/commit/94bde8cdc39ff7e9c59ee0cd5edda882955242aa
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
A clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
A clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
Log Message:
-----------
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffers (#114148)
Introduces `__builtin_hlsl_buffer_update_counter` clang buildin that is
used to implement the `IncrementCounter` and `DecrementCounter` methods
on `RWStructuredBuffer` and `RasterizerOrderedStructuredBuffer` (see
Note).
The builtin is translated to LLVM intrisic `llvm.dx.bufferUpdateCounter`
or `llvm.spv.bufferUpdateCounter`.
Introduces `BuiltinTypeMethodBuilder` helper in `HLSLExternalSemaSource`
that enables adding methods to builtin types using builder pattern like
this:
```
BuiltinTypeMethodBuilder(Sema, RecordBuilder, "MethodName", ReturnType)
.addParam("param_name", Type, InOutModifier)
.callBuiltin("buildin_name", { BuiltinParams })
.finalizeMethod();
```
Fixes #113513
Commit: b3363104d3af75f7f0151f28fc9e577cea6dea6b
https://github.com/llvm/llvm-project/commit/b3363104d3af75f7f0151f28fc9e577cea6dea6b
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/test/CodeGen/Xtensa/mul.ll
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[UTC] Add support for Xtensa (#117441)
Regenerate the failing test as well.
Commit: 14b9ca3f38494bbd03709188b6e73c06ab84cd15
https://github.com/llvm/llvm-project/commit/14b9ca3f38494bbd03709188b6e73c06ab84cd15
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[Sema] Fix a warning
This patch fixes:
clang/lib/Sema/SemaHLSL.cpp:2225:32: error: absolute value function
'abs' given an argument of type 'int64_t' (aka 'long') but has
parameter of type 'int' which may cause truncation of value
[-Werror,-Wabsolute-value]
Commit: 5f9db0876a2022d68e368cd4a06f240ca839198c
https://github.com/llvm/llvm-project/commit/5f9db0876a2022d68e368cd4a06f240ca839198c
Author: M. Zeeshan Siddiqui <mzs at microsoft.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
Allow SymbolUserOpInterface operators to be used in RemoveDeadValues Pass (#117405)
This change removes the restriction on `SymbolUserOpInterface` operators
so they can be used with operators that implement `SymbolOpInterface`,
example:
`memref.global` implements `SymbolOpInterface` so it can be used with
`memref.get_global` which implements `SymbolUserOpInterface`
```
// Define a global constant array
memref.global "private" constant @global_array : memref<10xi32> = dense<[1, 2, 3, 4, 5, 6, 7, 8, 9, 10]> : tensor<10xi32>
// Access this global constant within a function
func @use_global() {
%0 = memref.get_global @global_array : memref<10xi32>
}
```
Reference: https://github.com/llvm/llvm-project/pull/116519 and
https://discourse.llvm.org/t/question-on-criteria-for-acceptable-ir-in-removedeadvaluespass/83131
---------
Co-authored-by: Zeeshan Siddiqui <mzs at ntdev.microsoft.com>
Commit: 28064bfad12cfce959d74fa6d099312e19703f26
https://github.com/llvm/llvm-project/commit/28064bfad12cfce959d74fa6d099312e19703f26
Author: David Green <david.green at arm.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/arm64-clrsb.ll
M llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
M llvm/test/CodeGen/AArch64/arm64-vclz.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fcvt-fixed.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/mingw-refptr.ll
M llvm/test/CodeGen/AArch64/mulcmle.ll
M llvm/test/CodeGen/AArch64/overflow.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat.ll
M llvm/test/CodeGen/AArch64/usub_sat_plus.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
Log Message:
-----------
[AArch64][GlobalISel] Update and cleanup a number of gisel tests. NFC
Mostly removing unnecessary -global-isel-abort=2 or adding fallback messages
Commit: e2519b674c5551caf6604b1bc8567887298b6127
https://github.com/llvm/llvm-project/commit/e2519b674c5551caf6604b1bc8567887298b6127
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
Log Message:
-----------
[VPlan] Print incoming VPBB for Phi VPIRInstruction (NFC).
Print the incoming block for Phi VPIRInstructions, for better debugging
& testing.
Commit: c8b837ad8ce4f36a3b2e47f1f1367dc0b41fca7b
https://github.com/llvm/llvm-project/commit/c8b837ad8ce4f36a3b2e47f1f1367dc0b41fca7b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/include/mlir-c/Pass.h
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/lib/CAPI/IR/Pass.cpp
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][Python] Add the `--mlir-print-ir-tree-dir` to the C and Python API (#117339)
Commit: 213b849c5e2118e44f3b13de43749c4ddb26598f
https://github.com/llvm/llvm-project/commit/213b849c5e2118e44f3b13de43749c4ddb26598f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Use libcalls for some FP instructions when F/D aren't present.
This is based on what fails when adding integer only RUN lines to
float-intrinsics.ll and double-intrinsics.ll.
We're still missing a lot of test cases that SelectionDAG has. These
will be added in future patches.
Commit: dc4c8de179ff2237378bd42a2b650fad2f7b1940
https://github.com/llvm/llvm-project/commit/dc4c8de179ff2237378bd42a2b650fad2f7b1940
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
R clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
R clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
R clang/test/SemaHLSL/BuiltIns/buffer_update_counter-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
Log Message:
-----------
Revert "[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffers (#114148)" (#117448)
This reverts commit 94bde8cdc39ff7e9c59ee0cd5edda882955242aa.
Commit: 3cecf17065919da0a7fa9b38f37592e5462c2f85
https://github.com/llvm/llvm-project/commit/3cecf17065919da0a7fa9b38f37592e5462c2f85
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
A lld/test/ELF/merge-addr.s
M lld/test/ELF/merge-reloc.s
R lld/test/ELF/merge-relocatable.s
R lld/test/ELF/merge-shared-str.s
R lld/test/ELF/merge-shared.s
R lld/test/ELF/merge-string.s
R lld/test/ELF/merge-to-non-alloc.s
Log Message:
-----------
[ELF] Refactor merge-* tests
Commit: 43e3871a327b8e2ff57e16b46d5bc44beb430d91
https://github.com/llvm/llvm-project/commit/43e3871a327b8e2ff57e16b46d5bc44beb430d91
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/OutputSections.cpp
M lld/ELF/SyntheticSections.cpp
Log Message:
-----------
[ELF] Make section member orders consistent
SectionBase, InputSectionBase, InputSection, MergeInputSection, and
OutputSection have different member orders. Make them consistent and
adopt the order similar to the raw Elf64_Shdr.
Commit: d6e6478e95d7b20a5c742112c425ea06b85922c4
https://github.com/llvm/llvm-project/commit/d6e6478e95d7b20a5c742112c425ea06b85922c4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
Log Message:
-----------
[memprof] Remove a dead constructor in AllocationInfo (NFC) (#117427)
This patch removes a dead constructor in AllocationInfo. We used to
use it for MemProf Version 1 deserialization purposes via
MemProfRecord::MemProfRecord.
Commit: d4bed617f4378873d7ddf4b53c041e7b39d1a9ca
https://github.com/llvm/llvm-project/commit/d4bed617f4378873d7ddf4b53c041e7b39d1a9ca
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/merge-reloc.s
Log Message:
-----------
[ELF] -r: keep sh_entsize for SHF_MERGE sections with relocations
Follow-up to the NFC refactoring
43e3871a327b8e2ff57e16b46d5bc44beb430d91 and test cleanup
3cecf17065919da0a7fa9b38f37592e5462c2f85.
SHF_MERGE sections with relocations are handled as InputSection (without
duplicate elimination). The output section retains the original
sh_entsize in non-relocatable links. This patch ports the behavior for
relocatable links as well.
https://github.com/ClangBuiltLinux/linux/issues/2057
Commit: a5af6214dd0e9d53c66dc06bcd23540b05c70120
https://github.com/llvm/llvm-project/commit/a5af6214dd0e9d53c66dc06bcd23540b05c70120
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/InputSection.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Make SyntheticSection parameter order match InputSection
And rename `/*alignment=*/` to `/*addralign=*/`
Commit: 099a52fd2f3723db6b0550c99a1adc12d2d8d909
https://github.com/llvm/llvm-project/commit/099a52fd2f3723db6b0550c99a1adc12d2d8d909
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/MapFile.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Reorder SectionBase/InputSectionBase members
Move `sectionKind` outside the bitfield and move bss/keepUnique to
InputSectionBase.
* sizeof(InputSection) decreases from 160 to 152 on 64-bit systems.
* The numerous `sectionKind` accesses are faster.
Commit: cf9b4281c1b4c5d6f2bf31909521af8ab4bb4f45
https://github.com/llvm/llvm-project/commit/cf9b4281c1b4c5d6f2bf31909521af8ab4bb4f45
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/ARC/ARCInstrInfo.td
Log Message:
-----------
[ARC] Fix ARCISD::BRcc description (#117454)
Follow-up to #117375.
Commit: afae1a5f32bb16c389b718e91e6eb808e0deeac2
https://github.com/llvm/llvm-project/commit/afae1a5f32bb16c389b718e91e6eb808e0deeac2
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__configuration/availability.h
Log Message:
-----------
[libc++] Remove _LIBCPP_DISABLE_AVAILABILITY macro (#112952)
This was slated for removal years ago, so now's a good time to remove it.
Commit: 042a1cc553aa347f00cf4c56ec3c6168a2cd34b6
https://github.com/llvm/llvm-project/commit/042a1cc553aa347f00cf4c56ec3c6168a2cd34b6
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
Log Message:
-----------
[VPlan] Generalize type inference for binary/cast/shift/logic. NFC (#116173)
Commit: e4e5206050a657170892bc400fd4b870e0576ec6
https://github.com/llvm/llvm-project/commit/e4e5206050a657170892bc400fd4b870e0576ec6
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
Log Message:
-----------
[ELF] Make OutputDesc unique_ptr
Store them in LinkerScript::descPool. This removes a SpecificAlloc
instantiation, makes lld smaller, and drops the small memory waste due
to the separate BumpPtrAllocator.
Commit: 48b13ca48b701ce8230e45c1e4c8338806971e21
https://github.com/llvm/llvm-project/commit/48b13ca48b701ce8230e45c1e4c8338806971e21
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
Log Message:
-----------
[RISCV][CostModel] cost of vector cttz/ctlz under ZVBB (#115800)
Commit: a87f776c1c873ea86a95c368f1a9331adc65d1ee
https://github.com/llvm/llvm-project/commit/a87f776c1c873ea86a95c368f1a9331adc65d1ee
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
Log Message:
-----------
[ELF] Avoid make in elf::writeARMCmseImportLib
Commit: c894d3a846f351e592bf917ace57c7d2fcbeddc8
https://github.com/llvm/llvm-project/commit/c894d3a846f351e592bf917ace57c7d2fcbeddc8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
Log Message:
-----------
Fixup a test for #116330, to make `REQUIRES:asserts`
`-debug-only` is available only in +Asserts.
Commit: ed1d90ca11b1834e667e17255ba2ecf6fe305e8c
https://github.com/llvm/llvm-project/commit/ed1d90ca11b1834e667e17255ba2ecf6fe305e8c
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/Parse/ParseStmt.cpp
Log Message:
-----------
[clang][NFC] simplify the unset check in `ParseLabeledStatement` (#117430)
`!isInvalid && !isUsable -> !isInvalid && !(!isInvalid && !isUnset) ->
isUnset`
It is more simple to understand.
Commit: a0ef12c64284abf59bc092b2535cce1247d5f9a4
https://github.com/llvm/llvm-project/commit/a0ef12c64284abf59bc092b2535cce1247d5f9a4
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
A mlir/test/Conversion/MemRefToLLVM/type-conversion.mlir
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
A mlir/test/lib/Dialect/LLVM/TestPatterns.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][LLVM] `LLVMTypeConverter`: Tighten materialization checks (#116532)
This commit adds extra checks to the MemRef argument materializations in
the LLVM type converter. These materializations construct a
`MemRefType`/`UnrankedMemRefType` from the unpacked elements of a MemRef
descriptor or from a bare pointer.
The extra checks ensure that the inputs to the materialization function
are correct. It is possible that a user added extra type conversion
rules that convert MemRef types in a different way and the extra checks
ensure that we construct a MemRef descriptor only if the inputs are what
we expect.
This commit also drops a check around bare pointer materializations:
```
// This is a bare pointer. We allow bare pointers only for function entry
// blocks.
```
This check should not be part of the materialization function. Whether a
MemRef block argument is converted into a MemRef descriptor or a bare
pointer is decided in the lowering pattern. At the point of time when
materialization functions are executed, we already made that decision
and we should just materialize regardless of the input format.
Commit: 1a2cc2bce86448dfb1c9795a907d28ca2db6aaf5
https://github.com/llvm/llvm-project/commit/1a2cc2bce86448dfb1c9795a907d28ca2db6aaf5
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/ELF/InputSection.h
Log Message:
-----------
[ELF] Exclude sizeof(InputSection) to _WIN32
Structs with delicate packing are often larger in MSVC than Itanium.
099a52fd2f3723db6b0550c99a1adc12d2d8d909 did not make
sizeof(InputSection) smaller for MSVC. Just exclude MSVC.
Commit: ae01e3a7c66d68544c85dd6e2c5498d3c5896e29
https://github.com/llvm/llvm-project/commit/ae01e3a7c66d68544c85dd6e2c5498d3c5896e29
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[nfc][sancov] Remove unnecessary default argument (#117463)
Commit: 215f3dd5f6b82000bd61a5e8ff4a065baf8f4e3f
https://github.com/llvm/llvm-project/commit/215f3dd5f6b82000bd61a5e8ff4a065baf8f4e3f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[nfc][sancov] Remove unnecessary default argument (#117464)
Commit: 8d650736c19f2bd6a84dc29ec0becfceb357a739
https://github.com/llvm/llvm-project/commit/8d650736c19f2bd6a84dc29ec0becfceb357a739
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
Log Message:
-----------
[AMDGPU] Fix AMDGPUISD::TRAP description (#117453)
Glue operand is only present if there are variadic register operands,
which makes it optional.
Also, change the number of fixed operands to 1 (the trap ID).
Commit: c85c77c054f3e330c23501db115b1adc505b9805
https://github.com/llvm/llvm-project/commit/c85c77c054f3e330c23501db115b1adc505b9805
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
Log Message:
-----------
[AVR] Fix shift node descriptions (#117456)
Wide shift nodes produce two results, not one.
Reuse the added type profile to define the standard "shift parts" nodes.
Commit: 68a48ec90fb6609b964addcc99a55d16eee884a0
https://github.com/llvm/llvm-project/commit/68a48ec90fb6609b964addcc99a55d16eee884a0
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
Log Message:
-----------
[clang][analysis][NFC]place the comment to correct position (#117467)
Commit: eb4d2f24a7246ce05da789c9506201ce18638046
https://github.com/llvm/llvm-project/commit/eb4d2f24a7246ce05da789c9506201ce18638046
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M lld/Common/ErrorHandler.cpp
M lld/ELF/Driver.cpp
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Simplify reportMissingFeature. NFC
Commit: 5fa0345d90d60a90a1cc0cf33bab997c3e26b84e
https://github.com/llvm/llvm-project/commit/5fa0345d90d60a90a1cc0cf33bab997c3e26b84e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
Log Message:
-----------
[tsan] Unwind for CHECK according to fast_unwind_on_fatal (#117470)
It's needed for #116409, which hangs with slow
unwind.
Commit: 4d4a353b8eddb0728d5b278befdccda4de484319
https://github.com/llvm/llvm-project/commit/4d4a353b8eddb0728d5b278befdccda4de484319
Author: gbMattN <146744444+gbMattN at users.noreply.github.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_deadlock_detector.h
A compiler-rt/test/tsan/many_held_mutex.cpp
Log Message:
-----------
[TSan] Increase the number of simultaneously locked mutexes that a thread can hold (#116409)
I've run into an issue where TSan can't be used on some code without
turning off deadlock detection because a thread tries to hold too many
mutexes. It would be preferable to be able to use deadlock detection as
that is a major benefit of TSan.
Its mentioned in https://github.com/google/sanitizers/issues/950 that
the 64 mutex limit was an arbitrary number. I've increased it to 128 and
all the tests still pass. Considering the increasing number of cores on
CPUs and how programs can now use more threads to take advantage of it,
I think raising the limit to 128 would be some good future proofing
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 2af6ddb8a2cdc2a9a8a84a6244905bf9158cca8b
https://github.com/llvm/llvm-project/commit/2af6ddb8a2cdc2a9a8a84a6244905bf9158cca8b
Author: Théo Degioanni <theo.degioanni.llvm.deluge062 at simplelogin.fr>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/test/IR/properties.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir][ods] Fix missing property elision for variadic segment properties (#115930)
This fixes a bug where variadic segment properties would not be elided
when printing `prop-dict`.
Commit: bd7d6c806608b150b8aab87012afdbd3bed38c29
https://github.com/llvm/llvm-project/commit/bd7d6c806608b150b8aab87012afdbd3bed38c29
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 776476c282bca71d5b856e80e0a88fbd6f3ccdd2
Commit: c4d656a4e992648f3490536336c230041c74dc38
https://github.com/llvm/llvm-project/commit/c4d656a4e992648f3490536336c230041c74dc38
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependencies for a0ef12c64284abf59bc092b2535cce1247d5f9a4
Commit: f942949a7cf16a082eb43943b2a4f93f9180556f
https://github.com/llvm/llvm-project/commit/f942949a7cf16a082eb43943b2a4f93f9180556f
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/SymbolTable.cpp
M lld/test/COFF/arm64ec.test
Log Message:
-----------
[LLD][COFF] Require explicit specification of ARM64EC target (#116281)
Inferring the ARM64EC target can lead to errors. The `-machine:arm64ec`
option may include x86_64 input files, and any valid ARM64EC input is
also valid for `-machine:arm64x`. MSVC requires an explicit `-machine`
argument with informative diagnostics; this patch adopts the same
behavior.
Commit: 0c21ed48f40b2a6e3aa7e5d1873cf2455e847786
https://github.com/llvm/llvm-project/commit/0c21ed48f40b2a6e3aa7e5d1873cf2455e847786
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clang-tidy][NFC] fix release note order (#117484)
Commit: 7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
https://github.com/llvm/llvm-project/commit/7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
Author: Fabian Mora <6982088+fabianmcg at users.noreply.github.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h
A mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.td
A mlir/include/mlir/Conversion/GPUCommon/GPUToLLVM.h
A mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVM.h
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-target-attr.mlir
Log Message:
-----------
[mlir][LLVM] Add the `ConvertToLLVMAttrInterface` and `ConvertToLLVMOpInterface` interfaces (#99566)
This patch adds the `ConvertToLLVMAttrInterface` and
`ConvertToLLVMOpInterface` interfaces. It also modifies the
`convert-to-llvm` pass to use these interfaces when available.
The `ConvertToLLVMAttrInterface` interfaces allows attributes to
configure conversion to LLVM, including the conversion target, LLVM type
converter, and populating conversion patterns. See the `NVVMTargetAttr`
implementation of this interface for an example of how this interface
can be used to configure conversion to LLVM.
The `ConvertToLLVMOpInterface` interface collects all convert to LLVM
attributes stored in an operation.
Finally, the `convert-to-llvm` pass was modified to use these interfaces
when available. This allows applying `convert-to-llvm` to GPU modules
and letting the `NVVMTargetAttr` decide which patterns to populate.
Commit: 08bf901ed4a66d3afa8edbf167f658a2647147c5
https://github.com/llvm/llvm-project/commit/08bf901ed4a66d3afa8edbf167f658a2647147c5
Author: Xing Xue <xingxue at outlook.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
Log Message:
-----------
Revert "[AIX] Fix AIX BuildBot failure as AIX linker doesn't support version script." (#117444)
Commit
https://github.com/llvm/llvm-project/commit/eaa0a21d21962280dc2c03a09152510f6162a576
has fixed the build problem already so the change in
llvm/llvm-project#117342 does not make sense any more. I am reverting
it.
Commit: 63d9ef5e37539b8920eb6c93524e4be2c33a510c
https://github.com/llvm/llvm-project/commit/63d9ef5e37539b8920eb6c93524e4be2c33a510c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConcepts.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/AST/TemplateName.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#117469)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: aafe934c0c0c1d274099228e7e47669770235284
https://github.com/llvm/llvm-project/commit/aafe934c0c0c1d274099228e7e47669770235284
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
Log Message:
-----------
[hexagon] Require "asserts" build for widen-not-load test (#117414)
This test fails on the `clang-x64-windows-msvc` builder:
.---command stderr------------
|
C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\test\CodeGen\Hexagon\widen-not-load.ll:7:16:
error: CHECK-LABEL: expected string not found in input
| ; CHECK-LABEL: test1
| ^
| <stdin>:1:1: note: scanning from here
| llc.exe: Unknown command line argument
'-debug-only=hexagon-load-store-widening'. Try:
'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\llc.exe --help'
| ^
| <stdin>:1:35: note: possible intended match here
| llc.exe: Unknown command line argument
'-debug-only=hexagon-load-store-widening'. Try:
'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\llc.exe --help'
| ^
Commit: 6cfaddfd52d088c15a61b8149f39505019c73458
https://github.com/llvm/llvm-project/commit/6cfaddfd52d088c15a61b8149f39505019c73458
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
Log Message:
-----------
[X86] Split rr/rm CVT schedules on SNB/HSW/BDW (#117494)
The folded load variants almost never require Port5 for length changing conversions (just for SNB ymm cases), and don't typically use an extra uop for the load.
Confirmed with a mixture of Agner + uops.info comparisons.
Commit: 0a6d797c20f6ab53bc09fb66129f603ed6e4b524
https://github.com/llvm/llvm-project/commit/0a6d797c20f6ab53bc09fb66129f603ed6e4b524
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s
Log Message:
-----------
[X86] Improve F16C CVT schedules on SNB/HSW/BDW
Add complete IvyBridge schedule (which is included in the SandyBridge model, IvyBridge was the first to support F16C) - split rr/rm schedules as they usually have very different port usage.
Haswell/Broadwell use Port1 not Port0.
Confirmed with a mixture of Agner + uops.info comparisons.
Commit: ff97b283346273000a8140d6a3a8fcb5a1589946
https://github.com/llvm/llvm-project/commit/ff97b283346273000a8140d6a3a8fcb5a1589946
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/Common/ErrorHandler.cpp
M lld/ELF/Relocations.cpp
M lld/include/lld/Common/ErrorHandler.h
Log Message:
-----------
[ELF] Simplif reportUndefinedSymbol. NFC
Commit: c2ffb42893eb543f64169e32851e00352feaca69
https://github.com/llvm/llvm-project/commit/c2ffb42893eb543f64169e32851e00352feaca69
Author: Kazuki Sakamoto <sakamoto at splhack.org>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Fix TestLoadUnload.py (#117416)
ELF core debugging fix #117070 broke TestLoadUnload.py tests due to
GetModuleSpec call, ProcessGDBRemote fetches modules from remote. Revise
the original PR, renamed FindBuildId to FindModuleUUID.
Commit: 0dbdc6dc358bfe24d83c23ccc1c84c468ed24f30
https://github.com/llvm/llvm-project/commit/0dbdc6dc358bfe24d83c23ccc1c84c468ed24f30
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Simplify code to re-use existing basic blocks (NFCI).
Restructure and slightly simplify code to re-use existing basic blocks.
Commit: d8495ede01329e8636e43847517da1c9d80b896e
https://github.com/llvm/llvm-project/commit/d8495ede01329e8636e43847517da1c9d80b896e
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Relocations.cpp
Log Message:
-----------
[ELF] Change getLocation to use ELFSyncStream. NFC
Commit: 360718fb90cb60572c210ed4fa671128232cf3ba
https://github.com/llvm/llvm-project/commit/360718fb90cb60572c210ed4fa671128232cf3ba
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/test/ELF/linkerscript/symbol-location.s
Log Message:
-----------
[test] Improve symbol-location.s to check --defsym
Commit: c790d6f53f617b73c40d42a217c120023b9ab66f
https://github.com/llvm/llvm-project/commit/c790d6f53f617b73c40d42a217c120023b9ab66f
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/incompatible.s
Log Message:
-----------
[ELF] isCompatile: avoid a toStr and 2 ErrAlways
Commit: c4dc5ed8254e6b318200496d687b0a7b3163dc26
https://github.com/llvm/llvm-project/commit/c4dc5ed8254e6b318200496d687b0a7b3163dc26
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.h
Log Message:
-----------
[ELF] Avoid some toStr and ErrAlways
Commit: 1cd627562b8b66b5f9b0797fc45afcfa054daedd
https://github.com/llvm/llvm-project/commit/1cd627562b8b66b5f9b0797fc45afcfa054daedd
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Remove unneeded Twine in ELFSyncStream
Commit: 590f451b60d434b26c634a07125fb05baf461fa0
https://github.com/llvm/llvm-project/commit/590f451b60d434b26c634a07125fb05baf461fa0
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
Log Message:
-----------
[VPlan] Allow setting IR name for VPDerivedIVRecipe (NFCI).
Allow setting the name to use for the generated IR value of the derived
IV in preparations for https://github.com/llvm/llvm-project/pull/112145.
This is analogous to VPInstruction::Name.
Commit: 5ce4d4c77517f1bc9ad11b2637056b870f2bd156
https://github.com/llvm/llvm-project/commit/5ce4d4c77517f1bc9ad11b2637056b870f2bd156
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/test/Dialect/GPU/barrier-elimination.mlir
Log Message:
-----------
[mlir] fix memory effects in GPU barrier elimination (#117432)
Existing implementation may trigger infinite cycles when collecting
effects above or below the current block after wrapping around a
loop-like construct. Limit this case to only looking at the immediate
block (loop body). This is correct because wrap around is intended to
consider effects of different iterations of the same loop and shouldn't
be existing the loop block.
Reported-by: Fabian Mora <fmora.dev at gmail.com>
Co-authored-by: Fabian Mora <fmora.dev at gmail.com>
Commit: e3aafe407af36f580148d3ceccd1aa13a490f7c9
https://github.com/llvm/llvm-project/commit/e3aafe407af36f580148d3ceccd1aa13a490f7c9
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
Log Message:
-----------
[clang-tidy] fix false positive use-internal-linkage for func decl without body (#117490)
If in one TU, function only have declaration without body, this function
should be external linkage.
Fixed #117488
Commit: ae20dbdd63d97c342b89a72e9e839556d0deed07
https://github.com/llvm/llvm-project/commit/ae20dbdd63d97c342b89a72e9e839556d0deed07
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
Log Message:
-----------
[clang][analysis] refactor the unevaluated api (#117474)
It is hard to understand for `ExprMutationAnalyzer::isUnevaluated` to
accept 2 Stmt as parameters.
This patch wants to redesign the API to accept only 1 Stmt. Now it will
only check whether stmt is a sub-stmt of an unevaluated stmt.
Commit: 605b8dad5cb173ac86adb3541e9f70a824aff364
https://github.com/llvm/llvm-project/commit/605b8dad5cb173ac86adb3541e9f70a824aff364
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidConstOrRefDataMembersCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/avoid-const-or-ref-data-members.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in cppcoreguidelines-avoid-const-or-ref-data-members when detecting templated classes with inheritance (#115180)
`hasSimpleCopyConstructor` series of functions are not reliable when
these functions are not resolved. We need to manually resolve the status
of these functions from its base classes.
Fixes: #111985.
Commit: 3c344f92e62ac07faf5df68d73ad765b11f465f2
https://github.com/llvm/llvm-project/commit/3c344f92e62ac07faf5df68d73ad765b11f465f2
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[clang][tablegen][NFC]add static for internal linkage function (#117479)
Detected by misc-use-internal-linkage
Commit: cbdd14ee9de72c277d9f89a6aa57c54a495f5458
https://github.com/llvm/llvm-project/commit/cbdd14ee9de72c277d9f89a6aa57c54a495f5458
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[clang][NFC]add static for internal linkage function (#117482)
Detected by misc-use-internal-linkage
Commit: 2a5e3a67a0248db4a6981e343f0033a32ad4a577
https://github.com/llvm/llvm-project/commit/2a5e3a67a0248db4a6981e343f0033a32ad4a577
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/lib/AST/APValue.cpp
Log Message:
-----------
[AST] Fix a warning
This patch fixes:
clang/lib/AST/APValue.cpp:1091:1: error: unused function
'setLValueUninit' [-Werror,-Wunused-function]
Commit: 095f489757ead08184dd340f14a7b6158db6b0a3
https://github.com/llvm/llvm-project/commit/095f489757ead08184dd340f14a7b6158db6b0a3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/test/tools/llvm-mca/X86/SapphireRapids/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-adx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-aes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalgvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cd.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cdvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifmavl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaesvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-fma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lea.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x87.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/zero-idioms.s
Log Message:
-----------
[X86] Swap ports 10 and 11 in SapphireRapids Scheduling Model (#117468)
Based on intel/perfmon#149, the documentation is incorrect and the pfm
counter names are actually correct. This patch adjusts the
SapphireRapids scheduling model to match the performance counter naming/
correct naming that will soon be reflected in the optimization manual.
This fixes part of #117360.
Commit: 512dc5cb32e65081f4481afc757beade9bd64d04
https://github.com/llvm/llvm-project/commit/512dc5cb32e65081f4481afc757beade9bd64d04
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
Log Message:
-----------
[X86] Swap ports 10 and 11 in Alder Lake Scheduling Model (#117466)
Based on https://github.com/intel/perfmon/issues/149, the documentation
is incorrect and the pfm counter names are actually correct. This patch
adjusts the Alder Lake scheduling model to match the performance counter
naming/ correct naming that will soon be reflected in the optimization
manual.
This fixes part of #117360.
Commit: 5ed09d552d51825e495aebf38988beba83dbbca9
https://github.com/llvm/llvm-project/commit/5ed09d552d51825e495aebf38988beba83dbbca9
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Support/Compression.cpp
Log Message:
-----------
[Support] Check zstd decompress result before msan unpoison (#117276)
We should check the zstd decompress result before doing the msan
unpoison. If the res is abnormal, then it would be a huge number, which
will cause undesired msan unpoison behavior and will run for a long
time.
Commit: 6aeffa18e9ac51b7090325ea50d1841248a876c6
https://github.com/llvm/llvm-project/commit/6aeffa18e9ac51b7090325ea50d1841248a876c6
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lld/ELF/DriverUtils.cpp
M lld/test/ELF/reproduce.s
Log Message:
-----------
[ELF] --reproduce: strip directories for --dependency-file=
CMake may generate build.ninja with DEP_FILE specifying a non-existent
directory in the reproduce tarball.
Commit: e70f9e20964161abd3518d77b9efc736c6b6255e
https://github.com/llvm/llvm-project/commit/e70f9e20964161abd3518d77b9efc736c6b6255e
Author: Weining Lu <luweining at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[LoongArch] Remove the added in #116762
Commit: 02408d6b28951b2e094d00a70a398883c6b0cb33
https://github.com/llvm/llvm-project/commit/02408d6b28951b2e094d00a70a398883c6b0cb33
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
Log Message:
-----------
[VP] Refactoring some functions in ExpandVectorPredication.NFC (#115840)
Building vp intrinsic functions using a unified interface for
expandPredicationToIntCall/expandPredicationToFPCall/expandPredicationToCastIntrinsic
functions.
Commit: 5f3eab9e453c0237ccfafb6775b5af55bf028c84
https://github.com/llvm/llvm-project/commit/5f3eab9e453c0237ccfafb6775b5af55bf028c84
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRISelLowering.cpp
Log Message:
-----------
[AVR] Remove extra ROL / ROR operands (#117510)
The nodes have one input, shift amount of 1 is implied.
Commit: bb5bbe523d4437d72287f89fbaa277aaa71c0bd2
https://github.com/llvm/llvm-project/commit/bb5bbe523d4437d72287f89fbaa277aaa71c0bd2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Support s32/s64 G_FSUB/FDIV/FNEG without F/D extensions.
Use libcalls for G_FSUB/FDIV. Use integer operations for G_FNEG.
Copy most of the IR tests for arithmetic from SelectionDAG.
Commit: 345ca6a69203fe8ad17cf35da88e6a490679a2e7
https://github.com/llvm/llvm-project/commit/345ca6a69203fe8ad17cf35da88e6a490679a2e7
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: extra signature conversion check (#117471)
This commit adds an extra assertion to `applySignatureConversion` to
prevent incorrect API usage: The same block cannot be converted multiple
times. That would mess with the underlying conversion value mapping.
(Mappings would be overwritten.) This is similar to op replacements: The
same op cannot be replaced multiple times.
To simplify the check, `BlockTypeConversionRewrite::block` now stores
the original block. The new block is stored in an extra field. (It used
to be the other way around.)
This commit is in preparation of adding 1:N support to the conversion
value mapping. Before making any further changes to the mapping
infrastructure, I'd like to make sure that the code base around it (that
uses the mapping) is robust.
Commit: 0bfc9514715b3beb967f1a245e9db310d2aafa50
https://github.com/llvm/llvm-project/commit/0bfc9514715b3beb967f1a245e9db310d2aafa50
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
Log Message:
-----------
[lldb] Remove lldbutil.get_stack_frames (NFC) (#117505)
`SBThread.frames` can be used instead of `get_stack_frames`.
Commit: e26af0938c7a272cf0de11c92aa069485868e130
https://github.com/llvm/llvm-project/commit/e26af0938c7a272cf0de11c92aa069485868e130
Author: hev <wangrui at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
Log Message:
-----------
[llvm] Add `BasicTTIImpl::areInlineCompatible` for target feature subset checks (#117493)
This patch moves the `areInlineCompatible` implementation from multiple
subclasses (`AArch64TTIImpl`, `RISCVTTIImpl`, `WebAssemblyTTIImpl`) to
the base class `BasicTTIImpl`. The new implementation checks whether the
callee's target features are a subset of the caller's, enabling
consistent behavior across targets. Subclasses now simply delegate to
the base implementation, reducing code duplication and improving
maintainability.
Commit: 3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
https://github.com/llvm/llvm-project/commit/3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
Log Message:
-----------
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
This makes (fcopysign X, (fneg Y)) patterns work.
Commit: 2523439021dedbaee1ddfc49f59deab43cf6bb9b
https://github.com/llvm/llvm-project/commit/2523439021dedbaee1ddfc49f59deab43cf6bb9b
Author: hev <wangrui at loongson.cn>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll
A llvm/test/Transforms/Inline/LoongArch/lit.local.cfg
Log Message:
-----------
[LoongArch] Add a test case for inline compatibility checks (#117144)
Commit: 7317a6e99026f65a343e2e69685445dc5bd83172
https://github.com/llvm/llvm-project/commit/7317a6e99026f65a343e2e69685445dc5bd83172
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
A llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
Log Message:
-----------
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)
For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.
This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.
Commit: 87cc4b48c08a627f330396f941b84671c5e591d5
https://github.com/llvm/llvm-project/commit/87cc4b48c08a627f330396f941b84671c5e591d5
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
Log Message:
-----------
[NFC] Fix buildbot fail by add riscv64-registered-target
Commit: 9e3215ac167b80dcf51d6693ecdd6275c4e89954
https://github.com/llvm/llvm-project/commit/9e3215ac167b80dcf51d6693ecdd6275c4e89954
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfWriter.cpp
Log Message:
-----------
[memprof] Add an assert to InstrProfWriter::addMemProfData (#117426)
This patch adds a quick validity check to
InstrProfWriter::addMemProfData. Specifically, we check to see if we
have all (or none) of the MemProf profile components (frames, call
stacks, records).
The credit goes to Teresa Johnson for suggesting this assert.
Commit: ff7b42c194e0fa23e6a76f0a33a80c0c3af14e7d
https://github.com/llvm/llvm-project/commit/ff7b42c194e0fa23e6a76f0a33a80c0c3af14e7d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Speed up llvm-profdata (#117446)
CallStackRadixTreeBuilder::build takes the parameter
MemProfFrameIndexes by value, involving copies:
std::optional<const llvm::DenseMap<FrameIdTy, LinearFrameId>>
MemProfFrameIndexes
Then "build" makes another copy of MemProfFrameIndexe and passes it to
encodeCallStack for every call stack, which is painfully slow.
This patch changes the type to a pointer so that we don't have to make
a copy every time we pass the argument.
Without this patch, it takes 553 seconds to run "llvm-profdata merge"
on a large MemProf raw profile. This patch shortenes that down to 67
seconds.
Commit: 73bebf96bc21dcc01a8eccfb4ece200c1c665931
https://github.com/llvm/llvm-project/commit/73bebf96bc21dcc01a8eccfb4ece200c1c665931
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Update the position of some parameters in the vp intrinsic of abs/cttz/ctlz (#117519)
Commit: b9731a479cb053cd07cc5f460b097c5f2d5f396e
https://github.com/llvm/llvm-project/commit/b9731a479cb053cd07cc5f460b097c5f2d5f396e
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-24 (Sun, 24 Nov 2024)
Changed paths:
M clang/docs/ClangFormat.rst
M clang/include/clang/Format/Format.h
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format][doc] Minor cleanup
Commit: 2568e52a733a9767014e0d8ccb685553479a3031
https://github.com/llvm/llvm-project/commit/2568e52a733a9767014e0d8ccb685553479a3031
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
Log Message:
-----------
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part II) (#108812)
This is a follow up of #96878 to support hoisting load/store from BBs
have the same predecessor, if load/store are the only instructions and
the branch is unpredictable, e.g.:
```
void test (int a, int *c, int *d) {
if (a)
*c = a;
else
*d = a;
}
```
Commit: b0bdbf4288a664179024eead871a5e7b7fae6dda
https://github.com/llvm/llvm-project/commit/b0bdbf4288a664179024eead871a5e7b7fae6dda
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/7498eaa9abf2e4ac0c10fa9a02576d708cc1b624
Commit: 2585b6e8faf68d1d10ce0f356c4fede5876da6d2
https://github.com/llvm/llvm-project/commit/2585b6e8faf68d1d10ce0f356c4fede5876da6d2
Author: Christian Sigg <csigg at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix layering check failure.
Commit: df335b09eac8a48d9afc06d71a86646ff6b08131
https://github.com/llvm/llvm-project/commit/df335b09eac8a48d9afc06d71a86646ff6b08131
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
Log Message:
-----------
[Clang] Preserve partially substituted pack indexing type/expressions (#116782)
Substituting into pack indexing types/expressions can still result in
unexpanded types/expressions, such as `PackIndexingType` or
`PackIndexingExpr`. To handle these cases correctly, we should defer the
pack size checks to the next round of transformation, when the patterns
can be fully expanded.
To that end, the `FullySubstituted` flag is now necessary for computing
the dependencies of `PackIndexingExprs`. Conveniently, this flag can
also represent the prior `ExpandsToEmpty` status with an additional
emptiness check. Therefore, I converted all stored flags to use
`FullySubstituted`.
Fixes https://github.com/llvm/llvm-project/issues/116105
Commit: 404d0e9966a46c29e6539e20d9295adcbc8bf9bf
https://github.com/llvm/llvm-project/commit/404d0e9966a46c29e6539e20d9295adcbc8bf9bf
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/lib/Bindings/Python/IRAttributes.cpp
Log Message:
-----------
[mlir] Adjust code flagged by ClangTidyPerformance (NFC).
We can allocate the size of the vector in advance.
Commit: 0fe12a7db3f6663c9f2572ff0232e56f1bd411ae
https://github.com/llvm/llvm-project/commit/0fe12a7db3f6663c9f2572ff0232e56f1bd411ae
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
Log Message:
-----------
[clang-format][NFC] Remove a pointer in ContinuationIndenter
Commit: 815a1bb53a9bb753f9aea177135150b23012550f
https://github.com/llvm/llvm-project/commit/815a1bb53a9bb753f9aea177135150b23012550f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
Log Message:
-----------
[SystemZ] Use getSignedConstant() where necessary (#117181)
This will avoid assertion failures once we disable implicit truncation
in getConstant().
Inside adjustSubwordCmp() I ended up suppressing the issue with an
explicit cast, because this code deals with a mix of unsigned and signed
immediates.
Commit: 3317c9ceac0f362298a0871e9d2bc30ef0f1e1b5
https://github.com/llvm/llvm-project/commit/3317c9ceac0f362298a0871e9d2bc30ef0f1e1b5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
Log Message:
-----------
[AMDGPU] Use getSignedConstant() where necessary (#117328)
Create signed constant using getSignedConstant(), to avoid future
assertion failures when we disable implicit truncation in getConstant().
This also touches some generic legalization code, which apparently only
AMDGPU tests.
Commit: 55f5d68c2da1b9dda522fdd862ed53f18166fa44
https://github.com/llvm/llvm-project/commit/55f5d68c2da1b9dda522fdd862ed53f18166fa44
Author: Hans <hans at hanshq.net>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] Recognize mov QWORD PTR [rip + X], reg (#117335)
This comes up when intercepting clang-built `__sanitizer_cov` functions.
Commit: 6512e488f6a118fc781fc39ccb79766e11359048
https://github.com/llvm/llvm-project/commit/6512e488f6a118fc781fc39ccb79766e11359048
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lld/ELF/InputSection.cpp
A lld/test/ELF/arm-rwpi-debug-relocs.s
Log Message:
-----------
[LLD][ARM] Allow R_ARM_SBREL32 relocations in debug info (#116956)
The R_ARM_SBREL32 relocation is used in debug info for ARM RWPI
(read-write position independent) code. Compiler-generated DWARF info
will use an expression to add the relocated value to the actual value of
the static base (held in r9) at run-time, so it should be relocated as
if the static base is at address 0.
Commit: 1bc98957c898d7e7233746a7b284982d20539593
https://github.com/llvm/llvm-project/commit/1bc98957c898d7e7233746a7b284982d20539593
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
[lldb/DWARF] Remove duplicate type filtering (#116989)
In #108907, the index classes started filtering the DIEs according to
the full type query (instead of just the base name). This means that the
checks in SymbolFileDWARF are now redundant.
I've also moved the non-redundant checks so that now all checking is
done in the DWARFIndex class and the caller can expect to get the final
filtered list of types.
Commit: 866755f8da588ec2efbcac60679b9d9f5c4636a9
https://github.com/llvm/llvm-project/commit/866755f8da588ec2efbcac60679b9d9f5c4636a9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update backend maintainer (#116622)
We currently list Evan Cheng as the fallback maintainer for the LLVM
backend. However, their last contribution dates back to 2014.
I'd like to nominate arsenm instead, who is our most active backend
reviewer.
Commit: d35098bfa8e1e213f85a6b5035a5a7102f5da315
https://github.com/llvm/llvm-project/commit/d35098bfa8e1e213f85a6b5035a5a7102f5da315
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/IR/AttrTypeBase.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
Log Message:
-----------
[mlir][LLVM][NFC] Move `LLVMStructType` to ODS (#117485)
This PR extracts NFC changes out of
https://github.com/llvm/llvm-project/pull/116035 to reap as many of the
same benefits without any of the semantic changes.
More concretely, moving `LLVMStructType` to ODS has the benefits of
being able to generate much of the required boilerplate, such as
interface definitions, documentation and more, automatically.
Furthermore, `LLVMStructType` is then treated less special and its
definition can be found at the same place where all other complex type
definitions are found in the LLVM dialect.
Future changes could leverage more automatically generated code from
TableGen such as `assemblyFormat`. As these are not as trivial, they
have been left for future PRs.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: 2b5e2d74d38274e783ccf0de37aa106c76816f9e
https://github.com/llvm/llvm-project/commit/2b5e2d74d38274e783ccf0de37aa106c76816f9e
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
Log Message:
-----------
[AArch64][GlobalISel] Extend arm64-vshift.ll test coverage. NFC
Commit: 7d8d51ed3409cae96fb975281deca2babf4f9994
https://github.com/llvm/llvm-project/commit/7d8d51ed3409cae96fb975281deca2babf4f9994
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-target-version-unsupported.c
Log Message:
-----------
Recommit "[TargetVersion] Only enable on RISC-V and AArch64" (#117110)" (#117128)
Remain InheritableAttr to avoid the warning `TypePrinter.cpp:1953:10:
warning: enumeration value ‘TargetVersion’ not handled in switch`
origin messenge
[TargetVersion] Only enable on RISC-V and AArch64 (#115991) Address
#115000.
This patch constrains the target_version feature to work only on RISC-V
and AArch64 to prevent crashes in Clang.
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: e5faeb69fbb87722ee315884eeef2089b10b0cee
https://github.com/llvm/llvm-project/commit/e5faeb69fbb87722ee315884eeef2089b10b0cee
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
Log Message:
-----------
[InstCombine] Support reassoc for foldLogicOfFCmps (#116065)
We currently support simple reassociation for foldAndOrOfICmps().
Support the same for foldLogicOfFCmps() by going through the common
foldBooleanAndOr() helper.
This will also resolve the regression on #112704, which is also due to
missing reassoc support.
I had to adjust one fold to add support for FMF flag preservation,
otherwise there would be test regressions. There is a separate fold
(reassociateFCmps) handling reassociation for *just* that specific case
and it preserves FMF. Unfortunately it's not rendered entirely redundant
by this patch, because it handles one more level of reassociation as
well.
Commit: 22ec44f509ff266b581dbb490d7b040473b7c31a
https://github.com/llvm/llvm-project/commit/22ec44f509ff266b581dbb490d7b040473b7c31a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
A llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)
For IR like this:
%icmp = icmp ult <4 x i32> %a, splat (i32 5)
%res = extractelement <4 x i1> %icmp, i32 1
where there is only one use of %icmp we can take a similar approach
to what we already do for binary ops such add, sub, etc. and convert
this into
%ext = extractelement <4 x i32> %a, i32 1
%res = icmp ult i32 %ext, 5
For AArch64 targets at least the scalar boolean result will almost
certainly need to be in a GPR anyway, since it will probably be
used by branches for control flow. I've tried to reuse existing code
in scalarizeExtractedBinop to also work for setcc.
NOTE: The optimisations don't apply for tests such as
extract_icmp_v4i32_splat_rhs in the file
CodeGen/AArch64/extract-vector-cmp.ll
because scalarizeExtractedBinOp only works if one of the input
operands is a constant.
Commit: 321fe747957703ec1d17b59b5e3ed96f58cfdb12
https://github.com/llvm/llvm-project/commit/321fe747957703ec1d17b59b5e3ed96f58cfdb12
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
Log Message:
-----------
[InstCombine] Add extra test for eq of parts fold (NFC)
To guard against regression from #112704.
Commit: db140104054d5af588e26c36ad5faadbb599de1e
https://github.com/llvm/llvm-project/commit/db140104054d5af588e26c36ad5faadbb599de1e
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/abs.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement cost of intrinsic abs with LMUL (#115813)
Commit: 84fec7757ea330bbaf82b46ed081ccc45b120e45
https://github.com/llvm/llvm-project/commit/84fec7757ea330bbaf82b46ed081ccc45b120e45
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M lldb/docs/use/aarch64-linux.md
Log Message:
-----------
[lldb][docs] Clarify unit for SVE P register size
Commit: c537c752787e9da8bd8762dd5298a152f546861b
https://github.com/llvm/llvm-project/commit/c537c752787e9da8bd8762dd5298a152f546861b
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Log Message:
-----------
[AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
As with other operations we scalarize any vectors with larger types to let the
scalare legalization kick in.
Commit: f81f47e3ff29598fdf58cde94ccf2c7d4be53df5
https://github.com/llvm/llvm-project/commit/f81f47e3ff29598fdf58cde94ccf2c7d4be53df5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/fptrunc.ll
Log Message:
-----------
[InstCombine] Add fptrunc of max test (NFC)
To guard against regression from #117182.
Commit: 15fadeb2aa8b9f27a5a45f15832e73ef79cfe407
https://github.com/llvm/llvm-project/commit/15fadeb2aa8b9f27a5a45f15832e73ef79cfe407
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost for @llvm.experimental.vp.splat (#117313)
This is split off from #115274. There doesn't seem to be an easy way to
share this with getShuffleCost since that requires passing in a real
insert_element operand to get it to recognise it's a scalar splat.
For i1 vectors we can't currently lower them so it returns an invalid
cost.
---------
Co-authored-by: Shih-Po Hung <shihpo.hung at sifive.com>
Commit: 48ec59c234ce267a0454b15e9a79a326e21a4a97
https://github.com/llvm/llvm-project/commit/48ec59c234ce267a0454b15e9a79a326e21a4a97
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
Log Message:
-----------
[llvm][AMDGPU] Fold `llvm.amdgcn.wavefrontsize` early (#114481)
Fold `llvm.amdgcn.wavefrontsize` early, during InstCombine, so that it's
concrete value is used throughout subsequent optimisation passes.
Commit: 612f8ec7ac5dcddd16fb027aad64e2e353faa528
https://github.com/llvm/llvm-project/commit/612f8ec7ac5dcddd16fb027aad64e2e353faa528
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/flush_ast_print.cpp
M clang/test/OpenMP/flush_codegen.cpp
M clang/test/OpenMP/flush_messages.cpp
A flang/test/Lower/OpenMP/Todo/flush-seq-cst.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/flush02.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
seq_cst is allowed in Flush since OpenMP 5.1. (#114072)
This PR adds support seq_cst (sequential consistency) clause for the
flush directive in OpenMP. The seq_cst clause enforces a stricter memory
ordering, ensuring that all threads observe the memory effects of the
flush in the same order, improving consistency in memory operations
across threads.
---------
Co-authored-by: Shashwathi N <nshashwa at pe28vega.hpc.amslabs.hpecorp.net>
Co-authored-by: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Commit: e477989a055f92f6ca63fc8f76929cde81d33e44
https://github.com/llvm/llvm-project/commit/e477989a055f92f6ca63fc8f76929cde81d33e44
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
Log Message:
-----------
[InstCombine] Handle trunc i1 pattern in eq-of-parts fold (#112704)
Equality/inequality of the low bit can be represented by `(trunc (xor x,
y) to i1)`, possibly with an extra not. We have to handle this in the
eq-of-parts fold now that we no longer canonicalize this to a masked
icmp.
Proofs: https://alive2.llvm.org/ce/z/qidkzq
Fixes https://github.com/llvm/llvm-project/issues/110919.
Commit: ceaf6e912a846b88f19df682c6bdbe9516be04e9
https://github.com/llvm/llvm-project/commit/ceaf6e912a846b88f19df682c6bdbe9516be04e9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Support ImplicitValueInitExpr for multi-dim arrays (#117312)
The attached test case from
https://github.com/llvm/llvm-project/issues/117294 used to cause an
assertion because we called classifPrim() on an array type.
The new result doesn't crash but isn't exactly perfect either. Since the
problem arises when evaluating an ImplicitValueInitExpr, we have no
proper source location to point to. Point to the caller instead.
Commit: 535247841d8635bc998ec0ec4871ea22f27caba6
https://github.com/llvm/llvm-project/commit/535247841d8635bc998ec0ec4871ea22f27caba6
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Remove comments from generated validateOperandClass (#117352)
This generated comments like:
// 'BoolReg' class
case MCK_BoolReg: {
which seem redundant because the name is always repeated on the next
line as part of the MCK_ enumerator.
Commit: 8c5a3a97c0d061880d6705db8f000aa964c3e32d
https://github.com/llvm/llvm-project/commit/8c5a3a97c0d061880d6705db8f000aa964c3e32d
Author: Jefferson Le Quellec <jefferson.lequellec at codeplay.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/docs/PatternRewriter.md
Log Message:
-----------
[mlir][docs] Update MLIR's PatternRewriter documentation (#116183)
This PR adds the missing `const override` to the `rewrite` and
`matchAndRewrite` declaration in the Pattern Rewriter documentation as
described here:
https://github.com/llvm/llvm-project/blob/5cfa8baef33636827e5aa8dd76888c724433b53e/mlir/include/mlir/IR/PatternMatch.h#L237-L265
Commit: b5a11d378db4b39ceb085ebd59c941e9369d9596
https://github.com/llvm/llvm-project/commit/b5a11d378db4b39ceb085ebd59c941e9369d9596
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
[SelectOpt] Refactor to prepare for support more select-like operations (#115745)
* Enables conversion of several select-like instructions within one
group
* Any number of auxiliary instructions depending on the same condition
can be in between select-like instructions
* After splitting the basic block, move select-like instructions into
the relevant basic blocks and optimise them
* Make it easier to add support shift-base select-like instructions and
also any mixture of zext/sext/not instructions
Commit: 4b71b3782d217db0138b701c4514bd2168ca1659
https://github.com/llvm/llvm-project/commit/4b71b3782d217db0138b701c4514bd2168ca1659
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
A bolt/unittests/Core/MemoryMaps.cpp
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
Log Message:
-----------
[BOLT] DataAggregator support for binaries with multiple text segments (#92815)
When a binary has multiple text segments, the Size is computed as the
difference of the last address of these segments from the BaseAddress.
The base addresses of all text segments must be the same.
Introduces flag 'perf-script-events' for testing. It allows passing perf events
without BOLT having to parse them using 'perf script'. The flag is used to
pass a mock perf profile that has two memory mappings for a mock binary
that has two text segments. The size of the mapping is updated as this
change `parseMMapEvents` processes all text segments.
Commit: 957c2ac4f17ab5cc1e4a13c99ed968dcaac1dd91
https://github.com/llvm/llvm-project/commit/957c2ac4f17ab5cc1e4a13c99ed968dcaac1dd91
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M bolt/utils/bughunter.sh
Log Message:
-----------
[BOLT] Fix for bughunter.sh in offline mode (#116649)
In offline mode, the script sets 'PASS' variable and does not use it.
Surrounding code suggests using 'FAIL' variable instead.
Commit: b4d49fb52e2068cdf4944dc0783c3ef691c946c4
https://github.com/llvm/llvm-project/commit/b4d49fb52e2068cdf4944dc0783c3ef691c946c4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Remove RPC server API and use the header directly (#117075)
Summary:
This patch removes much of the `llvmlibc_rpc_server` interface. This
pretty much deletes all of this code and just replaces it with including
`rpc.h` directly. We still maintain the file to let `libc` handle the
opcodes, since those depend on the `printf` impelmentation.
This will need to be cleaned up more, but I don't want to put too much
into a single patch.
Commit: 0ccc3895126aaa94ae3fe890fcca0ad69658bbab
https://github.com/llvm/llvm-project/commit/0ccc3895126aaa94ae3fe890fcca0ad69658bbab
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc_util.h
Log Message:
-----------
[libc] Make RPC header work with GCC9
Commit: 52755ac2531529369f1f29b9d0b29645f304f389
https://github.com/llvm/llvm-project/commit/52755ac2531529369f1f29b9d0b29645f304f389
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Lower/OpenMP/Todo/map-mapper.f90
M flang/test/Parser/OpenMP/from-clause.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
M flang/test/Parser/OpenMP/target-update-to-clause.f90
M flang/test/Semantics/OpenMP/combined-constructs.f90
M flang/test/Semantics/OpenMP/defaultmap-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/map-clause.f90
M flang/test/Semantics/OpenMP/map-modifiers.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
Log Message:
-----------
[flang][OpenMP] Use new modifier infrastructure for MAP/FROM/TO clauses (#117447)
This removes the specialized parsers and helper classes for these
clauses, namely ConcatSeparated, MapModifiers, and MotionModifiers. Map
and the motion clauses are now handled in the same way as all other
clauses with modifiers, with one exception: the commas separating their
modifiers are optional. This syntax is deprecated in OpenMP 5.2.
Implement version checks for modifiers: for a given modifier on a given
clause, check if that modifier is allowed on this clause in the
specified OpenMP version. This replaced several individual checks.
Add a testcase for handling map modifiers in a different order, and for
diagnosing an ultimate modifier out of position.
Commit: 506ca19dc9d6a9f0ad47b82e71525743bbe8cf85
https://github.com/llvm/llvm-project/commit/506ca19dc9d6a9f0ad47b82e71525743bbe8cf85
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/DeviceRTL/src/Mapping.cpp
M offload/test/offloading/ompx_bare_ballot_sync.c
M offload/test/offloading/ompx_bare_shfl_down_sync.cpp
Log Message:
-----------
[OpenMP] Remove use of '__AMDGCN_WAVEFRONT_SIZE' (#113156)
Summary:
This is going to be deprecated in
https://github.com/llvm/llvm-project/pull/112849. This patch ports it to
use the builtin instead. This isn't a compile constant, so it could
slightly negatively affect codegen. There really should be an IR pass to
turn it into a constant if the function has known attributes.
Using the builtin is correct when we just do it for knowing the size
like we do here. Obviously guarding w32/w64 code with this check would
be broken.
Commit: 4715dec8c0200d2c57176e08ce3d7ce88776828d
https://github.com/llvm/llvm-project/commit/4715dec8c0200d2c57176e08ce3d7ce88776828d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Log Message:
-----------
[XTensa] Use getSignedConstant() for negative values
Commit: 3699931dee058c02f52818529b4e6b53613a2dc2
https://github.com/llvm/llvm-project/commit/3699931dee058c02f52818529b4e6b53613a2dc2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
Log Message:
-----------
[M68k] Use getSignedConstant() where necessary
Commit: 18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
https://github.com/llvm/llvm-project/commit/18abc7e0c5b34e9e7bbe0893a4a5281c0937f7d8
Author: David Green <david.green at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Log Message:
-----------
[PatternMatch] Introduce m_c_Select (#114328)
This matches m_Select(m_Value(), L, R) or m_Select(m_Value(), R, L).
Commit: 9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
https://github.com/llvm/llvm-project/commit/9b76e7fc603071baf6c30f0daaf4f4d5429a8a1b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
R llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
Revert "[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)" (#117556)
This reverts commit 22ec44f509ff266b581dbb490d7b040473b7c31a.
Commit: 6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
https://github.com/llvm/llvm-project/commit/6f16a8bf17ac9a171b5435ee53c3d2bef657bdad
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/c23.c
Log Message:
-----------
[clang][bytecode] Use bitcasts to cast from integer to vector (#117547)
In C, a cast from an integer to a vector is a CK_BitCast. Implement this
using the same code we use for __builtin_bit_cast.
Commit: 2d62daab497bfe1991869dc090c7d20a71108360
https://github.com/llvm/llvm-project/commit/2d62daab497bfe1991869dc090c7d20a71108360
Author: David Truby <david.truby at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Fir/struct-return-aarch64.fir
Log Message:
-----------
[flang] AArch64 support for BIND(C) derived return types (#114051)
This patch adds support for BIND(C) derived types as return values
matching the AArch64 Procedure Call Standard for C.
Support for BIND(C) derived types as value parameters will be in a
separate patch.
Commit: 809c5ac3b0d78f504d93717ac4c0a02816cf47bb
https://github.com/llvm/llvm-project/commit/809c5ac3b0d78f504d93717ac4c0a02816cf47bb
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
[X86] Modify tests for constrained rounding functions (#116951)
The existing tests for constrained functions often use constant
arguments. If constant evaluation is enhanced, such tests will not check
code generation of the tested functions. To avoid it, the tests are
modified to use loaded value instead of constants. Now only the tests
for rounding functions are changed.
Commit: 06cb5c9d2c24e7560fcafd911fb145b96e96a675
https://github.com/llvm/llvm-project/commit/06cb5c9d2c24e7560fcafd911fb145b96e96a675
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update ARM maintainers (#117002)
Move rengolin and asl to former maintainers, and add davemgreen,
ostannard, nasherm, smithp35 and stuji from ARM as current
maintainers (with a focus area for some).
Commit: 4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
https://github.com/llvm/llvm-project/commit/4a7a27cb1c5b7fd1acd69b0b91d5eee9391bd4c0
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt.ll
Log Message:
-----------
Revert "[SelectOpt] Refactor to prepare for support more select-like operations (#115745)"
This reverts commit b5a11d378db4b39ceb085ebd59c941e9369d9596.
Commit: a5506a39e0ae8de77136334659b526e5f224850d
https://github.com/llvm/llvm-project/commit/a5506a39e0ae8de77136334659b526e5f224850d
Author: Yadong Chen <cyd.matt at qq.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp assembly (#116943)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.
Changes:
updates the PtrAccessChainOp and InBoundPtrAccessChainOp defined in
SPIRVMemoryOps.td to use assemblyFormat. Removes part print/parse from
MemoryOps.cpp which is now generated by assemblyFormat
Updates tests to updated format
Issue: #73359
Commit: 6de97e9a679aaf3148d467e4d4e1ea99ba55d555
https://github.com/llvm/llvm-project/commit/6de97e9a679aaf3148d467e4d4e1ea99ba55d555
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/cmake/modules/prepare_libc_gpu_build.cmake
Log Message:
-----------
[libc] Allow NVPTX targets to build in debug mode
Summary:
This previously did not work, but recent improvements to the NVPTX
backend allow this to work now.
Commit: 387be04dde0a2618d2baf37a4652a076c003b4a2
https://github.com/llvm/llvm-project/commit/387be04dde0a2618d2baf37a4652a076c003b4a2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/shared/rpc.h
Log Message:
-----------
[libc][NFC] Add const to RPC header members
Summary:
Make sure that these don't get modified.
Commit: 7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
https://github.com/llvm/llvm-project/commit/7800d59f5bd03e38db0bbe94db5f8a3e0ec1a9a6
Author: thetruestblue <bblueconway at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/SanitizerCoverage.rst
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[SanitizerCoverage] Add gated tracing callbacks support to trace-cmp (#113227)
The option -sanitizer-coverage-gated-trace-callbacks gates the
invocation of the trace-pc-guard callbacks based on the value of a
global variable, which is stored in a specific section.
In this commit, we extend this feature to trace-cmp and gate the cmp
callbacks to the same variable used for trace-pc-guard.
Update SanitizerCoverage doc with this flag.
rdar://135404160
Patch by: Andrea Fioraldi
Commit: f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
https://github.com/llvm/llvm-project/commit/f9dca5bdbb0fccc0c12c7f8f1a190fa05f72f90d
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
Log Message:
-----------
[ADT] Add convenience function `filter_to_vector` (#117460)
This materializes a filter range as a small vector.
Similar to `map_to_vector`, this new utility function lives in the
`SmallVectorExtras.h` header.
Commit: 7e3187e12a2cef8b2552e08ce9423aca9c09d813
https://github.com/llvm/llvm-project/commit/7e3187e12a2cef8b2552e08ce9423aca9c09d813
Author: ddubov100 <155631080+ddubov100 at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/include/mlir/Interfaces/TilingInterface.td
Log Message:
-----------
Adding mlir prefix for missing places in TilingInterface.td (#117495)
Commit: 57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
https://github.com/llvm/llvm-project/commit/57bbdbd7ae3698a274edd4dd6ef1b53d9129e552
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
Log Message:
-----------
[SLP]Relax assertion in mask combine for non-power-of-2 number of elements
The nodes may contain non-power-of-2 number of elements. Need to relax
the assertion to avoid possible compiler crash
Fixes #117517
Commit: 1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
https://github.com/llvm/llvm-project/commit/1b18ce57f3d9bef4a97c4dd002570b3441ac85e5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
Log Message:
-----------
[X86] vector-interleaved-load-i16-stride-2.ll - regenerate with AVX512 common prefix
Commit: 4d8eb009d8ae4500940d77a64d914eed9a13b92c
https://github.com/llvm/llvm-project/commit/4d8eb009d8ae4500940d77a64d914eed9a13b92c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Remove SPF guard for trunc transforms (#117535)
This shouldn't be necessary anymore now that SPF patterns are
canonicalized to intrinsics.
Commit: 3de21477c49172081e502b47d608e729915f0914
https://github.com/llvm/llvm-project/commit/3de21477c49172081e502b47d608e729915f0914
Author: Viktoriia Bakalova <115406782+VitaNuo at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[clang][codegen] Mention the invariant that LLVM demangler should be … (#117346)
…able to handle mangled names generated by clang.
https://discourse.llvm.org/t/rfc-clang-diagnostic-for-demangling-failures/82835/8
Since we're putting the work on the above RFC on hold, let's leave a
comment in the source code pointing to prior efforts and the suggestion
of further steps.
Commit: f953b5eb72df77fc301aac210eab31c6270ff771
https://github.com/llvm/llvm-project/commit/f953b5eb72df77fc301aac210eab31c6270ff771
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
Log Message:
-----------
[SLP]Relax assertion about subvectors mask size
SubVectorsMask might be less than CommonMask, if the vectors with larger
number of elements are permuted or reused elements are used. Need to
consider this when estimation/building the vector to avoid compiler
crash
Fixes #117518
Commit: b872c4c9939999d8c588ca4e149e2b0b40773ebf
https://github.com/llvm/llvm-project/commit/b872c4c9939999d8c588ca4e149e2b0b40773ebf
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M flang/test/Driver/print-supported-cpus.f90
Log Message:
-----------
[flang][Driver] Fix incorrect condition in test
The conditions in a test did not match the target that was being
requested. This resulted in a test failure when building with
-DTARGETS_TO_BUILD=X86. This is now fixed.
Commit: c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
https://github.com/llvm/llvm-project/commit/c9e606b9cf50b822aca2a3dc5762fb77e9b976bd
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir] Improve doc in `OpFormatGen.cpp` (NFC) (#117564)
The comment is misleading because attributes do not have
`elidePrintingDefaultValue` bit. It appears that
`elidePrintingDefaultValue` was never merged upstream (see:
https://reviews.llvm.org/D135398 ), but the comment was likely
introduced by mistake in a later revision
(https://reviews.llvm.org/D135993.).
Commit: 99fd1c5536547ed4fc360b16e7fa2e06278707a8
https://github.com/llvm/llvm-project/commit/99fd1c5536547ed4fc360b16e7fa2e06278707a8
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libcxx/include/__chrono/duration.h
Log Message:
-----------
[libc++][NFC] Don't add legacy transitive includes in <__chrono/duration.h>
Commit: 20bd029a40faa2ae5383dd742b8a3595b1fe7c31
https://github.com/llvm/llvm-project/commit/20bd029a40faa2ae5383dd742b8a3595b1fe7c31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote fldexp with Zfh. (#117396)
The default expansion tries to create i16 operations after type
legalization.
Fixes #117349
Commit: 3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
https://github.com/llvm/llvm-project/commit/3db4f5b0daa33903e6522e2bf1b07c45edb5c8ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
Log Message:
-----------
AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)
The 2-pass XDL write VGPR, read by non-XDL SGEMM/DGEMM case
was 1 wait state overly conservative. Previously, for gfx940,
the XDL/non-XDL cases happened to have the same number of cycles
in all cases. Now the XDL consumer case has an additional state for
2 pass sources.
Commit: c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
https://github.com/llvm/llvm-project/commit/c3fe5ad6be9eb58d5043de9a5940ef3c397631b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
Log Message:
-----------
AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)
Confusingly, this is a different hazard to the one on gfx10
with a subtarget feature.
Commit: 27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
https://github.com/llvm/llvm-project/commit/27a8afa3fcf7e0378dff65cf3374f7a4e4e2b9a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
Log Message:
-----------
AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)
Commit: 8a2311c4bf9993230e37dc20b57973dc917f2338
https://github.com/llvm/llvm-project/commit/8a2311c4bf9993230e37dc20b57973dc917f2338
Author: Callum Fare <callum at codeplay.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
A offload/liboffload/API/APIDefs.td
A offload/liboffload/API/CMakeLists.txt
A offload/liboffload/API/Common.td
A offload/liboffload/API/Device.td
A offload/liboffload/API/OffloadAPI.td
A offload/liboffload/API/Platform.td
A offload/liboffload/API/README.md
A offload/liboffload/CMakeLists.txt
A offload/liboffload/README.md
A offload/liboffload/exports
A offload/liboffload/include/OffloadImpl.hpp
A offload/liboffload/include/generated/OffloadAPI.h
A offload/liboffload/include/generated/OffloadEntryPoints.inc
A offload/liboffload/include/generated/OffloadFuncs.inc
A offload/liboffload/include/generated/OffloadImplFuncDecls.inc
A offload/liboffload/include/generated/OffloadPrint.hpp
A offload/liboffload/src/Helpers.hpp
A offload/liboffload/src/OffloadImpl.cpp
A offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
A offload/test/tools/offload-tblgen/default_returns.td
A offload/test/tools/offload-tblgen/entry_points.td
A offload/test/tools/offload-tblgen/functions_basic.td
A offload/test/tools/offload-tblgen/functions_code_loc.td
A offload/test/tools/offload-tblgen/functions_ranged_param.td
A offload/test/tools/offload-tblgen/print_enum.td
A offload/test/tools/offload-tblgen/print_function.td
A offload/test/tools/offload-tblgen/type_tagged_enum.td
A offload/tools/offload-tblgen/APIGen.cpp
A offload/tools/offload-tblgen/CMakeLists.txt
A offload/tools/offload-tblgen/EntryPointGen.cpp
A offload/tools/offload-tblgen/FuncsGen.cpp
A offload/tools/offload-tblgen/GenCommon.hpp
A offload/tools/offload-tblgen/Generators.hpp
A offload/tools/offload-tblgen/PrintGen.cpp
A offload/tools/offload-tblgen/RecordTypes.hpp
A offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
A offload/unittests/OffloadAPI/CMakeLists.txt
A offload/unittests/OffloadAPI/common/Environment.cpp
A offload/unittests/OffloadAPI/common/Environment.hpp
A offload/unittests/OffloadAPI/common/Fixtures.hpp
A offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
A offload/unittests/OffloadAPI/device/olGetDevice.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
A offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
A offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
A offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
[Offload] Introduce offload-tblgen and initial new API implementation (#108413)
Introduce `offload-tblgen` and an initial implementation of a subset of
the new API. The tablegen files are intended to be the single source of
truth for the new API, with the header files, documentation, and others
bits of source all automatically generated.
**TODO** (based on review feedback so far):
- [x] Check in the generated headers
- [x] Add an `offload-generate` target to trigger the generation rather
than building them every time
- [x] Decide how error handling should work
- [x] Finish up new error handling implementation
- [x] Decide naming convention
- [x] Add testing for the new API
- [x] Add tablegen specific testing
- [x] clang-tidy and use llvm:: types when possible
- [x] Add optional code location arguments
- [x] Avoid multiple returns from one function
### offload-tblgen
See the included
[README](https://github.com/callumfare/llvm-project/blob/d80db06491d85444bb6f7e59d8068a22cef3a6b4/offload/new-api/API/README.md)
for more information on how the API definition and generation works. I'm
happy to answer any questions about it and plan to walk through it in a
future LLVM Offload call.
It should be noted that struct definitions have not been fully
implemented/tested as they aren't used by the initial API definitions,
but finishing that off in the future shouldn't be too much work.
The tablegen tooling has been designed to be easily extended with new
backends, using the classes in `RecordTypes.hpp` to abstract over the
tablegen records.
### New API
Previous discussions at the LLVM/Offload meeting have brought up the
need for a new API for exposing the functionality of the plugins. This
change introduces a very small subset of a new API, which is primarily
for testing the offload tooling and demonstrating how a new API can fit
into the existing code base without being too disruptive. Exact designs
for these entry points and future additions can be worked out over time.
The new API does however introduce the bare minimum functionality to
implement device discovery for Unified Runtime and SYCL. This means that
the `urinfo` and `sycl-ls` tools can be used on top of Offload. A
(rough) implementation of a Unified Runtime adapter (aka plugin) for
Offload is available
[here](https://github.com/callumfare/unified-runtime/tree/offload_adapter).
Our intention is to maintain this and use it to implement and test
Offload API changes with SYCL.
### Demoing the new API
```sh
$ git clone -b offload_adapter https://github.com/callumfare/unified-runtime.git
$ cd unified-runtime
$ mkdir build
$ cd build
$ cmake .. -GNinja -DUR_BUILD_ADAPTER_OFFLOAD=ON \
-DUR_OFFLOAD_INSTALL_DIR=<offload build dir containing liboffload_new.so> \
-DUR_OFFLOAD_INCLUDE_DIR=<offload build dir containing 'offload' headers directory>
$ ninja urinfo
export LD_LIBRARY_PATH=<offload build dir containing offload plugin libraries>
$ UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
[cuda:gpu][cuda:0] CUDA, NVIDIA GeForce GT 1030 [12030]
# Demo with tracing
$ OFFLOAD_TRACE=1 UR_ADAPTERS_FORCE_LOAD=$PWD/lib/libur_adapter_offload.so ./bin/urinfo
---> offloadPlatformGet(.NumEntries = 0, .phPlatforms = {}, .pNumPlatforms = 0x7ffd05e4d6e0 (2))-> OFFLOAD_RESULT_SUCCESS
---> offloadPlatformGet(.NumEntries = 2, .phPlatforms = {0x564bf4040220, 0x564bf4040240}, .pNumPlatforms = nullptr)-> OFFLOAD_RESULT_SUCCESS
...
```
### Open questions and future work
* The new API is implemented in a separate library
(`liboffload_new.so`). It could just as easily be part of the existing
`libomptarget` library - I have no strong feelings on which is better.
* Only some of the available device info is exposed, and not all the
possible device queries needed for SYCL are implemented by the plugins.
A sensible next step would be to refactor and extend the existing device
info queries in the plugins. The existing info queries are all strings,
but the new API introduces the ability to return any arbitrary type.
* It may be sensible at some point for the plugins to implement the new
API directly, and the higher level code on top of it could be made
generic, but this is more of a long-term possibility.
Commit: 9cc2502c048b1403ba8ba5cc5a655d867c329d12
https://github.com/llvm/llvm-project/commit/9cc2502c048b1403ba8ba5cc5a655d867c329d12
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/test/Driver/hexagon-toolchain-linux.c
Log Message:
-----------
[clang] hexagon: fix link order for libc/builtins (#117057)
When linking programs with `eld`, we get a link error like below:
Error:
/inst/clang+llvm-19.1.0-cross-hexagon-unknown-linux-musl/x86_64-linux-gnu/bin/../target/hexagon-unknown-linux-musl//usr/lib/libc.a(scalbn.lo)(.text.scalbn+0x3c):
undefined reference to `__hexagon_muldf3'
libc has references to the clang_rt builtins library, so the order of
the libraries should be reversed.
Commit: d88ed9357a0e4a49ce908c538ef21c1702c34638
https://github.com/llvm/llvm-project/commit/d88ed9357a0e4a49ce908c538ef21c1702c34638
Author: Raphael Moreira Zinsly <6718397+rzinsly at users.noreply.github.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
Log Message:
-----------
[NFC][RISCV] Refactor allocation of the stack space (#116625)
Separates the stack allocations from prologue in preparation for the
stack clash protection support.
Commit: e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
https://github.com/llvm/llvm-project/commit/e97fb2207e1ef6235a6268dbbd3cc08d437b07ef
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
Log Message:
-----------
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
This patch support for intrinsics in clang, as well as assembly
instructions in the backend.
Co-authored-by: Sirish Pande <Sirish.Pande at amd.com>
Commit: 6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
https://github.com/llvm/llvm-project/commit/6f8e7c11cf6157a9f93aa5842dd26fb51b37dce7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8ea78002c2637faf56ed5c0c88582fdd4f0ac701
https://github.com/llvm/llvm-project/commit/8ea78002c2637faf56ed5c0c88582fdd4f0ac701
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Add test case for RVV CSRs with cm.push.
The cfi_offset is incorrect for the RVV registers when cm.push
is used.
Commit: 7ad1084b521ea191245c47b4e63e4f97035e3786
https://github.com/llvm/llvm-project/commit/7ad1084b521ea191245c47b4e63e4f97035e3786
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (#117380)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 91af15b7648a10c3edcd9792b3f3487be399233b
https://github.com/llvm/llvm-project/commit/91af15b7648a10c3edcd9792b3f3487be399233b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (#117381)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[x] = Inst{11} = src0_modifier{2}
opsel[y] = Inst{12} = src1_modifier{2}
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 8997bf8e4636592ca0e4f31747adc02904d47b0c
https://github.com/llvm/llvm-project/commit/8997bf8e4636592ca0e4f31747adc02904d47b0c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (#117382)
OPSEL[3] selects low/high 16 bits of dest write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 70fef78329eb4da338ef8345b5059f9a57ff21a5
https://github.com/llvm/llvm-project/commit/70fef78329eb4da338ef8345b5059f9a57ff21a5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (#117383)
OPSEL[0] selects srcword to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 362d8fb2416ca3393b960eb158301d6f06dc5324
https://github.com/llvm/llvm-project/commit/362d8fb2416ca3393b960eb158301d6f06dc5324
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (#117384)
OPSEL ASM Syntax: opsel:[x,y,z]
where,
opsel[z] = Inst{14} = src0_modifier{3}
Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 00770489e4299fe6ab99b1772127d84dfe222ffc
https://github.com/llvm/llvm-project/commit/00770489e4299fe6ab99b1772127d84dfe222ffc
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Frontend/InitPreprocessor.cpp
A clang/test/C/C23/n2412.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
Log Message:
-----------
[C23] Fixed the value of BOOL_WIDTH (#117364)
The standard mandates that this returns the width of the type, which is
the number of bits in the value. For bool, that's required to be `1`
explicitly.
Fixes #117348
Commit: 0a140c4248b5eae5c044de4f394852ee7339a5e8
https://github.com/llvm/llvm-project/commit/0a140c4248b5eae5c044de4f394852ee7339a5e8
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
Log Message:
-----------
[AMDGPU] Adds pre-commit test for fmul-select combine (#111107)
This adds the f32/f64/f16/bf16 test cases for below pattern :
`fmul x, select(y, A, B)`
with just one use of select Inst above.
It acts as pre-commit tests for dagCombining above pattern into cheaper
ldexp in case of non-inlline 32 bit-constants. (#111109)
Commit: 29828b26fac3ee744c8f7dcb33cc082dc7c00a02
https://github.com/llvm/llvm-project/commit/29828b26fac3ee744c8f7dcb33cc082dc7c00a02
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
Log Message:
-----------
[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_offset for RVV CSRs. (#117408)
getCalleeSavedStackSize() already contains RVPushStackSize. Don't
subtract it again.
Commit: d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
https://github.com/llvm/llvm-project/commit/d7c20a6f0c1119814bc1580ae3c8e68b5a7e7bed
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
A libc/shared/rpc_opcodes.h
M libc/src/__support/RPC/rpc_client.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc][NFC] Move RPC opcodes to the 'shared/' directory as well
Commit: 1a86d44c80d2a0c603f67ed8bdcccaed830719a3
https://github.com/llvm/llvm-project/commit/1a86d44c80d2a0c603f67ed8bdcccaed830719a3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
M llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (#117417)
OPSEL ASM Syntax for v_cvt_scalef32_pk_f32_fp4 : opsel:[x,y,z]
where, x & y i.e. OPSEL[1 : 0] selects which src_byte to read.
OPSEL ASM Syntax for v_cvt_scalef32_pk_fp4_f32 : opsel:[a,b,c,d]
where, c & d i.e. OPSEL[3 : 2] selects which dst_byte to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap at amd.com>
Commit: 3cb28522ba4c2b80fbaf0840377aab4fce985110
https://github.com/llvm/llvm-project/commit/3cb28522ba4c2b80fbaf0840377aab4fce985110
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
M runtimes/CMakeLists.txt
Log Message:
-----------
Reapply "[runtimes] Allow building against an installed LLVM tree"
This relands #86209 which was reverted because ./bin/llvm no longer
accepted test paths in the source tree instead of the build tree. This was
happening because `add_subdirectory(${LLVM_MAIN_SRC_DIR}/utils/llvm-lit`
was called before all tsst suites were registered, and therefore it was
missing the source->build dir mappings.
Original commit message:
I am currently trying to test the LLVM runtimes (including compiler-rt)
against an installed LLVM tree rather than a build tree (since that is
no longer available). Currently, the runtimes build of compiler-rt assumes
that LLVM_BINARY_DIR is writable since it uses configure_file() to write
there during the CMake configure stage. Instead, generate this file inside
CMAKE_CURRENT_BINARY_DIR, which will match LLVM_BINARY_DIR when invoked
from llvm/runtimes/CMakeLists.txt.
I also needed to make a minor change to the hwasan tests: hwasan_symbolize
was previously found in the LLVM_BINARY_DIR, but since it is generated as
part of the compiler-rt build it is now inside the CMake build directory
instead. I fixed this by passing the output directory to lit as
config.compiler_rt_bindir and using llvm_config.add_tool_substitutions().
For testing that we no longer write to the LLVM install directory as
part of testing or configuration, I created a read-only bind mount and
configured the runtimes builds as follows:
```
$ sudo mount --bind --read-only ~/llvm-install /tmp/upstream-llvm-readonly
$ cmake -DCMAKE_BUILD_TYPE=Debug \
-DCMAKE_C_COMPILER=/tmp/upstream-llvm-readonly/bin/clang \
-DCMAKE_CXX_COMPILER=/tmp/upstream-llvm-readonly/bin/clang++ \
-DLLVM_INCLUDE_TESTS=TRUE -DLLVM_ENABLE_ASSERTIONS=TRUE \
-DCOMPILER_RT_INCLUDE_TESTS=TRUE -DCOMPILER_RT_DEBUG=OFF \
-DLLVM_ENABLE_RUNTIMES=compiler-rt \
-DCMAKE_DISABLE_FIND_PACKAGE_LLVM=TRUE \
-DCMAKE_DISABLE_FIND_PACKAGE_Clang=TRUE \
-G Ninja -S ~/upstream-llvm-project/runtimes \
-B ~/upstream-llvm-project/runtimes/cmake-build-debug-llvm-git
```
Pull Request: https://github.com/llvm/llvm-project/pull/114307
Commit: d047bee496e07748f0dd70f52c3b309c66fedab3
https://github.com/llvm/llvm-project/commit/d047bee496e07748f0dd70f52c3b309c66fedab3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/cmake/OpenMPTesting.cmake
R offload/liboffload/API/APIDefs.td
R offload/liboffload/API/CMakeLists.txt
R offload/liboffload/API/Common.td
R offload/liboffload/API/Device.td
R offload/liboffload/API/OffloadAPI.td
R offload/liboffload/API/Platform.td
R offload/liboffload/API/README.md
R offload/liboffload/CMakeLists.txt
R offload/liboffload/README.md
R offload/liboffload/exports
R offload/liboffload/include/OffloadImpl.hpp
R offload/liboffload/include/generated/OffloadAPI.h
R offload/liboffload/include/generated/OffloadEntryPoints.inc
R offload/liboffload/include/generated/OffloadFuncs.inc
R offload/liboffload/include/generated/OffloadImplFuncDecls.inc
R offload/liboffload/include/generated/OffloadPrint.hpp
R offload/liboffload/src/Helpers.hpp
R offload/liboffload/src/OffloadImpl.cpp
R offload/liboffload/src/OffloadLib.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/lit.cfg
M offload/test/lit.site.cfg.in
R offload/test/tools/offload-tblgen/default_returns.td
R offload/test/tools/offload-tblgen/entry_points.td
R offload/test/tools/offload-tblgen/functions_basic.td
R offload/test/tools/offload-tblgen/functions_code_loc.td
R offload/test/tools/offload-tblgen/functions_ranged_param.td
R offload/test/tools/offload-tblgen/print_enum.td
R offload/test/tools/offload-tblgen/print_function.td
R offload/test/tools/offload-tblgen/type_tagged_enum.td
R offload/tools/offload-tblgen/APIGen.cpp
R offload/tools/offload-tblgen/CMakeLists.txt
R offload/tools/offload-tblgen/EntryPointGen.cpp
R offload/tools/offload-tblgen/FuncsGen.cpp
R offload/tools/offload-tblgen/GenCommon.hpp
R offload/tools/offload-tblgen/Generators.hpp
R offload/tools/offload-tblgen/PrintGen.cpp
R offload/tools/offload-tblgen/RecordTypes.hpp
R offload/tools/offload-tblgen/offload-tblgen.cpp
M offload/unittests/CMakeLists.txt
R offload/unittests/OffloadAPI/CMakeLists.txt
R offload/unittests/OffloadAPI/common/Environment.cpp
R offload/unittests/OffloadAPI/common/Environment.hpp
R offload/unittests/OffloadAPI/common/Fixtures.hpp
R offload/unittests/OffloadAPI/device/olDeviceInfo.hpp
R offload/unittests/OffloadAPI/device/olGetDevice.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceCount.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfo.cpp
R offload/unittests/OffloadAPI/device/olGetDeviceInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatform.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformCount.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfo.cpp
R offload/unittests/OffloadAPI/platform/olGetPlatformInfoSize.cpp
R offload/unittests/OffloadAPI/platform/olPlatformInfo.hpp
Log Message:
-----------
Revert "[Offload] Introduce offload-tblgen and initial new API implementation (#108413)"
This reverts commit 8a2311c4bf9993230e37dc20b57973dc917f2338.
Commit: a5dd6463608bb09404e8a898ed337ef0b4a292c4
https://github.com/llvm/llvm-project/commit/a5dd6463608bb09404e8a898ed337ef0b4a292c4
Author: B I Mohammed Abbas <bimohammadabbas at gmail.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
Log Message:
-----------
Add extendhfxf2 into compiler rt (#113897)
Retry of pr #109090 and #111099.
Co-authored-by: Alexander Richardson <alexrichardson at google.com>
Commit: ed6749a4055c8b1500b39ebd4a8b981bf25250e8
https://github.com/llvm/llvm-project/commit/ed6749a4055c8b1500b39ebd4a8b981bf25250e8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
Log Message:
-----------
[RISCV] Promote frexp with Zfh.
The default expansion tries to create an illegal integer type after
legalization.
Commit: b0bc4674b761a71974e561184d055ac8159fd578
https://github.com/llvm/llvm-project/commit/b0bc4674b761a71974e561184d055ac8159fd578
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
Log Message:
-----------
[X86] Fix bad instregex in VPMOVSX/ZX znver4 512-bit patterns.
The Z size was optional, meaning it matched with the 128-bit SSE instructions as well.
Noticed while triaging the strange perf numbers on #110308
Commit: bb88fd171a6be892cec36969860a9034b48b8656
https://github.com/llvm/llvm-project/commit/bb88fd171a6be892cec36969860a9034b48b8656
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
A clang/test/CodeGenHLSL/resource-bindings.hlsl
M llvm/docs/DirectX/DXILResources.rst
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
Log Message:
-----------
[DirectX] Calculate resource binding offsets using the lower bound (#117303)
In the DXIL CreateHandle and CreateHandleFromBinding ops, resource
bindings are
indexed from the beginning of the binding space, not from the binding
itself.
Translate from an index into the binding to one from the beginning of
the space
when lowering to these operations.
Commit: fdf1f69c57ac3667d27c35e097040284edb1f574
https://github.com/llvm/llvm-project/commit/fdf1f69c57ac3667d27c35e097040284edb1f574
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
A llvm/test/CodeGen/Generic/cgdata-merge-local.ll
A llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
R llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
[CGData][GMF] Skip No Params (#116548)
This update follows up on change #112671 and is mostly a NFC, with the following exceptions:
- Introduced `-global-merging-skip-no-params` to bypass merging when no parameters are required.
- Parameter count is now calculated based on the unique hash count.
- Added `-global-merging-inst-overhead` to adjust the instruction overhead, reflecting the machine instruction size.
- Costs and benefits are now computed using the double data type. Since the finalization process occurs offline, this should not significantly impact build time.
- Moved a sorting operation outside of the loop.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: b0ca543532d13fde8907853f6c9909ad7e68cd9f
https://github.com/llvm/llvm-project/commit/b0ca543532d13fde8907853f6c9909ad7e68cd9f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/MemProfReader.cpp
Log Message:
-----------
[memprof] Remove dead code in MemProfReader (NFC) (#117607)
The only constructor in current use is the one that takes
IndexedMemProfData. Likewise, the only accessor in current use is
takeMemProfData.
Commit: fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
https://github.com/llvm/llvm-project/commit/fe3c23b439b9a2d00442d9bc6a4ca86f73066a3d
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
R llvm/test/CodeGen/Generic/cgdata-merge-local.ll
R llvm/test/CodeGen/Generic/cgdata-merge-no-params.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
Log Message:
-----------
Revert "[CGData][GMF] Skip No Params (#116548)"
This reverts commit fdf1f69c57ac3667d27c35e097040284edb1f574.
Commit: 3ba9081ade3d7e14aa4e51ca836e764139038bc3
https://github.com/llvm/llvm-project/commit/3ba9081ade3d7e14aa4e51ca836e764139038bc3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-25 (Mon, 25 Nov 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
A bolt/unittests/Core/MemoryMaps.cpp
M bolt/utils/bughunter.sh
M clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidConstOrRefDataMembersCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseInternalLinkageCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-internal-linkage.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/avoid-const-or-ref-data-members.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/use-internal-linkage-func.cpp
M clang/docs/ClangFormat.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SanitizerCoverage.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclFriend.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/ExprConcepts.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumCXXABI.cpp
M clang/lib/AST/ParentMapContext.cpp
M clang/lib/AST/TemplateName.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Frontend/InitPreprocessor.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/AST/ByteCode/c23.c
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/C/C23/n2412.c
M clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
A clang/test/CodeGenHLSL/resource-bindings.hlsl
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-read-tr.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/Driver/hexagon-toolchain-linux.c
M clang/test/OpenMP/flush_ast_print.cpp
M clang/test/OpenMP/flush_codegen.cpp
M clang/test/OpenMP/flush_messages.cpp
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/init.c
A clang/test/Sema/attr-target-version-unsupported.c
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-shlib/CMakeLists.txt
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/www/cxx_status.html
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/extendhfxf2.c
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_deadlock_detector.h
M compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
M compiler-rt/lib/tsan/rtl/tsan_rtl.h
M compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
A compiler-rt/test/builtins/Unit/extendhfxf2_test.c
M compiler-rt/test/hwasan/lit.cfg.py
M compiler-rt/test/lit.common.configured.in
A compiler-rt/test/tsan/many_held_mutex.cpp
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Runtime/CUDA/allocatable.h
A flang/include/flang/Runtime/CUDA/memmove-function.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/runtime/CUDA/CMakeLists.txt
M flang/runtime/CUDA/allocatable.cpp
A flang/runtime/CUDA/memmove-function.cpp
M flang/runtime/CUDA/memory.cpp
M flang/test/Driver/print-supported-cpus.f90
M flang/test/Fir/CUDA/cuda-allocate.fir
A flang/test/Fir/struct-return-aarch64.fir
A flang/test/Lower/OpenMP/Todo/flush-seq-cst.f90
M flang/test/Lower/OpenMP/Todo/map-mapper.f90
M flang/test/Parser/OpenMP/from-clause.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
M flang/test/Parser/OpenMP/target-update-to-clause.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/combined-constructs.f90
M flang/test/Semantics/OpenMP/defaultmap-clause-v45.f90
M flang/test/Semantics/OpenMP/flush02.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/map-clause.f90
M flang/test/Semantics/OpenMP/map-modifiers.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
R libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/shared/rpc.h
A libc/shared/rpc_opcodes.h
M libc/shared/rpc_util.h
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/block.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/src/__support/freetrie.h
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/__support/freelist_malloc_test.cpp
M libc/test/src/__support/freelist_test.cpp
M libc/test/src/__support/freestore_test.cpp
M libc/test/src/__support/freetrie_test.cpp
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M libc/utils/gpu/loader/nvptx/nvptx-loader.cpp
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/__chrono/duration.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__memory_resource/synchronized_pool_resource.h
M libcxx/include/future
M libcxx/include/memory_resource
M libcxx/include/syncstream
A libcxx/src/.clang-tidy
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/utils/ci/buildkite-pipeline.yml
M lld/COFF/Config.h
M lld/COFF/SymbolTable.cpp
M lld/Common/ErrorHandler.cpp
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/MipsArchTree.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Target.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
M lld/MachO/Config.h
M lld/MachO/Driver.cpp
M lld/MachO/LTO.cpp
M lld/MachO/Options.td
M lld/include/lld/Common/ErrorHandler.h
M lld/test/COFF/arm64ec.test
A lld/test/ELF/arm-rwpi-debug-relocs.s
M lld/test/ELF/incompatible.s
M lld/test/ELF/linkerscript/symbol-location.s
A lld/test/ELF/merge-addr.s
M lld/test/ELF/merge-reloc.s
R lld/test/ELF/merge-relocatable.s
R lld/test/ELF/merge-shared-str.s
R lld/test/ELF/merge-shared.s
R lld/test/ELF/merge-string.s
R lld/test/ELF/merge-to-non-alloc.s
M lld/test/ELF/reproduce.s
A lld/test/MachO/ltopasses-extension.ll
M lldb/docs/use/aarch64-linux.md
M lldb/include/lldb/Target/Process.h
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/Core/DynamicLoader.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
M llvm/Maintainers.md
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/DirectX/DXILResources.rst
M llvm/docs/LangRef.rst
M llvm/include/llvm/ADT/SmallVectorExtras.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/Bitcode/Writer/CMakeLists.txt
M llvm/lib/CodeGen/Analysis.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/Support/Compression.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SISchedule.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.td
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZOperands.td
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/lib/Target/X86/X86SchedBroadwell.td
M llvm/lib/Target/X86/X86SchedHaswell.td
M llvm/lib/Target/X86/X86SchedSandyBridge.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/RISCV/abs.ll
M llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/arm64-clrsb.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
M llvm/test/CodeGen/AArch64/arm64-vclz.ll
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
M llvm/test/CodeGen/AArch64/fcvt-fixed.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/mingw-refptr.ll
M llvm/test/CodeGen/AArch64/mulcmle.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-vector-splat.ll
M llvm/test/CodeGen/AArch64/overflow.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat.ll
M llvm/test/CodeGen/AArch64/usub_sat_plus.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
A llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
A llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx940.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/DirectX/CreateHandle.ll
M llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll
M llvm/test/CodeGen/Generic/machine-function-splitter.ll
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
A llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
A llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
R llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
A llvm/test/CodeGen/RISCV/rvv/rvv-cfi-info.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
A llvm/test/CodeGen/X86/tailcall-nofpclass.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v48.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/Xtensa/mul.ll
A llvm/test/Instrumentation/BoundsChecking/negative.ll
M llvm/test/MC/AMDGPU/ds.s
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/AMDGPU/gfx950_asm_read_tr.s
M llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx950_err.s
M llvm/test/MC/AMDGPU/invalid-instructions-spellcheck.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/mimg-err.s
M llvm/test/MC/AMDGPU/mimg.s
M llvm/test/MC/AMDGPU/regression/bug28165.s
M llvm/test/MC/AMDGPU/regression/bug28413.s
M llvm/test/MC/AMDGPU/smrd.s
M llvm/test/MC/AMDGPU/sopk.s
A llvm/test/MC/AMDGPU/unknown-target-cpu.s
M llvm/test/MC/AMDGPU/vintrp.s
M llvm/test/MC/AMDGPU/vop1.s
M llvm/test/MC/AMDGPU/vop2.s
M llvm/test/MC/AMDGPU/vop3-convert.s
M llvm/test/MC/AMDGPU/vop3-errs.s
M llvm/test/MC/AMDGPU/vop3.s
M llvm/test/MC/AMDGPU/vop_dpp.s
M llvm/test/MC/AMDGPU/vop_sdwa.s
M llvm/test/MC/AMDGPU/vopc.s
M llvm/test/MC/AMDGPU/wave_any.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_ds_read_tr.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
A llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
A llvm/test/ThinLTO/X86/Inputs/memprof-old-alloc-context-summary.bc
A llvm/test/ThinLTO/X86/memprof-old-alloc-context-summary.ll
A llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll
A llvm/test/Transforms/Inline/LoongArch/lit.local.cfg
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wavefrontsize.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
M llvm/test/Transforms/InstCombine/fptrunc.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/branch-weights.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
A llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-subvectors-insert.ll
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-adx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x87.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
M llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/Haswell/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/independent-load-stores.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-adx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-aes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bitalgvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512bwvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cd.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512cdvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512dqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512gfnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512ifmavl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vaesvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vnnivl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpclmulqdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vpopcntdqvl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxgfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-bmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clflushopt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-clwb.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmov.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-cmpxchg.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-f16c.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-fma.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-gfni.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lea.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-lzcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-mmx.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-movbe.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-pclmul.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-popcnt.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-prefetchw.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdrand.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-rdseed.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse1.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-sse42.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vaes.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-vpclmulqdq.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_32.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x87.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-xsave.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/zero-idioms.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-sse41.s
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/SmallVectorExtrasTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/gn/secondary/bolt/unittests/Core/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
M mlir/docs/PatternRewriter.md
M mlir/include/mlir-c/Pass.h
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h
A mlir/include/mlir/Conversion/ConvertToLLVM/ToLLVMInterface.td
A mlir/include/mlir/Conversion/GPUCommon/GPUToLLVM.h
A mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVM.h
M mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/include/mlir/IR/AttrTypeBase.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinDialectBytecode.td
M mlir/include/mlir/IR/BuiltinLocationAttributes.td
M mlir/include/mlir/IR/Location.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/include/mlir/Interfaces/TilingInterface.td
M mlir/lib/AsmParser/LocationParser.cpp
M mlir/lib/AsmParser/Parser.h
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/lib/CAPI/IR/Pass.cpp
M mlir/lib/Conversion/ConvertToLLVM/CMakeLists.txt
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/ConvertToLLVM/ToLLVMInterface.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Func/Transforms/FuncConversions.cpp
M mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/BuiltinDialectBytecode.cpp
M mlir/lib/IR/Location.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/requirements.txt
A mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-target-attr.mlir
A mlir/test/Conversion/MemRefToLLVM/type-conversion.mlir
M mlir/test/Dialect/Affine/affine-data-copy.mlir
M mlir/test/Dialect/Affine/affine-loop-invariant-code-motion.mlir
M mlir/test/Dialect/Affine/loop-fusion-4.mlir
M mlir/test/Dialect/GPU/barrier-elimination.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/IR/locations.mlir
M mlir/test/IR/properties.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/Transforms/test-legalizer.mlir
A mlir/test/get_darwin_real_python.py
M mlir/test/lib/Dialect/LLVM/CMakeLists.txt
A mlir/test/lib/Dialect/LLVM/TestPatterns.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lit.cfg.py
M mlir/test/python/pass_manager.py
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M offload/DeviceRTL/src/Mapping.cpp
M offload/plugins-nextgen/common/CMakeLists.txt
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/test/offloading/ompx_bare_ballot_sync.c
M offload/test/offloading/ompx_bare_shfl_down_sync.cpp
M runtimes/CMakeLists.txt
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
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