[all-commits] [llvm/llvm-project] dc3dba: [Intrinsics][AArch64] Add intrinsic to mask off al...

[Sam Tebbs via All-commits]

  Branch: refs/heads/users/SamTebbs33/alias-intrinsic
  Home:   https://github.com/llvm/llvm-project
  Commit: dc3dba57e8cd76191ba03270d512f9931d4f4600
      https://github.com/llvm/llvm-project/commit/dc3dba57e8cd76191ba03270d512f9931d4f4600
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-20 (Wed, 20 Nov 2024)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/alias_mask.ll
    A llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
    R llvm/test/CodeGen/AArch64/whilewr.ll

  Log Message:
  -----------
  [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes

It can be unsafe to load a vector from an address and write a vector to
an address if those two addresses have overlapping lanes within a
vectorised loop iteration.

This PR adds an intrinsic designed to create a mask with lanes disabled
if they overlap between the two pointer arguments, so that only safe
lanes are loaded, operated on and stored.

Along with the two pointer parameters, the intrinsic also takes an
immediate that represents the size in bytes of the vector element
types, as well as an immediate i1 that is true if there is a write
after-read-hazard or false if there is a read-after-write hazard.

This will be used by #100579 and replaces the existing lowering for
whilewr since that isn't needed now we have the intrinsic.


  Commit: e984b6120792f90ef00cd9ac23fde16adee73a5a
      https://github.com/llvm/llvm-project/commit/e984b6120792f90ef00cd9ac23fde16adee73a5a
  Author: Samuel Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M llvm/docs/LangRef.rst

  Log Message:
  -----------
  Fix intrinsic signature in docs


  Commit: 2ea522b993b1f835e519ed51ac6f167556fc3772
      https://github.com/llvm/llvm-project/commit/2ea522b993b1f835e519ed51ac6f167556fc3772
  Author: Samuel Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/test/CodeGen/AArch64/alias_mask.ll
    M llvm/test/CodeGen/AArch64/alias_mask_scalable.ll

  Log Message:
  -----------
  Add -o - to test run lines


  Commit: 4c4ab8aeed1b4fd66a90334dfcd889481f7e35b6
      https://github.com/llvm/llvm-project/commit/4c4ab8aeed1b4fd66a90334dfcd889481f7e35b6
  Author: Samuel Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h

  Log Message:
  -----------
  Format


Compare: https://github.com/llvm/llvm-project/compare/d3e07beaf383...4c4ab8aeed1b

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