[all-commits] [llvm/llvm-project] 9ebf02: Add intrinsic to mask off aliasing vector lanes

[Sam Tebbs via All-commits]

  Branch: refs/heads/users/SamTebbs33/alias-intrinsic
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ebf022a2fbdd38e5b2d15d11e92f31671c5896f
      https://github.com/llvm/llvm-project/commit/9ebf022a2fbdd38e5b2d15d11e92f31671c5896f
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/IR/Intrinsics.td

  Log Message:
  -----------
  Add intrinsic to mask off aliasing vector lanes

It can be unsafe to load a vector from an address and write a vector to
an address if those two addresses have overlapping lanes within a
vectorised loop iteration.

This PR adds an intrinsic designed to create a mask with lanes disabled
if they overlap between the two pointer arguments, so that only safe
lanes are loaded, operated on and stored.

Along with the two pointer parameters, the intrinsic also takes an
immediate i32 that represents the size in bytes of the vector element
types, as well as an immediate i1 that is true if there is a write
after-read-hazard or false if there is a read-after-write hazard.

This will be used by #100579 which will also implement default lowering
in SelectionDAG.


  Commit: 9bfb63a46e75433034b74d4615cebb138b9aa1fb
      https://github.com/llvm/llvm-project/commit/9bfb63a46e75433034b74d4615cebb138b9aa1fb
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  Log Message:
  -----------
  Lower in selectiondag


  Commit: d3e07beaf383f9cbe93232d56020db1c4e77e6b2
      https://github.com/llvm/llvm-project/commit/d3e07beaf383f9cbe93232d56020db1c4e77e6b2
  Author: Sam Tebbs <samuel.tebbs at arm.com>
  Date:   2024-11-18 (Mon, 18 Nov 2024)

  Changed paths:
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  wip


Compare: https://github.com/llvm/llvm-project/compare/9ebf022a2fbd%5E...d3e07beaf383

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