[all-commits] [llvm/llvm-project] 7317a6: [RISCV][MachineVerifier] Use RegUnit for register ...

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7317a6e99026f65a343e2e69685445dc5bd83172
      https://github.com/llvm/llvm-project/commit/7317a6e99026f65a343e2e69685445dc5bd83172
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2024-11-25 (Mon, 25 Nov 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    A llvm/test/MachineVerifier/RISCV/subreg-liveness.mir

  Log Message:
  -----------
  [RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)

For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.

This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.



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