[all-commits] [llvm/llvm-project] 3fb0be: [RISCV][GISel] Add register class to some isel out...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
      https://github.com/llvm/llvm-project/commit/3fb0bea859efaf401ad0ce420d7b75e3ff1c4746
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-24 (Sun, 24 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll

  Log Message:
  -----------
  [RISCV][GISel] Add register class to some isel output patterns so they can be imported.

This makes (fcopysign X, (fneg Y)) patterns work.



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