[all-commits] [llvm/llvm-project] 0a6d79: [X86] Improve F16C CVT schedules on SNB/HSW/BDW

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a6d797c20f6ab53bc09fb66129f603ed6e4b524
      https://github.com/llvm/llvm-project/commit/0a6d797c20f6ab53bc09fb66129f603ed6e4b524
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-24 (Sun, 24 Nov 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
    M llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
    M llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
    M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s

  Log Message:
  -----------
  [X86] Improve F16C CVT schedules on SNB/HSW/BDW

Add complete IvyBridge schedule (which is included in the SandyBridge model, IvyBridge was the first to support F16C) - split rr/rm schedules as they usually have very different port usage.

Haswell/Broadwell use Port1 not Port0.

Confirmed with a mixture of Agner + uops.info comparisons.



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