[all-commits] [llvm/llvm-project] 028d41: [Hexagon] Add Hexagon Load Widening Pass (#116330)

[Yashas Andaluri via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 028d41d7cf16ffaba1493d850a382a6d3eb814cf
      https://github.com/llvm/llvm-project/commit/028d41d7cf16ffaba1493d850a382a6d3eb814cf
  Author: Yashas Andaluri <quic_yandalur at quicinc.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/lib/Target/Hexagon/CMakeLists.txt
    A llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
    R llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
    M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
    A llvm/test/CodeGen/Hexagon/load-widen.ll
    M llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll
    A llvm/test/CodeGen/Hexagon/widen-alias.ll
    A llvm/test/CodeGen/Hexagon/widen-not-load.ll
    A llvm/test/CodeGen/Hexagon/widen-volatile.ll

  Log Message:
  -----------
  [Hexagon] Add Hexagon Load Widening Pass (#116330)

Extend existing store widening pass to widen load instructions.

This patch also borrows the alias check algorithm from AMDGPU's load
store widening pass.

Widened load instruction is inserted before the first candidate load
instruction.
Widened store instruction is inserted after the last candidate store
instruction.
This method helps avoid moving uses/defs when replacing load/store
instructions with their widened equivalents.

The pass has also been extended to
* Generate 64-bit widened stores
* Handle 32-bit post increment load/store
* Handle stores of non-immediate values
* Handle stores where the offset is a GlobalValue



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