[all-commits] [llvm/llvm-project] f84fc4: [RISCV][GISel] Make s16->s32 G_ANYEXT/SEXT/ZEXT le...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Fri Nov 22 11:44:36 PST 2024
Branch: refs/heads/users/vitalybuka/spr/revert-aarch64-define-high-bits-of-fpr-and-gpr-registers-take-2-114827
Home: https://github.com/llvm/llvm-project
Commit: f84fc44f1a46969817bfd1b38991f7e43a8efe1d
https://github.com/llvm/llvm-project/commit/f84fc44f1a46969817bfd1b38991f7e43a8efe1d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-21 (Thu, 21 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir
Log Message:
-----------
[RISCV][GISel] Make s16->s32 G_ANYEXT/SEXT/ZEXT legal.
Commit: 3761b675196f2c5ac31bf5fe027f6bb2907ff2a9
https://github.com/llvm/llvm-project/commit/3761b675196f2c5ac31bf5fe027f6bb2907ff2a9
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Dialect conversion: Remove "finalize" phase (#117097)
This is a re-upload of #116934, which was reverted.
The dialect conversion driver has three phases:
- **Create** `IRRewrite` objects as the IR is traversed.
- **Finalize** `IRRewrite` objects. During this phase, source
materializations for mismatching value types are created. (E.g., when
`Value` is replaced with a `Value` of different type, but there is a
user of the original value that was not modified because it is already
legal.)
- **Commit** `IRRewrite` objects. During this phase, all remaining IR
modifications are materialized. In particular, SSA values are actually
being replaced during this phase.
This commit removes the "finalize" phase. This simplifies the code base
a bit and avoids one traversal over the `IRRewrite` stack. Source
materializations are now built during the "commit" phase, right before
an SSA value is being replaced.
This commit also removes the "inverse mapping" of the conversion value
mapping, which was used to predict if an SSA value will be dead at the
end of the conversion. This check is replaced with an approximate check
that does not require an inverse mapping. (A false positive for `v` can
occur if another value `v2` is mapped to `v` and `v2` turns out to be
dead at the end of the conversion. This case is not expected to happen
very often.) This reduces the complexity of the driver a bit and removes
one potential source of bugs. (There have been bugs in the usage of the
inverse mapping in the past.)
`BlockTypeConversionRewrite` no longer stores a pointer to the type
converter. This pointer is now stored in `ReplaceBlockArgRewrite`.
This commit is in preparation of merging the 1:1 and 1:N dialect
conversion driver. It simplifies the upcoming changes around the
conversion value mapping. (API surface of the conversion value mapping
is reduced.)
Commit: 1490f38b2253a10fcb186a18dd2875cbbeb89fd1
https://github.com/llvm/llvm-project/commit/1490f38b2253a10fcb186a18dd2875cbbeb89fd1
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-21 (Thu, 21 Nov 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Avoid make<ArmCmseSGVeneer>
Store them as unique_ptr in sgVeneers instead.
Commit: d71fa331df49450361a9e5cd4e48ae4a79b6126b
https://github.com/llvm/llvm-project/commit/d71fa331df49450361a9e5cd4e48ae4a79b6126b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/SymbolContext.cpp
A lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
Log Message:
-----------
[lldb] Fix inline function resolution for discontinuous functions (#116777)
The problem here is the assumption that the entire function will be
placed in a single section. This will ~never be the case for a
discontinuous function, as the point of splitting the function is to let
the linker group parts of the function according to their "hotness".
The fix is to change the offset computation to use file addresses
instead.
Commit: 994c544c18c86cbdb6536aae5d27ef7e2f592486
https://github.com/llvm/llvm-project/commit/994c544c18c86cbdb6536aae5d27ef7e2f592486
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
Log Message:
-----------
doc: Clarify that ffile-prefix-map applies to fcoverage-prefix-map, too [NFC] (#117135)
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: 925e1956cd5039fa2489b802d25555e247c34175
https://github.com/llvm/llvm-project/commit/925e1956cd5039fa2489b802d25555e247c34175
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseExpr.cpp
M clang/test/AST/ast-dump-recovery.cpp
Log Message:
-----------
[Clang] enhance error recovery with RecoveryExpr for trailing commas in call arguments (#114684)
Fixes #100921
Commit: a9882bda96228ca23e166a817f93a7dbc99763cb
https://github.com/llvm/llvm-project/commit/a9882bda96228ca23e166a817f93a7dbc99763cb
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M libcxx/test/std/utilities/charconv/charconv.msvc/test.pass.cpp
Log Message:
-----------
[libc++] Mark charconv test as unsupported under msan (#116933)
Commit: 5518bb215b51cc339c3ecac064032f6791ae6476
https://github.com/llvm/llvm-project/commit/5518bb215b51cc339c3ecac064032f6791ae6476
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Check getFunctionTypeLoc() for validity in InlayHintVisitor (#117296)
Fixes https://github.com/clangd/clangd/issues/2223
Commit: eac8ea323a2a478dcf53f994c7b0369bfb10747c
https://github.com/llvm/llvm-project/commit/eac8ea323a2a478dcf53f994c7b0369bfb10747c
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
[SystemZ] Modify tests for constrained rounding functions (#116952)
The existing tests for constrained functions often use constant
arguments. If constant evaluation is enhanced, such tests will not check
code generation of the tested functions. To avoid it, the tests are
modified to use loaded value instead of constants. Now only the tests
for rounding functions are changed.
Commit: 562c93a165e5bb85b0cf464bbb157b33a668af83
https://github.com/llvm/llvm-project/commit/562c93a165e5bb85b0cf464bbb157b33a668af83
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/include/mlir/Query/QuerySession.h
Log Message:
-----------
[mlir] IWYU mlir/include/mlir/Query/QuerySession.h
Commit: 92301180f7e2d240c560f621f6fc1b07217cac01
https://github.com/llvm/llvm-project/commit/92301180f7e2d240c560f621f6fc1b07217cac01
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/SplitFunctions.cpp
A bolt/test/X86/exceptions-compact.s
Log Message:
-----------
[BOLT] Use compact EH format for fixed-address executables (#117274)
Use ULEB128 format for emitting LSDAs for fixed-address executables,
similar to what we use for PIEs/DSOs. Main difference is that we don't
use landing pad trampolines when landing pads are not contained in a
single fragment. Instead, we fallback to emitting larger fixed-address
LSDAs, which is still better than adding trampoline instructions.
Commit: 2cc5b493cb5c7df4d7f3acfb493725b2bb7082f5
https://github.com/llvm/llvm-project/commit/2cc5b493cb5c7df4d7f3acfb493725b2bb7082f5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Add fhahn as ConstraintElimination maintainer (#117006)
Commit: 157d847ba737b4136aeb1d92912f549ea1c96d4c
https://github.com/llvm/llvm-project/commit/157d847ba737b4136aeb1d92912f549ea1c96d4c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Use getSignedConstant() where necessary (#117177)
This is to prevent assertion failures when we disable implicit
truncation in getConstant().
getCanonicalConstSplat() works with a mix of unsigned and signed values,
so I explicitly truncate the APInt there.
Commit: 632c5d29919ce93dc5f33fd729a0b97adc7c831b
https://github.com/llvm/llvm-project/commit/632c5d29919ce93dc5f33fd729a0b97adc7c831b
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
Log Message:
-----------
[VPlan] Support VPReverseVectorPointer in DataWithEVL vectorization (#113667)
VPReverseVectorPointer relies on the runtime VF, but in DataWithEVL
tail-folding, EVL (which can be less than VF at runtime) should be used
instead.
This patch updates the logic to check the users of VF and replaces the
second operand if the user is VPReverseVectorPointer.
Commit: 05fcdd555eaac74717cd132ca434c90ae99381dd
https://github.com/llvm/llvm-project/commit/05fcdd555eaac74717cd132ca434c90ae99381dd
Author: Victor Perez <victor.perez at codeplay.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
Log Message:
-----------
[MLIR][SPIRV-TO-LLVM] Support SPV_INTEL_split_barrier ops (#116648)
Add conversion to LLVM for `SPV_INTEL_split_barrier` operations via
conversion to SPIR-V built-ins.
Signed-off-by: Victor Perez <victor.perez at codeplay.com>
Commit: 1d4602070f96c9a6921d51a3b907f90cd2e3ae32
https://github.com/llvm/llvm-project/commit/1d4602070f96c9a6921d51a3b907f90cd2e3ae32
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mld-seq-sa.c
M clang/test/Preprocessor/init-loongarch.c
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
Log Message:
-----------
[LoongArch] Support LA V1.1 feature ld-seq-sa that don't generate dbar 0x700. (#116762)
Two options for clang
-mld-seq-sa: Do not generate load-load barrier instructions (dbar 0x700)
-mno-ld-seq-sa: Generate load-load barrier instructions (dbar 0x700)
The default is -mno-ld-seq-sa
Commit: ef206446f2bbcb1bacc73d7611a96c457f59499f
https://github.com/llvm/llvm-project/commit/ef206446f2bbcb1bacc73d7611a96c457f59499f
Author: Youngsuk Kim <joseph942010 at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/integer-overflow.cpp
Log Message:
-----------
[clang] Warn const integer-overflow of member in temporary struct bound to rvalue reference (#117225)
Fixes #46755
---------
Co-authored-by: Sirraide <aeternalmail at gmail.com>
Commit: 294c5cb2bea88fa048e00757188749f074c5b09f
https://github.com/llvm/llvm-project/commit/294c5cb2bea88fa048e00757188749f074c5b09f
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/test/CodeGen/amdgpu-barrier-type-debug-info.c
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Type.h
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/target-type-properties.ll
Log Message:
-----------
[IR] Add TargetExtType::CanBeLocal property (#99016)
Add a property to allow marking target extension types that cannot be
used in an alloca instruction or byval argument, similar to CanBeGlobal
for global variables.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: cc721dba4e94c1d28214f81da0f1af79b6ca4218
https://github.com/llvm/llvm-project/commit/cc721dba4e94c1d28214f81da0f1af79b6ca4218
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
Log Message:
-----------
[AArch64][Codegen] Improve small shufflevector/concat lowering for SME (#116662)
This now tries to widen the shuffle before generating a possibly
expensive SVE TBL, this may allow the shuffle to be matched as something
cheaper like a ZIP1.
Commit: fdb1bf9b5949b2a97041922405a812a060fce5f4
https://github.com/llvm/llvm-project/commit/fdb1bf9b5949b2a97041922405a812a060fce5f4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
Log Message:
-----------
[LoongArch] Use getSignedConstant() where necessary (#117172)
To prevent assertion failures when we disable implicit truncation in
getConstant().
Commit: 063a6f70a6e86deb81fe6b1f24fecb7774d8cb44
https://github.com/llvm/llvm-project/commit/063a6f70a6e86deb81fe6b1f24fecb7774d8cb44
Author: Martin Storsjö <martin at martin.st>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lld/MinGW/Options.td
Log Message:
-----------
[LLD] [MinGW] Get rid of trailing whitespace. NFC.
Commit: 55e9afab6e5fc2fd2d456567657cfdf08920bb65
https://github.com/llvm/llvm-project/commit/55e9afab6e5fc2fd2d456567657cfdf08920bb65
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC. Remove the useless check for alternate instruction. (#117293)
Only BinaryOperator and CastInst support alternate instruction. It
always returns false for TreeEntry::isAltShuffle if an instruction is
ExtractElementInst, ExtractValueInst, LoadInst, StoreInst or
InsertElementInst.
Commit: 68aa6ac58c2bd59cac15417e7d8356ef8382dabd
https://github.com/llvm/llvm-project/commit/68aa6ac58c2bd59cac15417e7d8356ef8382dabd
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC. Remove redundant computation in getReorderingData. (#117295)
Commit: cac13606c20ee6e78b04dd3b36af2c0ee61ab9ef
https://github.com/llvm/llvm-project/commit/cac13606c20ee6e78b04dd3b36af2c0ee61ab9ef
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/EdgeBundles.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/EdgeBundles.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SpillPlacement.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
Log Message:
-----------
[CodeGen][NewPM] Port EdgeBundles analysis to NPM (#116616)
Commit: dde9477d8c0b85d445f10b08b0120f3d361cb77f
https://github.com/llvm/llvm-project/commit/dde9477d8c0b85d445f10b08b0120f3d361cb77f
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/SparseSet.h
M llvm/unittests/ADT/SparseSetTest.cpp
Log Message:
-----------
[NFC] Use unique_ptr in SparseSet (#116617)
This allows implementing the move constructor.
Commit: 775148f2367600f90d28684549865ee9ea2f11be
https://github.com/llvm/llvm-project/commit/775148f2367600f90d28684549865ee9ea2f11be
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/test/TableGen/riscv-target-def.td
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Log Message:
-----------
[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)
We can get these information via `sys_riscv_hwprobe`.
This can be used to implement `__builtin_cpu_is`.
Commit: c11b6b1b8af7454b35eef342162dc2cddf54b4de
https://github.com/llvm/llvm-project/commit/c11b6b1b8af7454b35eef342162dc2cddf54b4de
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
A clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
A clang/test/CodeGen/RISCV/builtin-cpu-is.c
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/RISCVTargetParser.cpp
Log Message:
-----------
[RISCV] Support __builtin_cpu_is
We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.
We can support `__builtin_cpu_is` via comparing values in compiler's
CPU definitions and `__riscv_cpu_model`.
This depends on #116202.
Reviewers: lenary, BeMg, kito-cheng, preames, lukel97
Reviewed By: lenary
Pull Request: https://github.com/llvm/llvm-project/pull/116231
Commit: 3c621b1e2069d7853ebd849b0dd796bea5f732bf
https://github.com/llvm/llvm-project/commit/3c621b1e2069d7853ebd849b0dd796bea5f732bf
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
Log Message:
-----------
[MSP430] Use getSignedTargetConstant()
The displacement is signed.
Commit: b36fcf4f493ad9d30455e178076d91be99f3a7d8
https://github.com/llvm/llvm-project/commit/b36fcf4f493ad9d30455e178076d91be99f3a7d8
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/RISCVTargetParser.cpp
Log Message:
-----------
[RISCV] Rename variable CPUModel to Model
The variable name can't be the same as the struct name or we will
have "error: declaration of ‘llvm::RISCV::CPUModel llvm::RISCV::CPUInfo::CPUModel’
changes meaning of ‘CPUModel’ [-fpermissive]".
Commit: 11ee21671f7d4b02222763eebfcb221c9598605e
https://github.com/llvm/llvm-project/commit/11ee21671f7d4b02222763eebfcb221c9598605e
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
R lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
Log Message:
-----------
Revert " [lldb][dwarf] Compute fully qualified names on simplified template names with DWARFTypePrinter (#117071)"
This reverts commit f06c187799d910fd3ac3e9106397e5eecff9f265.
Temporary revert: there is https://github.com/llvm/llvm-project/pull/117239 that is suppose to fix the issue.
Reverting to keep things rolling.
Commit: a9731dff0a0133f718e8e4fb6c729aa1d7c909a4
https://github.com/llvm/llvm-project/commit/a9731dff0a0133f718e8e4fb6c729aa1d7c909a4
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Avoid a getSource() call (#117311)
This is only needed when we actually emit a diagnostic, so move the
getSource() after the early return.
Commit: d1dae1e8612a2fa69d0d731e16d07baf8ce10c85
https://github.com/llvm/llvm-project/commit/d1dae1e8612a2fa69d0d731e16d07baf8ce10c85
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
R clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
R clang/test/CodeGen/RISCV/builtin-cpu-is.c
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/test/TableGen/riscv-target-def.td
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Log Message:
-----------
Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain
This reverts commit b36fcf4f493ad9d30455e178076d91be99f3a7d8.
This reverts commit c11b6b1b8af7454b35eef342162dc2cddf54b4de.
This reverts commit 775148f2367600f90d28684549865ee9ea2f11be.
multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076
Commit: f84903486cd174e39fb36fa88c98c9563b671c7e
https://github.com/llvm/llvm-project/commit/f84903486cd174e39fb36fa88c98c9563b671c7e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Sema/amdgcn-address-spaces.c
Log Message:
-----------
[AMDGPU] Do not allow the region address space to be converted to generic (#117171)
Summary:
Previous changes relaxed the address space rules based on what the
target says about them. This accidentally included the AS(2) region as
convertible to generic. Simply check for AS(2) and reject it.
Commit: 676a1e6643c7f8db22607fb98984965d51518b40
https://github.com/llvm/llvm-project/commit/676a1e6643c7f8db22607fb98984965d51518b40
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
[AMDGPU] Remove uses of deprecreated HSA executable functions (#117241)
Summary:
These functions were deprecated in ROCR 1.3 which was released quite
some time ago. The main functionality that was lost was modifying and
inspecting the code object indepedently of the executable, however we do
all of that custom through our ELF API. This should be within the
versions of other functions we use.
Commit: 86b69c31642e98f8357df62c09d118ad1da4e16a
https://github.com/llvm/llvm-project/commit/86b69c31642e98f8357df62c09d118ad1da4e16a
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
Log Message:
-----------
[SPIR-V] Fix SPIR-V extension SPV_INTEL_function_pointers: introduce CodeSectionINTEL (#117250)
This PR fixes generation of OpConstantFunctionPointerINTEL instruction
for the SPIR-V extension SPV_INTEL_function_pointers. Result type of
OpConstantFunctionPointerINTEL must be OpTypePointer with Storage Class
operand equal to CodeSectionINTEL.
See also https://github.com/llvm/llvm-project/pull/116636
CC: @MrSidims
Commit: 5405f54b014666fb8fe9c981a71593e3861cb3d7
https://github.com/llvm/llvm-project/commit/5405f54b014666fb8fe9c981a71593e3861cb3d7
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/Lanai/LanaiInstrInfo.td
Log Message:
-----------
[Lanai] Use getSignedTargetConstant() for signed immediate
Commit: 2e07c2b1bf2bde62eaefe85494a8d2740f4b5ae8
https://github.com/llvm/llvm-project/commit/2e07c2b1bf2bde62eaefe85494a8d2740f4b5ae8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AVR/AVRISelLowering.cpp
Log Message:
-----------
[AVR] Use getSignedConstant() for negative number
Commit: 8b4909111228e30ca3abdf3e40b04b9de9690714
https://github.com/llvm/llvm-project/commit/8b4909111228e30ca3abdf3e40b04b9de9690714
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstr64Bit.td
Log Message:
-----------
[Sparc] Use getSignedConstant() where necessary
This avoids assertion failures once we disable implicit
truncation in getConstant().
Commit: 88959324710a5a24687162642d4faf7e056743c5
https://github.com/llvm/llvm-project/commit/88959324710a5a24687162642d4faf7e056743c5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Avoid implicit truncation in getConstant()
Either use getSignedConstant() or change variable type to unsigned
to avoid unnecessary sign extension in the first place.
Commit: 22fdc57140283d053207ea5763dc03ec7770a8ff
https://github.com/llvm/llvm-project/commit/22fdc57140283d053207ea5763dc03ec7770a8ff
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonIntrinsics.td
M llvm/lib/Target/Hexagon/HexagonPatterns.td
Log Message:
-----------
[Hexagon] Avoid implicit truncation in getConstant()
Use getSignedConstant() or change variable type as appropriate.
This will avoid assertion failures when implicit truncation is
disabled.
Commit: 556ea5265a254aabfd8d520a3b841785e99f4328
https://github.com/llvm/llvm-project/commit/556ea5265a254aabfd8d520a3b841785e99f4328
Author: Raghu Maddhipatla <7686592+raghavendhra at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/nested-target.f90
Log Message:
-----------
[Flang] [Semantics] [OpenMP] Added missing semantic check with nested target region. (#115344)
Issue semantic warning for any combination of nested OMP TARGET
directives inside another OMP TARGET region.
This change would not affect OMP TARGET inside an OMP TARGET DATA.
However, it issues warning for OMP TARGET DATA inside an OMP TARGET
region.
Commit: ecaf2c335cd612646086ec53315cb1018a5b9d91
https://github.com/llvm/llvm-project/commit/ecaf2c335cd612646086ec53315cb1018a5b9d91
Author: Petr Kurapov <petr.a.kurapov at intel.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/test/Conversion/GPUCommon/transfer_write.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/ops.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[MLIR] Move warp_execute_on_lane_0 from vector to gpu (#116994)
Please see the related RFC here:
https://discourse.llvm.org/t/rfc-move-execute-on-lane-0-from-vector-to-gpu-dialect/82989.
This patch does exactly one thing - moves the op to gpu.
Commit: 4389220549285fc9ef1e96f762eafa5f79a5d1ee
https://github.com/llvm/llvm-project/commit/4389220549285fc9ef1e96f762eafa5f79a5d1ee
Author: smanna12 <soumi.manna at intel.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[Clang] Prevent potential null pointer dereferences (#117176)
This commit addresses several null pointer issues identified by static
analysis by replacing dyn_cast<> with cast<> and getAs<> with castAs<>
in various parts of the Clang codebase. The cast and castAs method is
used to ensure that the type is correctly cast, which helps prevent
potential null pointer dereferences.
Changes:
1. ASTContext.cpp:
Replaced dyn_cast with cast to ensure that the type is correctly cast to
AttributedType.
2. SemaFunctionEffects.cpp:
Replaced getAs with castAs to ensure that the type is correctly cast to
FunctionProtoType.
3. SemaHLSL.cpp:
Replaced getAs with castAs to ensure that the type is correctly cast to
VectorType.
Commit: c7d5ef420d66bf321999a5c922dd6e77f8dc2e9d
https://github.com/llvm/llvm-project/commit/c7d5ef420d66bf321999a5c922dd6e77f8dc2e9d
Author: vannem-sj <vannem at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
R libcxx/test/std/time/time.cal/time.cal.weekday/time.cal.weekday.members/operator[].pass.cpp
A libcxx/test/std/time/time.cal/time.cal.weekday/time.cal.weekday.members/subscript_operator.pass.cpp
Log Message:
-----------
[libc++] Rename operator[].pass.cpp to subscript_operator.pass.cpp (#117216)
This filename includes non FAT32 legal characters, and has caused a few
issues with glob tools that don't escape brackets properly.
Commit: 14bdcefbd88f35e31064241b52bccfabfb027499
https://github.com/llvm/llvm-project/commit/14bdcefbd88f35e31064241b52bccfabfb027499
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP]Model reduction_add(ext(<n x i1>)) as ext(ctpop(bitcast <n x i1> to int n))
Currently sequences reduction_add(ext(<n x i1>)) are modeled as vector
extensions + reduction add, but later instcombiner transforms it into
ext(ctcpop(bitcast <n x i1> to int n)). Patch adds direct support for
this in SLP vectorizer, which enables better cost estimation.
AVX512, -O3+LTO
CINT2006/445.gobmk - extra vector code
Prolangs-C/bison - extra vector code
Benchmarks/NPB-serial/is - 16 x + 8 x reductions vectorized as 24
x reduction
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/116875
Commit: 4da960b898f404d91109b50d423c3db400b4e9a8
https://github.com/llvm/llvm-project/commit/4da960b898f404d91109b50d423c3db400b4e9a8
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/test/TableGen/riscv-target-def.td
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Log Message:
-----------
[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)
We can get these information via `sys_riscv_hwprobe`.
This can be used to implement `__builtin_cpu_is`.
Commit: 875b10f7d0888ca7e53f527f4c30531bd6b50bfb
https://github.com/llvm/llvm-project/commit/875b10f7d0888ca7e53f527f4c30531bd6b50bfb
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
A clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
A clang/test/CodeGen/RISCV/builtin-cpu-is.c
M clang/test/Preprocessor/has_builtin_cpuid.c
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/TargetParser/RISCVTargetParser.cpp
Log Message:
-----------
[RISCV] Support __builtin_cpu_is
We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.
We can support `__builtin_cpu_is` via comparing values in compiler's
CPU definitions and `__riscv_cpu_model`.
This depends on #116202.
Reviewers: lenary, BeMg, kito-cheng, preames, lukel97
Reviewed By: lenary
Pull Request: https://github.com/llvm/llvm-project/pull/116231
Commit: 912c502a9e4bab8e07de4419f8cbae35c98b112f
https://github.com/llvm/llvm-project/commit/912c502a9e4bab8e07de4419f8cbae35c98b112f
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
Log Message:
-----------
[clang] Infer lifetime_capture_by for STL containers (#117122)
This is behind `-Wdangling-capture` warning which is disabled by default.
Commit: b8eef18868570b2f5244d6d43de02a1812d1c880
https://github.com/llvm/llvm-project/commit/b8eef18868570b2f5244d6d43de02a1812d1c880
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port ecaf2c335cd612646086ec53315cb1018a5b9d91
Commit: 720a4c70edd0a9815f0e830d8ad4e1c322e404ae
https://github.com/llvm/llvm-project/commit/720a4c70edd0a9815f0e830d8ad4e1c322e404ae
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
Log Message:
-----------
[lldb] Fix DW_OP_piece-O3 test on AArch64 Windows (#117336)
Making a breakpoint on a line causes an error on aarch64-pc-windows.
This patch changes the test so that a breakpoint can be made on a
function name.
#117168
Commit: 20cb4ec845dec70f304c054ba5b45c0a388112b8
https://github.com/llvm/llvm-project/commit/20cb4ec845dec70f304c054ba5b45c0a388112b8
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/utils/analyzer/exploded-graph-rewriter.py
Log Message:
-----------
[analyzer] Print the PostInitializer target in exploded-graph-rewriter (#116034)
This aids debugging PostInitializer program points by knowing what is
the location being initialized.
Commit: c4aa83840b72b9eb94e6bc2088326fb27c43ada6
https://github.com/llvm/llvm-project/commit/c4aa83840b72b9eb94e6bc2088326fb27c43ada6
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
Improve slightly the pre-commit git hook usage of the auto-format helper (#117326)
The default mode does not provide a way to see the actual failure of the
formatters without modifying the code. Instead offer the user the option
to rerun with a `FORMAT_HOOK_VERBOSE=1` environment variable to print
the actual formatting diff.
Commit: 7fcc0f9065727c2c3151f7103c9d2803e507c7b7
https://github.com/llvm/llvm-project/commit/7fcc0f9065727c2c3151f7103c9d2803e507c7b7
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/test/Target/LLVMIR/gpu.mlir
Log Message:
-----------
Populate the llvm::GlobalVariable ELF section, with the attribute from the ObjectAttrs (#117246)
Commit: 7ce00148f86db3fee41cdf4e224e0af069dd1a00
https://github.com/llvm/llvm-project/commit/7ce00148f86db3fee41cdf4e224e0af069dd1a00
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] remove duplicated test line in VOP2 test (#117195)
This is a NFC change. Remove duplicated test line in gfx11/gfx12 vop2
test file with the latest update_mc_test_script.py --unique option
This is also preparing for the up-coming true16 change
Commit: 026af9e972469c878e51f1215659b7264da0136d
https://github.com/llvm/llvm-project/commit/026af9e972469c878e51f1215659b7264da0136d
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] remove duplicated test line in VOP3 test (#117193)
This is a NFC change. Remove duplicated test line in gfx11/gfx12 vop3
test file with the latest `update_mc_test_script.py --unique` option
This is also preparing for the up-coming true16 change
Commit: 1fd8d3fea53e6e4573cdce55bd38ef0a7813a442
https://github.com/llvm/llvm-project/commit/1fd8d3fea53e6e4573cdce55bd38ef0a7813a442
Author: Chuvak <demenev2002 at yandex.ru>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp
Log Message:
-----------
[mlir] Fix wrong names in LinalgOps and ScalableValueBoundsConstraintSet (#117227)
Fix for some mistakes in source code found using PVS Studio.
Inspired by: https://pvs-studio.com/en/blog/posts/cpp/1188/
Fixed:
- [Bug 2](https://pvs-studio.com/en/blog/posts/cpp/1188/#ID725051E718)
- [Bug 3](https://pvs-studio.com/en/blog/posts/cpp/1188/#IDFA2459368E)
Commit: 9ea2a4aabe0902ee176f449825139e32642f4dd9
https://github.com/llvm/llvm-project/commit/9ea2a4aabe0902ee176f449825139e32642f4dd9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] IsNOT - cleanup comments for each match. NFC.
Preparation for a refactor of IsNOT to better handle oneuse cases - move comments next to each match.
Commit: 4cc278587f3f44df08c6bebc0b4887f8522143f1
https://github.com/llvm/llvm-project/commit/4cc278587f3f44df08c6bebc0b4887f8522143f1
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
Log Message:
-----------
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
Update VOPC profile with VOP3 pseudo:
1. On GFX11+, v_cmp_class_f16 has src1 type f16 for literals, however
it's semantically interpreted as an integer. Update VOPC class f16
profile from operand type f16, i16 to f16, f16, currently updating it
for fake16 format, and will update t16 format in the following patch.
2. 16bit V_CMP_CLASS instructions (V_CMP_**_U/I/F16) are named with
`t16`, but actually using 32 bit registers. Correct it by updating the
pseudo definitions with useRealTrue16/useFakeTrue16 predicates and
rename these `t16` instructions to `fake16`.
3. Update the inst select so that `t16`/`fake16` instructions are
selected in true16/fake16 flow.
4. The mir test file are impacted for a name change of these impacted 16
bit V_CMP instructions, but non-functional change to emitted code
Commit: 39913ae095dc9fd25465e70297ce900c300c80a5
https://github.com/llvm/llvm-project/commit/39913ae095dc9fd25465e70297ce900c300c80a5
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP][REVEC] Make reorderTopToBottom support ShuffleVectorInst. (#117310)
We don't want reorderTopToBottom to reorder ShuffleVectorInst (because
ShuffleVectorInst currently supports only a limited set of patterns).
Either we make ShuffleVectorInst support more patterns, or we let
ReorderIndices reorder the result of the vectorization of
ShuffleVectorInst. We choose the latter solution.
Commit: 61f1dc05a88de38afcb337ef194cfdb7dc798197
https://github.com/llvm/llvm-project/commit/61f1dc05a88de38afcb337ef194cfdb7dc798197
Author: tlemy <138604946+tlemy at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/CXX/class.access/class.friend/p11.cpp
M clang/test/SemaCXX/function-redecl.cpp
Log Message:
-----------
Added more descriptive message (issue 116808) (#117201)
The dialogue messages were changed to be more descriptive.
Fixes #116808
Commit: 9c9e030fba868b3d3bf2ce84ff3c7078686b99e2
https://github.com/llvm/llvm-project/commit/9c9e030fba868b3d3bf2ce84ff3c7078686b99e2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP][NFC]Add a test with the RISCV ctpop-based reduction
Commit: b71038a69ee95f5dd740f99a1cb7aefde0859562
https://github.com/llvm/llvm-project/commit/b71038a69ee95f5dd740f99a1cb7aefde0859562
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
Log Message:
-----------
[AIX] Fix AIX BuildBot failure as AIX linker doesn't support version script. (#117342)
AIX BuildBot failed due to
https://github.com/llvm/llvm-project/pull/116556 as AIX linker does not
support version script.
This PR is to fix the failure
This PR is on behalf of gnikolov at ca.ibm.com
Commit: 05b3d26181ade32f5988d2be4939f605a5225782
https://github.com/llvm/llvm-project/commit/05b3d26181ade32f5988d2be4939f605a5225782
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-11-23 (Sat, 23 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Basic/Targets/RISCV.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[clang][RISCV] Bump RVV intrinsic to version 1.0 (#116597)
The spec:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4
Also remove __riscv_v_intrinsic_overloading since it's no longer in
spec, the overloading intrinsics should be also enabled when RVV
intrinsics are defined.
Commit: 285754d79960e2416d43127703922cbf8647e284
https://github.com/llvm/llvm-project/commit/285754d79960e2416d43127703922cbf8647e284
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Fix closing brace indentation in validateOperandClass
Commit: 29f11f0a3240dff1e10ed3d4a5412ecb8c762327
https://github.com/llvm/llvm-project/commit/29f11f0a3240dff1e10ed3d4a5412ecb8c762327
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
M llvm/utils/TableGen/X86ManualInstrMapping.def
Log Message:
-----------
[X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)
More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equivalent instructions
Commit: ee0ca4e81f1fdd86d5eddc3290175fe8cb28b97f
https://github.com/llvm/llvm-project/commit/ee0ca4e81f1fdd86d5eddc3290175fe8cb28b97f
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/is_typed_resource_element_compatible_concept.hlsl
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
M clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
R clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
Log Message:
-----------
[HLSL] Add implicit resource element type concepts to AST (#116413)
This PR is step one on the journey to implement resource element type
validation via C++20 concepts. The PR sets up the infrastructure for
injecting implicit concept decls / concept specialization expressions
into the AST, which will then be evaluated after template arguments are
instantiated. This is not meant to be a complete implementation of the
desired validation for HLSL,
there are a couple of missing elements:
We need the __builtin_hlsl_is_typed_resource_element_compatible builtin
to be implemented.
We need other constraints, like is_intangible
We need to put the first 2 points together, and construct a finalized
constraint expression, which should differ between typed and raw buffers
This is just an initial PR that puts some of the core infrastructure in
place.
This PR is an edit of #112600, so that new tests that were put into main
don't fail
Fixes #75676
Commit: dc637e940cb115fe72408ba96ad2e5e2396a3e94
https://github.com/llvm/llvm-project/commit/dc637e940cb115fe72408ba96ad2e5e2396a3e94
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
Log Message:
-----------
Revert "[lldb] Fix DW_OP_piece-O3 test on AArch64 Windows" (#117354)
Reverts llvm/llvm-project#117336
Commit: 4be09f06242be9349f05016fb50d3dbb378600bf
https://github.com/llvm/llvm-project/commit/4be09f06242be9349f05016fb50d3dbb378600bf
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
Log Message:
-----------
[lldb][test] DW_OP_piece-O3.c: Disable on Windows (#117355)
#117168
Commit: 689c53219280151b6421d633d993ed886827849b
https://github.com/llvm/llvm-project/commit/689c53219280151b6421d633d993ed886827849b
Author: Artem Belevich <tra at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
A clang/test/Driver/cuda-no-threadsafe-statics.cu
Log Message:
-----------
[CUDA] pass -fno-threadsafe-statics to GPU sub-compilations. (#117074)
We do not have support for the threadsafe statics on the GPU side.
However, we do sometimes end up with empty local static initializers,
and those happen to trigger calls to `__cxa_guard*`, which breaks
compilation.
Partially addresses https://github.com/llvm/llvm-project/issues/117023
Commit: a5f501e347f66d66818fba5aa7dbc25a07299ca5
https://github.com/llvm/llvm-project/commit/a5f501e347f66d66818fba5aa7dbc25a07299ca5
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/asdouble.hlsl
A clang/test/SemaHLSL/BuiltIns/asdouble-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
A llvm/test/CodeGen/DirectX/asdouble.ll
Log Message:
-----------
[HLSL][DXIL] Implement `asdouble` intrinsic (#114847)
- define intrinsic as builtin in Builtins.td
- link intrinsic in hlsl_intrinsics.h
- add semantic analysis to SemaHLSL.cpp
- lower to `llvm` or a `dx` intrinsic when applicable in CGBuiltin.cpp
- define DXIL intrinsic in IntrinsicsDirectX.td
- add DXIL op and mapping in DXIL.td
- enable scalarization of intrinsic
- add basic sema checking to asdouble-errors.hlsl
Resolves #99081
Commit: f170f5fa80f244ccac51e9867de3ad823512a2d4
https://github.com/llvm/llvm-project/commit/f170f5fa80f244ccac51e9867de3ad823512a2d4
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M lldb/bindings/interface/SBThreadExtensions.i
M lldb/test/API/lang/c/stepping/TestStepAndBreakpoints.py
Log Message:
-----------
[lldb] Add stop_reason_data property to SBThread python extensions (#117266)
Add a pythonic `stop_reason_data` property to `SBThread`. The property
produces a list of ints.
Commit: a04b0d587a8d260063fe1d50f6fecdc585d75ff4
https://github.com/llvm/llvm-project/commit/a04b0d587a8d260063fe1d50f6fecdc585d75ff4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/Module.h
M llvm/lib/IR/Module.cpp
M llvm/unittests/IR/ModuleTest.cpp
Log Message:
-----------
Implement Move-assignment for llvm::Module (NFC) (#117270)
Move-assignment is quite convenient in various situation, and
work-around having it available is very convoluted.
Commit: 5ac81a1d158e5b0577c33656235d90865d4682fb
https://github.com/llvm/llvm-project/commit/5ac81a1d158e5b0577c33656235d90865d4682fb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
Log Message:
-----------
[X86] Add test coverage for #79799
Commit: c87336fc46b32dfb62ebbb259a7a4ec3d354a283
https://github.com/llvm/llvm-project/commit/c87336fc46b32dfb62ebbb259a7a4ec3d354a283
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M mlir/unittests/IR/AffineMapTest.cpp
Log Message:
-----------
[mlir][test] Add unittests for `getInversePermutation` (#116945)
The only way to test `getInversePermutation` is through unit tests. The
concept of "inverse permutations" is tricky to document and these tests
are a good source documentation of the expected/intended behavoiur.
Hence these additional unit tests.
This is a follow-on of #114775 in which I added tests for
`isProjectedPermutation`.
Commit: 71f14ffba6ec8a6606911279781576e521c2b7dd
https://github.com/llvm/llvm-project/commit/71f14ffba6ec8a6606911279781576e521c2b7dd
Author: Artem Belevich <tra at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc.hip
Log Message:
-----------
[HIP] Fix tests broken by #117074 / 689c532 (#117361)
Commit: 7530e707afc60014624eb62bda9557cdc7f28dd0
https://github.com/llvm/llvm-project/commit/7530e707afc60014624eb62bda9557cdc7f28dd0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/test/MC/Disassembler/X86/x86-64.txt
Log Message:
-----------
[X86] Ignore REX prefixes not immediately before opcode (#117299)
The Intel X86 Architecture Manual says the following:
> A REX prefix is ignored, as are its individual bits, when it is not
needed
> for an instruction or when it does not immediately precede the opcode
byte or
> the escape opcode byte (0FH) of an instruction for which it is needed.
This
> has the implication that only one REX prefix, properly located, can
affect an
> instruction.
We currently do not handle these cases in the disassembler, leading to
incorrect disassembly. This patch rectifies the situation by treating
REX prefixes as standard prefixes rather than only expecting them before
the Opcode.
The motivating test case added as a test was fuzzer generated.
Commit: 23d7a6cedb5198535086a67586487f19effbd411
https://github.com/llvm/llvm-project/commit/23d7a6cedb5198535086a67586487f19effbd411
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/FrontendOptions.h
M flang/lib/Frontend/CompilerInvocation.cpp
A flang/test/Driver/print-supported-cpus.f90
M flang/tools/flang-driver/fc1_main.cpp
Log Message:
-----------
[flang][Driver] Support -print-supported-cpus and associated aliases (#117199)
The aliases are -mcpu=help and -mtune=help. There is still an issue with
the output which prints an example line that references clang. That is
not fixed here because it is printed in llvm/MC/SubtargetInfo.cpp. Some
more thought is needed to determine how best to handle this.
Fixes #117010
Commit: 1683f84d289348ba6879635c4161979204f75230
https://github.com/llvm/llvm-project/commit/1683f84d289348ba6879635c4161979204f75230
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/test/CodeGen/AArch64/init-undef.mir
Log Message:
-----------
Revert "[InitUndef] handleSubReg should skip artificial subregs. (#116248)" (#117365)
Maybe not needed but to avoid conflicts with #117307
Without revert of this one, but reverting #117307, the
regenerated init-undef.mir became empty.
This reverts commit be15fd5085680cc5ed9ec4f4f2258b504cdd55db.
Commit: ad9dcd96dc895f57a3747fe68ef455e0bf43c805
https://github.com/llvm/llvm-project/commit/ad9dcd96dc895f57a3747fe68ef455e0bf43c805
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/test/CodeGen/ARM/fcmp-xo.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
A llvm/test/CodeGen/ARM/fpscr-multi-use.ll
M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
M llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/select.ll
M llvm/test/CodeGen/Thumb2/mve-fmas.ll
M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
Log Message:
-----------
Reland "[ARM] Stop gluing FP comparisons to FMSTAT" (#117248)
Following #116547, this changes the result of `ARMISD::CMPFP*` and the
operand of `ARMISD::FMSTAT` from a special `Glue` type to a normal type.
This change allows comparisons to be CSEd and scheduled around as can be
seen in the test changes.
Note that `ARMISD::FMSTAT` is still glued to its consumer nodes; this is
going to be changed in a separate patch.
This patch also sets `CopyCost` of `cl_FPSCR_NZCV` register class to a
negative value. The reason is the same as for CCR register class: it
makes DAG scheduler and InstrEmitter try to avoid copies of `FPCSR_NZCV`
register to / from virtual registers. Previously, this was not
necessary, since no attempt was made to create copies in the first
place.
`TRI::getCrossCopyRegClass` is modified in a way that prevents DAG
scheduler from copying FPSCR into a virtual register. The register
allocator might need to spill the virtual register, but that only seem
to work in Thumb mode.
Commit: 14a58a1390a72ba6c66606e58e86425dcb902763
https://github.com/llvm/llvm-project/commit/14a58a1390a72ba6c66606e58e86425dcb902763
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
R llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
Log Message:
-----------
Revert "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)" (#117367)
To pass tests with #117307 revert.
This reverts commit 3093b29b597b9a936a3e4d1c8bc4a7ccba8fc848.
Commit: 1ed5ef60466bb9f2cea4ea04f453eb9c498eb7bd
https://github.com/llvm/llvm-project/commit/1ed5ef60466bb9f2cea4ea04f453eb9c498eb7bd
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-22 (Fri, 22 Nov 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/SplitFunctions.cpp
A bolt/test/X86/exceptions-compact.s
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/is_typed_resource_element_compatible_concept.hlsl
M clang/test/AST/ast-dump-recovery.cpp
M clang/test/AST/attr-lifetime-capture-by.cpp
M clang/test/CXX/class.access/class.friend/p11.cpp
A clang/test/CodeGen/RISCV/builtin-cpu-is-error.c
A clang/test/CodeGen/RISCV/builtin-cpu-is.c
M clang/test/CodeGen/amdgpu-barrier-type-debug-info.c
A clang/test/CodeGenHLSL/builtins/asdouble.hlsl
A clang/test/Driver/cuda-no-threadsafe-statics.cu
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/loongarch-march.c
A clang/test/Driver/loongarch-mld-seq-sa.c
M clang/test/Preprocessor/has_builtin_cpuid.c
M clang/test/Preprocessor/init-loongarch.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/amdgcn-address-spaces.c
M clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
M clang/test/SemaCXX/function-redecl.cpp
M clang/test/SemaCXX/integer-overflow.cpp
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
A clang/test/SemaHLSL/BuiltIns/asdouble-errors.hlsl
M clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
R clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
M clang/tools/clang-shlib/CMakeLists.txt
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/analyzer/exploded-graph-rewriter.py
M flang/include/flang/Frontend/FrontendOptions.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Driver/print-supported-cpus.f90
M flang/test/Semantics/OpenMP/nested-target.f90
M flang/tools/flang-driver/fc1_main.cpp
M libc/utils/gpu/loader/amdgpu/amdhsa-loader.cpp
R libcxx/test/std/time/time.cal/time.cal.weekday/time.cal.weekday.members/operator[].pass.cpp
A libcxx/test/std/time/time.cal/time.cal.weekday/time.cal.weekday.members/subscript_operator.pass.cpp
M libcxx/test/std/utilities/charconv/charconv.msvc/test.pass.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/SyntheticSections.h
M lld/MinGW/Options.td
M lldb/bindings/interface/SBThreadExtensions.i
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
M lldb/source/Symbol/Block.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/test/API/lang/c/stepping/TestStepAndBreakpoints.py
M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
A lldb/test/Shell/SymbolFile/DWARF/x86/discontinuous-inline-function.s
R lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M llvm/Maintainers.md
M llvm/include/llvm/ADT/SparseSet.h
M llvm/include/llvm/CodeGen/EdgeBundles.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.def
M llvm/include/llvm/TargetParser/LoongArchTargetParser.h
M llvm/include/llvm/TargetParser/RISCVTargetParser.h
M llvm/lib/CodeGen/EdgeBundles.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SpillPlacement.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonIntrinsics.td
M llvm/lib/Target/Hexagon/HexagonPatterns.td
M llvm/lib/Target/Lanai/LanaiInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArch.td
M llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstr64Bit.td
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/LoongArchTargetParser.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Assembler/target-type-properties.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/ARM/fcmp-xo.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
A llvm/test/CodeGen/ARM/fpscr-multi-use.ll
M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
M llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/select.ll
A llvm/test/CodeGen/DirectX/asdouble.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
M llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-fmas.ll
M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
M llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
M llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
M llvm/test/MC/Disassembler/X86/x86-64.txt
M llvm/test/TableGen/riscv-target-def.td
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
M llvm/unittests/ADT/SparseSetTest.cpp
M llvm/unittests/IR/ModuleTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
M llvm/utils/TableGen/X86ManualInstrMapping.def
M llvm/utils/git/code-format-helper.py
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorDistribution.h
M mlir/include/mlir/Query/QuerySession.h
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/GPUCommon/transfer_write.mlir
M mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/ops.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
M mlir/test/Target/LLVMIR/gpu.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/unittests/IR/AffineMapTest.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/8de3fb6298a3...1ed5ef60466b
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