[all-commits] [llvm/llvm-project] b71038: [AIX] Fix AIX BuildBot failure as AIX linker doesn...

Alexey Bataev via All-commits all-commits at lists.llvm.org
Fri Nov 22 11:00:58 PST 2024 

  Branch: refs/heads/users/alexey-bataev/spr/slpuse-getextendedreduction-cost-and-fix-reduction-cost-calculations
  Home:   https://github.com/llvm/llvm-project
  Commit: b71038a69ee95f5dd740f99a1cb7aefde0859562
      https://github.com/llvm/llvm-project/commit/b71038a69ee95f5dd740f99a1cb7aefde0859562
  Author: Daniel Chen <cdchen at ca.ibm.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M clang/tools/clang-shlib/CMakeLists.txt

  Log Message:
  -----------
  [AIX] Fix AIX BuildBot failure as AIX linker doesn't support version script. (#117342)

AIX BuildBot failed due to
https://github.com/llvm/llvm-project/pull/116556 as AIX linker does not
support version script.
This PR is to fix the failure

This PR is on behalf of gnikolov at ca.ibm.com


  Commit: 05b3d26181ade32f5988d2be4939f605a5225782
      https://github.com/llvm/llvm-project/commit/05b3d26181ade32f5988d2be4939f605a5225782
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-11-23 (Sat, 23 Nov 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/Preprocessor/riscv-target-features.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [clang][RISCV] Bump RVV intrinsic to version 1.0 (#116597)

The spec:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4
Also remove __riscv_v_intrinsic_overloading since it's no longer in
spec, the overloading intrinsics should be also enabled when RVV
intrinsics are defined.


  Commit: 285754d79960e2416d43127703922cbf8647e284
      https://github.com/llvm/llvm-project/commit/285754d79960e2416d43127703922cbf8647e284
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  [TableGen] Fix closing brace indentation in validateOperandClass


  Commit: 29f11f0a3240dff1e10ed3d4a5412ecb8c762327
      https://github.com/llvm/llvm-project/commit/29f11f0a3240dff1e10ed3d4a5412ecb8c762327
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86CompressEVEX.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86SchedSapphireRapids.td
    M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
    M llvm/test/TableGen/x86-fold-tables.inc
    M llvm/test/TableGen/x86-instr-mapping.inc
    M llvm/utils/TableGen/X86ManualInstrMapping.def

  Log Message:
  -----------
  [X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)

More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equivalent instructions


  Commit: ee0ca4e81f1fdd86d5eddc3290175fe8cb28b97f
      https://github.com/llvm/llvm-project/commit/ee0ca4e81f1fdd86d5eddc3290175fe8cb28b97f
  Author: Joshua Batista <jbatista at microsoft.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M clang/lib/Sema/HLSLExternalSemaSource.cpp
    M clang/lib/Sema/SemaExprCXX.cpp
    M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/RWBuffer-AST.hlsl
    M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
    A clang/test/AST/HLSL/is_typed_resource_element_compatible_concept.hlsl
    M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
    M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
    M clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
    R clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl

  Log Message:
  -----------
  [HLSL] Add implicit resource element type concepts to AST  (#116413)

This PR is step one on the journey to implement resource element type
validation via C++20 concepts. The PR sets up the infrastructure for
injecting implicit concept decls / concept specialization expressions
into the AST, which will then be evaluated after template arguments are
instantiated. This is not meant to be a complete implementation of the
desired validation for HLSL,
there are a couple of missing elements:

We need the __builtin_hlsl_is_typed_resource_element_compatible builtin
to be implemented.
We need other constraints, like is_intangible
We need to put the first 2 points together, and construct a finalized
constraint expression, which should differ between typed and raw buffers
This is just an initial PR that puts some of the core infrastructure in
place.

This PR is an edit of #112600, so that new tests that were put into main
don't fail
Fixes #75676


  Commit: dc637e940cb115fe72408ba96ad2e5e2396a3e94
      https://github.com/llvm/llvm-project/commit/dc637e940cb115fe72408ba96ad2e5e2396a3e94
  Author: Ilia Kuklin <ikuklin at accesssoftek.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c

  Log Message:
  -----------
  Revert "[lldb] Fix DW_OP_piece-O3 test on AArch64 Windows" (#117354)

Reverts llvm/llvm-project#117336


  Commit: 4be09f06242be9349f05016fb50d3dbb378600bf
      https://github.com/llvm/llvm-project/commit/4be09f06242be9349f05016fb50d3dbb378600bf
  Author: Ilia Kuklin <ikuklin at accesssoftek.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c

  Log Message:
  -----------
  [lldb][test] DW_OP_piece-O3.c: Disable on Windows (#117355)

#117168


  Commit: 689c53219280151b6421d633d993ed886827849b
      https://github.com/llvm/llvm-project/commit/689c53219280151b6421d633d993ed886827849b
  Author: Artem Belevich <tra at google.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M clang/lib/Driver/ToolChains/Cuda.cpp
    M clang/lib/Driver/ToolChains/HIPAMD.cpp
    A clang/test/Driver/cuda-no-threadsafe-statics.cu

  Log Message:
  -----------
  [CUDA] pass -fno-threadsafe-statics to GPU sub-compilations. (#117074)

We do not have support for the threadsafe statics on the GPU side.

However, we do sometimes end up with empty local static initializers,
and those happen to trigger calls to `__cxa_guard*`, which breaks
compilation.

Partially addresses https://github.com/llvm/llvm-project/issues/117023


  Commit: a5f501e347f66d66818fba5aa7dbc25a07299ca5
      https://github.com/llvm/llvm-project/commit/a5f501e347f66d66818fba5aa7dbc25a07299ca5
  Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M clang/include/clang/Basic/Builtins.td
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/hlsl/hlsl_intrinsics.h
    M clang/lib/Sema/SemaHLSL.cpp
    A clang/test/CodeGenHLSL/builtins/asdouble.hlsl
    A clang/test/SemaHLSL/BuiltIns/asdouble-errors.hlsl
    M llvm/include/llvm/IR/IntrinsicsDirectX.td
    M llvm/lib/Target/DirectX/DXIL.td
    M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
    A llvm/test/CodeGen/DirectX/asdouble.ll

  Log Message:
  -----------
  [HLSL][DXIL] Implement `asdouble` intrinsic (#114847)

- define intrinsic as builtin in Builtins.td
- link intrinsic in hlsl_intrinsics.h
- add semantic analysis to SemaHLSL.cpp
- lower to `llvm` or a `dx` intrinsic when applicable in CGBuiltin.cpp
- define DXIL intrinsic in IntrinsicsDirectX.td
- add DXIL op and mapping in DXIL.td
- enable scalarization of intrinsic

- add basic sema checking to asdouble-errors.hlsl
    
 Resolves #99081


  Commit: f170f5fa80f244ccac51e9867de3ad823512a2d4
      https://github.com/llvm/llvm-project/commit/f170f5fa80f244ccac51e9867de3ad823512a2d4
  Author: Dave Lee <davelee.com at gmail.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M lldb/bindings/interface/SBThreadExtensions.i
    M lldb/test/API/lang/c/stepping/TestStepAndBreakpoints.py

  Log Message:
  -----------
  [lldb] Add stop_reason_data property to SBThread python extensions (#117266)

Add a pythonic `stop_reason_data` property to `SBThread`. The property
produces a list of ints.


  Commit: c4daa205e5dbc4d29deb0abbb9fa58a1a91f143d
      https://github.com/llvm/llvm-project/commit/c4daa205e5dbc4d29deb0abbb9fa58a1a91f143d
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/Builtins.td
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Driver/ToolChains/Cuda.cpp
    M clang/lib/Driver/ToolChains/HIPAMD.cpp
    M clang/lib/Headers/hlsl/hlsl_intrinsics.h
    M clang/lib/Sema/HLSLExternalSemaSource.cpp
    M clang/lib/Sema/SemaExprCXX.cpp
    M clang/lib/Sema/SemaHLSL.cpp
    M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/RWBuffer-AST.hlsl
    M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
    M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
    A clang/test/AST/HLSL/is_typed_resource_element_compatible_concept.hlsl
    A clang/test/CodeGenHLSL/builtins/asdouble.hlsl
    A clang/test/Driver/cuda-no-threadsafe-statics.cu
    M clang/test/Preprocessor/riscv-target-features.c
    M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
    M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
    A clang/test/SemaHLSL/BuiltIns/asdouble-errors.hlsl
    M clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatible.hlsl
    R clang/test/SemaHLSL/Types/Traits/IsTypedResourceElementCompatibleErrors.hlsl
    M clang/tools/clang-shlib/CMakeLists.txt
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M lldb/bindings/interface/SBThreadExtensions.i
    M lldb/test/API/lang/c/stepping/TestStepAndBreakpoints.py
    M lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/IR/IntrinsicsDirectX.td
    M llvm/lib/Target/DirectX/DXIL.td
    M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/X86/X86CompressEVEX.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86SchedSapphireRapids.td
    A llvm/test/CodeGen/DirectX/asdouble.ll
    M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
    M llvm/test/TableGen/x86-fold-tables.inc
    M llvm/test/TableGen/x86-instr-mapping.inc
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp
    M llvm/utils/TableGen/X86ManualInstrMapping.def

  Log Message:
  -----------
  Address comments

Created using spr 1.3.5


Compare: https://github.com/llvm/llvm-project/compare/6e8a8f667dd4...c4daa205e5db

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