[all-commits] [llvm/llvm-project] cc721d: [AArch64][Codegen] Improve small shufflevector/con...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc721dba4e94c1d28214f81da0f1af79b6ca4218
      https://github.com/llvm/llvm-project/commit/cc721dba4e94c1d28214f81da0f1af79b6ca4218
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll

  Log Message:
  -----------
  [AArch64][Codegen] Improve small shufflevector/concat lowering for SME (#116662)

This now tries to widen the shuffle before generating a possibly
expensive SVE TBL, this may allow the shuffle to be matched as something
cheaper like a ZIP1.



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