[all-commits] [llvm/llvm-project] 55e8d6: [𝘀𝗽𝗿] initial version

[Vitaly Buka via All-commits]

  Branch: refs/heads/users/vitalybuka/spr/revert-aarch64-define-high-bits-of-fpr-and-gpr-registers-take-2-114827
  Home:   https://github.com/llvm/llvm-project
  Commit: 55e8d6af804ceda76fcdd026aa875b4005f481d7
      https://github.com/llvm/llvm-project/commit/55e8d6af804ceda76fcdd026aa875b4005f481d7
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
    M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
    M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
    M llvm/test/CodeGen/AArch64/misched-bundle.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
    M llvm/test/CodeGen/AArch64/preserve.ll
    M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
    R llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
    M llvm/unittests/Target/AArch64/CMakeLists.txt
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.4



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