[all-commits] [llvm/llvm-project] 822398: [X86][MC] Support R_X86_64_CODE_4_GOTPC32_TLSDESC ...

[Feng Zou via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8223982eba22323f7a737a62259d6d6048504107
      https://github.com/llvm/llvm-project/commit/8223982eba22323f7a737a62259d6d6048504107
  Author: Feng Zou <feng.zou at intel.com>
  Date:   2024-11-22 (Fri, 22 Nov 2024)

  Changed paths:
    M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
    M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    M llvm/test/MC/X86/tlsdesc-64.s

  Log Message:
  -----------
  [X86][MC] Support R_X86_64_CODE_4_GOTPC32_TLSDESC (#116908)

For

  lea name at tlsdesc(%rip), %reg

add

  R_X86_64_CODE_4_GOTPC32_TLSDESC = 45

if the instruction starts at 4 bytes before the relocation offset. This
should be used if reg is one of the additional general-purpose
registers, r16-r31, in Intel APX. It is similar to
R_X86_64_GOTPC32_TLSDESC and linker optimization must take the different
instruction encoding into account.

Linker can convert the instructions with R_X86_64_CODE_4_GOTPC32_TLSDESC
to

  mov $name at tpoff, %reg

if the first byte of the instruction at the relocation offset - 4 is
0xd5 (namely, encoded w/REX2 prefix) when possible.

Binutils patch:
https://github.com/bminor/binutils-gdb/commit/a533c8df598b5ef99c54a13e2b137c98b34b043c
Binutils mailthread:
https://sourceware.org/pipermail/binutils/2023-December/131463.html
ABI discussion:
https://groups.google.com/g/x86-64-abi/c/ACwD-UQXVDs/m/vrgTenKyFwAJ
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation



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