[all-commits] [llvm/llvm-project] 29afbd: [RISCV] Add DAG combine to convert (iX ctpop (bitc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29afbd5893fbf68a2b64321bee0c82233b8b852e
      https://github.com/llvm/llvm-project/commit/29afbd5893fbf68a2b64321bee0c82233b8b852e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/combine-ctpop-to-vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/expandload.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to convert (iX ctpop (bitcast (vXi1 A))) into vcpop.m. (#117062)

This only handles the simplest case where vXi1 is a legal vector type.
If the vector type isn't legal we need to go through type legalization,
but the pattern gets much harder to recognize after that. Either because
ctpop gets expanded due to Zbb not being enabled, or the bitcast
becoming a bitcast+extractelt, or the ctpop being split into multiple
ctpops and adds, etc.



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