[all-commits] [llvm/llvm-project] 0165f8: [RISCV] Fix the worst case for VSHA2MS in SiFive P...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0165f8817cbda4dc6a83db0d2994f7ece12726ff
      https://github.com/llvm/llvm-project/commit/0165f8817cbda4dc6a83db0d2994f7ece12726ff
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s

  Log Message:
  -----------
  [RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)

For each RVV instruction we should have a single WriteRes assignment to
the worst case scheduling class. This assignment is usually equal to
that of the largest LMUL + smallest SEW. My #114317 accidentally made
two of these assignments on `WriteVSHA2MSV_WorstCase`. This won't affect
our MachineScheduler nor most of our llvm-mca use cases (assuming you
populate the correct LMUL and SEW), yet it's not ideal either.

This patch fixes this issue by assigning the correct numbers and
resource mapping to `WriteVSHA2MSV_WorstCase`, which is equal to that of
largest LMUL + _largest_ SEW (Zvknh's scheduling properties are
special). I also added a MCA test to make sure we always pick up the
correct worst case numbers for P600's scheduling model.

Original issue was reported by @reidtatge



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