[all-commits] [llvm/llvm-project] f21bf5: AMDGPU: Shrink used number of registers for mfma s...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/gfx950/shrink-mfma-scale-inputs-based-on-format
  Home:   https://github.com/llvm/llvm-project
  Commit: f21bf54074830fd0148ace8b2458bb290ce5f7d5
      https://github.com/llvm/llvm-project/commit/f21bf54074830fd0148ace8b2458bb290ce5f7d5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-11-21 (Thu, 21 Nov 2024)

  Changed paths:
    M clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
    M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
    A llvm/test/Transforms/InstCombine/AMDGPU/mfma-scale.ll

  Log Message:
  -----------
  AMDGPU: Shrink used number of registers for mfma scale based on format

Currently the builtins assume you are using an 8-bit format that requires
an 8 element vector. We can shrink the number of registers if the format
requires 4 or 6.



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