[all-commits] [llvm/llvm-project] 329137: [mlir][vector] Fix 0-d vector transfer mask infere...

[Diego Caballero via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32913724acf9e02beed46999fee1424086b8c884
      https://github.com/llvm/llvm-project/commit/32913724acf9e02beed46999fee1424086b8c884
  Author: Diego Caballero <dieg0ca6aller0 at gmail.com>
  Date:   2024-11-20 (Wed, 20 Nov 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
    M mlir/test/Dialect/Vector/invalid.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][vector] Fix 0-d vector transfer mask inference (#116526)

When inferring the mask of a transfer operation that results in a single `i1` element, 
we could represent it using either `vector<i1>` or vector<1xi1>. To avoid type mismatches,
this PR updates the mask inference logic to consistently generate `vector<1xi1>` for
these cases. We can enable 0-D masks if they are needed in the future.

See: https://github.com/llvm/llvm-project/issues/116197



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