[all-commits] [llvm/llvm-project] 18be88: [NVPTX][NFC] Regenerate some tests checks (#116605)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Wed Nov 20 04:35:17 PST 2024
Branch: refs/heads/users/alexey-bataev/spr/slpadd-cost-estimation-for-gather-node-reshuffling
Home: https://github.com/llvm/llvm-project
Commit: 18be88e20abd9046217d79954c0477ee01ddd2f3
https://github.com/llvm/llvm-project/commit/18be88e20abd9046217d79954c0477ee01ddd2f3
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
Log Message:
-----------
[NVPTX][NFC] Regenerate some tests checks (#116605)
Use update_llc_test_checks.py to automate the test checks in some files
I was observing changes in locally.
Commit: a6fc489bb7a2e9fb3a7f70cccc181e4ee70374bf
https://github.com/llvm/llvm-project/commit/a6fc489bb7a2e9fb3a7f70cccc181e4ee70374bf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Cuda.h
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
M llvm/test/MC/AMDGPU/gfx940_asm_features.s
A llvm/test/MC/AMDGPU/gfx950-unsupported.s
A llvm/test/MC/AMDGPU/gfx950_invalid_encoding.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
M offload/DeviceRTL/CMakeLists.txt
Log Message:
-----------
AMDGPU: Add gfx950 subtarget definitions (#116307)
Mostly a stub, but adds some baseline tests and
tests for removed instructions.
Commit: cab732861c4885b714c70f2945de9f1dd4d725fa
https://github.com/llvm/llvm-project/commit/cab732861c4885b714c70f2945de9f1dd4d725fa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
AMDGPU: Add subtarget features for minimum3/maximum3 instructions (#116308)
gfx12 and gfx950 managed to produce 3 different permutations of this feature.
gfx12 supports f32 and f16, and gfx950 supports f32 and v2f16.
Commit: 5a556d55fb753d7e6e7a310a3fc0f7e83f8f9144
https://github.com/llvm/llvm-project/commit/5a556d55fb753d7e6e7a310a3fc0f7e83f8f9144
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
A llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
A llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
A llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
Log Message:
-----------
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
Commit: ca1b35a6c80d7075f4058c642d8c015e4fc8d304
https://github.com/llvm/llvm-project/commit/ca1b35a6c80d7075f4058c642d8c015e4fc8d304
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
A llvm/test/MC/AMDGPU/gfx950_asm_vop1.s
A llvm/test/MC/AMDGPU/gfx950_asm_vop1_dpp16.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop1.txt
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
AMDGPU: Add v_prng_b32 instruction for gfx950 (#116310)
Rand num instruction for stochastic rounding.
Commit: de5e4ebb5a1b82df5b1d27f423dbad30f872aac6
https://github.com/llvm/llvm-project/commit/de5e4ebb5a1b82df5b1d27f423dbad30f872aac6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M libcxx/include/bit
M libcxx/include/charconv
M libcxx/include/compare
M libcxx/include/expected
M libcxx/include/mdspan
M libcxx/include/memory_resource
M libcxx/include/ranges
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
Log Message:
-----------
[libc++] Remove transitive includes from empty headers (#116295)
This removes transitive includes that are only in a header that is empty
in a given C++ version.
Commit: 486e1d91e30068381f7ef4157361fe35c15abdee
https://github.com/llvm/llvm-project/commit/486e1d91e30068381f7ef4157361fe35c15abdee
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[RISCV][docs] Release Notes
These cover recent additions and changes to assembly and inline assembly
support.
Commit: 85ef9666c892d5e11fce3a0b84e4eaf4603256ee
https://github.com/llvm/llvm-project/commit/85ef9666c892d5e11fce3a0b84e4eaf4603256ee
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M libcxx/include/future
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/thread/futures/futures.async/async.pass.cpp
Log Message:
-----------
[libc++] Avoid including all of <thread> in <future> (#116541)
Commit: 3b8606be547acbc7ae93d943645e6d6c83f66983
https://github.com/llvm/llvm-project/commit/3b8606be547acbc7ae93d943645e6d6c83f66983
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
Re-land "[SandboxIR] Add debug checker to compare IR before/after a revert (#115968)" (#116671)
This PR re-lands https://github.com/llvm/llvm-project/pull/115968 with a
fix for a buildbot failure.
The `IRSnapshotChecker` class is only defined in debug mode, so its unit
tests must also be inside `#ifndef NDEBUG`.
Commit: f14e1a8597f83fa5bbc78befcb7059144d58ff5c
https://github.com/llvm/llvm-project/commit/f14e1a8597f83fa5bbc78befcb7059144d58ff5c
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h
R lldb/test/Shell/ObjectFile/ELF/elf-dynsym.test
Log Message:
-----------
Revert "Add support for reading the dynamic symbol table from PT_DYNAMIC (#112596)"
This reverts commit a7b2e73bcaa91255a20f1f2e692bec9eb6c17022.
This patch broke the greendragon bot
Failed Tests (10):
lldb-api :: python_api/sbplatform/TestLocateModuleCallback.py
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleCallbackSuccessWithModuleAndSymbol
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleCallbackSuccessWithOnlySymbol
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleCallbackSuccessWithSymbolAsModule
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleCallbackSuccessWithSymbolAsModuleAndSymbol
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleCallbackSuccessWithSymbolByPlatformUUID
lldb-unit :: Target/./TargetTests/LocateModuleCallbackTest/GetOrCreateModuleWithCachedModuleAndSymbol
lldb-unit :: Target/./TargetTests/ModuleCacheTest/GetAndPut
lldb-unit :: Target/./TargetTests/ModuleCacheTest/GetAndPutStrangeHostname
lldb-unit :: Target/./TargetTests/ModuleCacheTest/GetAndPutUuidExists
Commit: b769e3544a763a90abefd0dbe9254d83c765e1dc
https://github.com/llvm/llvm-project/commit/b769e3544a763a90abefd0dbe9254d83c765e1dc
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/GlobalModuleIndex.cpp
Log Message:
-----------
[clang][serialization] Blobify IMPORTS strings and signatures (#116095)
This PR changes a part of the PCM format to store string-like things in
the blob attached to a record instead of VBR6-encoding them into the
record itself. Applied to the `IMPORTS` section (which is very hot),
this speeds up dependency scanning by 2.8%.
Commit: 7b525495e8574285c19188be11e7ef8a51382ff3
https://github.com/llvm/llvm-project/commit/7b525495e8574285c19188be11e7ef8a51382ff3
Author: Wael Yehia <wyehia at ca.ibm.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M compiler-rt/test/profile/ContinuousSyncMode/online-merging.c
Log Message:
-----------
[test][PGO] Use -fprofile-update=atomic instead of mllvm option in ContinuousSyncMode/online-merging.c
Commit: 842fd1537521d38913aec5c9a081afedf97d88fe
https://github.com/llvm/llvm-project/commit/842fd1537521d38913aec5c9a081afedf97d88fe
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/X86/Target.cpp
M llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
Log Message:
-----------
[llvm-exegesis] Add explicit support for setting DF in X86 (#115644)
While llvm-exegesis has explicit support for setting EFLAGS which
contains DF, it can be nice sometimes to explicitly set DF, especially
given that it is modeled as a separate register within LLVM. This patch
adds the ability to do that by lowering setting the value to 0 or 1 to
cld and std respectively.
Commit: 3d172f3dff25ce70f7158330ac4068e48e2b364d
https://github.com/llvm/llvm-project/commit/3d172f3dff25ce70f7158330ac4068e48e2b364d
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Linker/IRMover.cpp
Log Message:
-----------
[Linker] Remove dead code handling recursive types. NFC. (#116652)
Commit: eac02611048a81bd78e461b651158c3c6557cb74
https://github.com/llvm/llvm-project/commit/eac02611048a81bd78e461b651158c3c6557cb74
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Linker/IRMover.cpp
Log Message:
-----------
[Linker] Remove a use of StructType::setBody. NFC. (#116653)
This falls out naturally after inlining finishType into its only
remaining use.
Commit: 1d0b2851224b1ef97c49faac2c666535f1997363
https://github.com/llvm/llvm-project/commit/1d0b2851224b1ef97c49faac2c666535f1997363
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/test/Shell/Unwind/windows-unaligned-x86_64.test
Log Message:
-----------
[lldb] Relax check for breakpoint site in Unwind/windows-unaligned-x86_64.test (#115318)
This test checks the thread backtrace for entries of intermediate frames
that aren't aligned to 16 bytes. In order to do that, it sets a single
breakpoint and makes sure we stop there. It seems sufficient, however,
to check that we hit the breakpoint itself and not which particular
site.
Commit: ac17b50f50bad5c1cc306e1813322ed2ae6e1ef0
https://github.com/llvm/llvm-project/commit/ac17b50f50bad5c1cc306e1813322ed2ae6e1ef0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Use getSignedTargetConstant. NFC
Commit: 6a863f7e2679a60f2f38ae6a920d0b6e1a2c1690
https://github.com/llvm/llvm-project/commit/6a863f7e2679a60f2f38ae6a920d0b6e1a2c1690
Author: lntue <lntue at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M libc/src/math/generic/exp10m1f16.cpp
M libc/src/math/generic/tanhf16.cpp
Log Message:
-----------
[libc] Fix signed zeros for exp10m1f16 and tanhf16. (#116654)
Commit: e59582b6f8f1be3e675866f6a5d661eb4c8ed448
https://github.com/llvm/llvm-project/commit/e59582b6f8f1be3e675866f6a5d661eb4c8ed448
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M libc/fuzzing/__support/hashtable_fuzz.cpp
M libc/src/__support/HashTable/generic/bitmask_impl.inc
M libc/src/__support/hash.h
M libc/test/src/__support/HashTable/group_test.cpp
M libc/test/src/__support/HashTable/table_test.cpp
Log Message:
-----------
[libc] avoid type-punning with inactive union member (#116685)
Commit: ce0cc8e9eb1ee5613a6fb442179a92c3fabf27c5
https://github.com/llvm/llvm-project/commit/ce0cc8e9eb1ee5613a6fb442179a92c3fabf27c5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/VE/VEInstrInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
Log Message:
-----------
[AArch64][VE][X86] Use getSignedTargetConstant. NFC
Commit: cde4ae789e4a2f408d06d2b0045cca22c201c47b
https://github.com/llvm/llvm-project/commit/cde4ae789e4a2f408d06d2b0045cca22c201c47b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
Log Message:
-----------
[ARM] Use getSignedTargetConstant. NFC
Commit: b42a81631491571c4b78d095917ebdddee69b04f
https://github.com/llvm/llvm-project/commit/b42a81631491571c4b78d095917ebdddee69b04f
Author: jimingham <jingham at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/ThreadPlanStack.h
M lldb/source/Target/ThreadPlanStack.cpp
Log Message:
-----------
Convert ThreadPlanStack's mutex to a shared mutex. (#116438)
I have some reports of A/B inversion deadlocks between the
ThreadPlanStack and the StackFrameList accesses. There's a fair bit of
reasonable code in lldb that does "While accessing the ThreadPlanStack,
look at that threads's StackFrameList", and also plenty of "While
accessing the ThreadPlanStack, look at the StackFrameList."
In all the cases I've seen so far, there was at most one of the locks
taken that were trying to mutate the list, the other three were just
reading. So we could solve the deadlock by converting the two mutexes
over to shared mutexes.
This patch is the easy part, the ThreadPlanStack mutex.
The tricky part was because these were originally recursive mutexes, and
recursive access to shared mutexes is undefined behavior according to
the C++ standard, I had to add a couple NoLock variants to make sure it
didn't get used recursively. Then since the only remaining calls are out
to ThreadPlans and ThreadPlans don't have access to their containing
ThreadPlanStack, converting this to a non-recursive lock should be safe.
Commit: e44c28f07ede2bd693e2372317880f57a635fa73
https://github.com/llvm/llvm-project/commit/e44c28f07ede2bd693e2372317880f57a635fa73
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticRefactoringKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/CodeGen/PowerPC/musttail-forward-declaration-inline.c
M clang/test/CodeGen/PowerPC/musttail-forward-declaration-weak.c
M clang/test/CodeGen/PowerPC/musttail-indirect.cpp
M clang/test/CodeGen/PowerPC/musttail-inline.c
M clang/test/CodeGen/PowerPC/musttail-undefined.c
M clang/test/CodeGen/PowerPC/musttail-weak.c
M clang/test/CodeGen/PowerPC/musttail.c
M clang/test/CodeGen/X86/x86_64-PR42672.c
M clang/test/Driver/module-output.cppm
M clang/test/Misc/pragma-attribute-strict-subjects.c
M clang/test/Modules/no-eager-load.cppm
M clang/test/Modules/same-decl-in-different-modules.cppm
M clang/test/OpenMP/for_simd_loop_messages.cpp
M clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/parallel_for_simd_messages.cpp
M clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/simd_linear_messages.cpp
M clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp
M clang/test/OpenMP/taskloop_simd_linear_messages.cpp
M clang/test/Parser/pragma-attribute.cpp
M clang/test/Refactor/Extract/ObjCProperty.m
M clang/test/Sema/asm.c
M clang/test/Sema/pragma-attribute-strict-subjects.c
M clang/test/SemaObjC/comptypes-legal.m
M clang/test/SemaOpenCL/access-qualifier.cl
Log Message:
-----------
[clang] Replace "can't" and "can not" in diagnostics with "cannot" (#116623)
See
https://discourse.llvm.org/t/cant-cannot-can-not-in-diagnostic-messages/83171
Commit: 6dceb0e34ed3dd4be72d211abb8c9c447bd57735
https://github.com/llvm/llvm-project/commit/6dceb0e34ed3dd4be72d211abb8c9c447bd57735
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx950_asm_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop1.txt
Log Message:
-----------
AMDGPU: Add V_CVT_F32_BF16 for gfx950 (#116311)
Commit: 0c421687f897b530a0fd3481fa03a2d29fd0b97c
https://github.com/llvm/llvm-project/commit/0c421687f897b530a0fd3481fa03a2d29fd0b97c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
A llvm/test/MC/AMDGPU/mai-gfx950.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt
A llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
Log Message:
-----------
AMDGPU: Add first gfx950 mfma instructions (#116312)
Scheduling info and hazards are wrong and TBD.
Commit: f8d1905a24c16bf6db42d428672401156ef6a473
https://github.com/llvm/llvm-project/commit/f8d1905a24c16bf6db42d428672401156ef6a473
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
M llvm/test/CodeGen/AArch64/popcount.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
Log Message:
-----------
[GlobalISel] Combine [S,U]SUBO (#116489)
We import the llvm.ssub.with.overflow.* Intrinsics, but the Legalizer
also builds them while legalizing other opcodes, see narrowScalarAddSub.
Commit: 31aa7f34e07c901773993dac0f33568307f96da6
https://github.com/llvm/llvm-project/commit/31aa7f34e07c901773993dac0f33568307f96da6
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Affine/Utils.h
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOps.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/test/Dialect/Affine/affine-expand-index-ops.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/invalid.mlir
M mlir/test/python/dialects/affine.py
Log Message:
-----------
[mlir][Affine] Let affine.[de]linearize_index omit outer bounds (#116103)
The affine.delinearize_index and affine.linearize_index operations, as
currently defined, require providing a length N basis to [de]linearize N
values. The first value in this basis is never used during lowering and
is unused during lowering. (Note that, even though it isn't used during
lowering it can still be used to, for example, remove length-1 outputs
from a delinearize).
This dead value makes sense in the original context of these operations,
which is linearizing or de-linearizing indexes to memref<>s, vector<>s,
and other shaped types, where that outer bound is avaliable and may be
useful for analysis.
However, other usecases exist where the outer bound is not known. For
example:
%thread_id_x = gpu.thread_id x : index
%0:3 = affine.delinearize_index %thread_id_x into (4, 16) : index,index,
index
In this code, we don't know the upper bound of the thread ID, but we do
want to construct the ?x4x16 grid of delinearized values in order to
further partition the GPU threads.
In order to support such usecases, we broaden the definition of
affine.delinearize_index and affine.linearize_index to make the outer
bound optional.
In the case of affine.delinearize_index, where the number of results is
a function of the size of the passed-in basis, we augment all existing
builders with a `hasOuterBound` argument, which, for backwards
compatibilty and to preserve the natural usage of the op, defaults to
`true`. If this flag is true, the op returns one result per basis
element, if it is false, it returns one extra result in position 0.
We also update existing canonicalization patterns (and move one of them
into the folder) to handle these cases. Note that disagreements about
the outer bound now no longer prevent delinearize/linearize
cancelations.
Commit: 55876278d362020503db5f0e66313829c40ff640
https://github.com/llvm/llvm-project/commit/55876278d362020503db5f0e66313829c40ff640
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/f16-abs.ll
Log Message:
-----------
[NVPTX] Add support for f16 fabs (#116107)
Add support for f16 and f16x2 support for abs. See PTX ISA 9.7.4.6. Half
Precision Floating Point Instructions: abs
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-abs
Commit: e0b522dd94e48229d587a54a3103ba1c198b16a7
https://github.com/llvm/llvm-project/commit/e0b522dd94e48229d587a54a3103ba1c198b16a7
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/test/CodeGen/DirectX/flatten-array.ll
Log Message:
-----------
[DirectX] Fix crash in DXILFlattenArrays for function declarations (#116690)
We were skipping intrinsics here, but really we need to skip all
function declarations - if the function doesn't have a body there's
nothing to walk.
Commit: a4e1a3dc8bc9bb971d8a38130254b4570f8b7a03
https://github.com/llvm/llvm-project/commit/a4e1a3dc8bc9bb971d8a38130254b4570f8b7a03
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Add another constructor to IndexedAllocationInfo (NFC) (#116684)
This patch adds another constructor to IndexedAllocationInfo that is
identical to the existing constructor except that the new one leaves
the CallStack field empty.
I'm planning to remove MemProf format Version 1. Then we will migrate
the users of the existing constructor to the new one as nobody will be
using the CallStack field anymore.
Adding the new constructor now allows us to migrate a few existing
users of the old constructor even before we remove the CallStack
field. In turn, that simplifies the patch to actually remove the
field.
Commit: ad9c0b369e86e75d56e229f294782a4eaf527226
https://github.com/llvm/llvm-project/commit/ad9c0b369e86e75d56e229f294782a4eaf527226
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
Log Message:
-----------
[SLP]Check if the gathered loads form full vector before attempting build it
Need to check that the number of gathered loads in the slice forms the
build vector to avoid compiler crash.
Fixes #116691
Commit: b083340cb663b6bd785dbd5864e5afd950745e35
https://github.com/llvm/llvm-project/commit/b083340cb663b6bd785dbd5864e5afd950745e35
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
A llvm/test/CodeGen/NVPTX/misched_func_call.ll
Log Message:
-----------
[llvm][NVPTX] Don't reorder MIs that construct a PTX function call (#116522)
With "-enable-misched", MachineScheduler can reorder MIs that must stick
together (in initially set order) to generate legal PTX code for a
function call.
When generating PTX code for the attached test (using LLVM before this
revision), the following invalid PTX code is generated:
```
{ // callseq 0, 0
.param .b64 param0;
st.param.f64 [param0], 0d0000000000000000;
.param .b64 retval0;
call.uni (retval0),
mul.lo.s32 %r7, %r10, %r3;
or.b32 %r8, %r4, %r7;
mul.lo.s32 %r9, %r2, %r8;
cvt.rn.f64.s32 %fd3, %r9;
quux,
(
param0
);
ld.param.f64 %fd1, [retval0];
} // callseq 0
```
Commit: ec67ad594b82fc2e763237d4e8d6bb2aea59110b
https://github.com/llvm/llvm-project/commit/ec67ad594b82fc2e763237d4e8d6bb2aea59110b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Format <string>
Commit: 50209e994200c98236a27b54e87e8c598d160402
https://github.com/llvm/llvm-project/commit/50209e994200c98236a27b54e87e8c598d160402
Author: David Green <david.green at arm.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
R llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
A llvm/test/CodeGen/AArch64/freeze.ll
Log Message:
-----------
[AArch64][GlobalISel] Move and update freeze.ll test. NFC
This adds a number of extra vector cases, notably the ptr vectors.
Commit: 36d47f88786d29d381545a5f88a7964b47d9a595
https://github.com/llvm/llvm-project/commit/36d47f88786d29d381545a5f88a7964b47d9a595
Author: David Green <david.green at arm.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AArch64/freeze.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize ptr vector freeze and implicit defs.
They can be treated the same as other s64 operations.
Commit: 1ced56540071476d0a4aa8cb5134106d02b5b7f1
https://github.com/llvm/llvm-project/commit/1ced56540071476d0a4aa8cb5134106d02b5b7f1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/scoped-fence-ops.c
Log Message:
-----------
[Clang] Add support for scoped atomic thread fence (#115545)
Summary:
Previously we added support for all of the atomic GNU extensions with
optional memory scoped except for `__atomic_thread_fence`. This patch
adds support for that. This should ideally allow us to generically emit
these LLVM scopes.
Commit: 94d100f2ba81c2bf0ef495f68d66ba8c94c71d2a
https://github.com/llvm/llvm-project/commit/94d100f2ba81c2bf0ef495f68d66ba8c94c71d2a
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
A lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
Log Message:
-----------
[lldb][dwarf] Compute fully qualified names on simplified template names with DWARFTypePrinter (#112811)
This is the second half of
https://github.com/llvm/llvm-project/pull/90008.
Essentially, it replaces the work of resolving template types when we
just need the qualified names with walking the DIE tree using
`DWARFTypePrinter`.
### Result
For an internal target, the time spent on `expr *this` for the first
time reduced from 28 secs to 17 secs.
Commit: b35f40688e3079d888932e0a35caa0b02d90db97
https://github.com/llvm/llvm-project/commit/b35f40688e3079d888932e0a35caa0b02d90db97
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/test/Bitcode/summary_version.ll
A llvm/test/ThinLTO/X86/Inputs/memprof-old-stackid-summary.bc
A llvm/test/ThinLTO/X86/memprof-old-stackid-summary.ll
Log Message:
-----------
[MemProf] Change the STACK_ID record to fixed width values (#116448)
The stack ids are hashes that are close to 64 bits in size, so emitting
as a pair of 32-bit fixed-width values is more efficient than a VBR.
This reduced the summary bitcode size for a large target by about 1%.
Bump the index version and ensure we can read the old format.
Commit: 5d33010f5edee8030d7b7d78c6e6f6992b659082
https://github.com/llvm/llvm-project/commit/5d33010f5edee8030d7b7d78c6e6f6992b659082
Author: David Truby <david.truby at arm.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M flang/test/Driver/dynamic-linker.f90
M flang/test/Driver/isysroot.f90
Log Message:
-----------
[NFC][flang] Fix driver linker tests on Windows (#116667)
Commit: 9c3665c8d26ba041a6e582e83cc2de0a1f63be48
https://github.com/llvm/llvm-project/commit/9c3665c8d26ba041a6e582e83cc2de0a1f63be48
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Log Message:
-----------
[rtsan] Add I/O multiplexing interceptors (#115227)
Intercepts in the family of `poll`, `select` and modern equivalents
`epoll` (linux only) and `kqueue` bsd family only.
These calls mirror the names of the system calls they call, which have
been verified on mac at least (e.g. kevent calls the system call
kevent).
Commit: dc087d1a338ca07b77c28522abb063e712b3877d
https://github.com/llvm/llvm-project/commit/dc087d1a338ca07b77c28522abb063e712b3877d
Author: Tom Honermann <tom.honermann at intel.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/IR/DIExpressionOptimizer.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
Avoid undefined behavior in shift operators during constant folding of DIExpressions. (#116466)
Bit shift operations with a shift operand greater than or equal to the bit width
of the (promoted) value type result in undefined behavior according to C++
[expr.shift]p1. This change adds checking for this situation and avoids attempts
to constant fold DIExpressions that would otherwise provoke such behavior.
An existing test that presumably intended to exercise shifts at the UB boundary
has been updated; it now checks for shifts of 64 bits instead of 65. This issue
was reported by a static analysis tool; no actual cases of shift operations that
would result in undefined behavior in practice have been identified.
Commit: 2310e3e3f2ccdab156abc7f9d186b2605027d8fe
https://github.com/llvm/llvm-project/commit/2310e3e3f2ccdab156abc7f9d186b2605027d8fe
Author: Daniel Sanders <daniel_l_sanders at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
Log Message:
-----------
[GlobalISel] Move DemandedElt's APInt size assert after isValid() check (#115979)
This prevents the assertion from wrongly triggering on invalid LLT's
Commit: 2de78815604e9027efd93cac27c517bf732587d2
https://github.com/llvm/llvm-project/commit/2de78815604e9027efd93cac27c517bf732587d2
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
A llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
R llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
[NFC] Move DroppedVariableStats to its own file and redesign it to be extensible. (#115563)
Move DroppedVariableStats code to its own file and change the class to
have an extensible design so that we can use it to add dropped
statistics to MIR passes and the instruction selector.
Commit: 3a3517c5e9d45a1d1aae5320887478b228b0f8be
https://github.com/llvm/llvm-project/commit/3a3517c5e9d45a1d1aae5320887478b228b0f8be
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/deque.bench.cpp
M libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/std/containers/sequences/vector/vector.modifiers/common.h
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.pass.cpp
Log Message:
-----------
[libc++] Improve the tests for vector::erase (#116265)
In particular, test everything with both a normal and a min_allocator,
add tests for a few corner cases and add tests with types that are
trivially relocatable. Also add tests that count the number of
assignments performed by vector::erase, since that is mandated by the
Standard.
This patch is a preparation for optimizing vector::erase.
Commit: 6e2b77d4696d4a672635c0ba1ead4824e2158a7d
https://github.com/llvm/llvm-project/commit/6e2b77d4696d4a672635c0ba1ead4824e2158a7d
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/CodeGen/MachineFunctionPass.h
M llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/unittests/MIR/CMakeLists.txt
A llvm/unittests/MIR/DroppedVariableStatsMIRTest.cpp
Log Message:
-----------
Add a pass to collect dropped var stats for MIR. (#115566)
This patch uses the DroppedVariableStats class to add dropped variable
statistics for MIR passes.
Commit: 78606af606deca9dd4de2ac1aec17a966c114bc2
https://github.com/llvm/llvm-project/commit/78606af606deca9dd4de2ac1aec17a966c114bc2
Author: Ziqing Luo <ziqing at udel.edu>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-warning-data-invocation.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Fix bug in unsafe casts to incomplete types (#116433)
Fixed the crash coming from attempting to get size of incomplete types.
Casting `span.data()` to a pointer-to-incomplete-type should be
immediately considered unsafe.
Solving issue #116286.
Co-authored-by: Ziqing Luo <ziqing_luo at apple.com>
Commit: 39bdf7a9db64927dfa4ad7fa85bcdf7a77a32ece
https://github.com/llvm/llvm-project/commit/39bdf7a9db64927dfa4ad7fa85bcdf7a77a32ece
Author: Doug Wyatt <doug at sonosphere.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
Log Message:
-----------
[Clang] SemaFunctionEffects: Fix bug where lambdas produced by template expansion weren't verified. (#116505)
---------
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
Commit: 81924ac1fb63273fc4648029301869a085bb9dac
https://github.com/llvm/llvm-project/commit/81924ac1fb63273fc4648029301869a085bb9dac
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/CodeGen/MachineFunctionPass.h
M llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/CodeGen/MachineFunctionPass.cpp
M llvm/unittests/MIR/CMakeLists.txt
R llvm/unittests/MIR/DroppedVariableStatsMIRTest.cpp
Log Message:
-----------
Revert "Add a pass to collect dropped var stats for MIR. (#115566)"
This reverts commit 6e2b77d4696d4a672635c0ba1ead4824e2158a7d.
Reverting due to buildbot failure:
unittests/IR/CMakeFiles/IRTests.dir/DroppedVariableStatsIRTest.cpp.o:DroppedVariableStatsIRTest.cpp:function llvm::DroppedVariableStatsIR::runAfterPass(llvm::StringRef, llvm::Any): error: undefined reference to 'llvm::DroppedVariableStatsIR::runOnModule(llvm::Module const*, bool)'
Commit: e914d97327ce5887e51c2d650987f2f48eda85c1
https://github.com/llvm/llvm-project/commit/e914d97327ce5887e51c2d650987f2f48eda85c1
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
R llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
R llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/IR/CMakeLists.txt
R llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
A llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
Revert "[NFC] Move DroppedVariableStats to its own file and redesign it to be extensible. (#115563)"
This reverts commit 2de78815604e9027efd93cac27c517bf732587d2.
Reverted due to buildbot failure:
unittests/IR/CMakeFiles/IRTests.dir/DroppedVariableStatsIRTest.cpp.o:DroppedVariableStatsIRTest.cpp:function llvm::DroppedVariableStatsIR::runAfterPass(llvm::StringRef, llvm::Any): error: undefined reference to 'llvm::DroppedVariableStatsIR::runOnModule(llvm::Module const*, bool)'
Commit: 170e1fe5a5211420923e32995d8bf3da196c2a54
https://github.com/llvm/llvm-project/commit/170e1fe5a5211420923e32995d8bf3da196c2a54
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/test/API/lang/cpp/stl/TestStdCXXDisassembly.py
Log Message:
-----------
[lldb] Fix regex support in SBTarget.modules_access (#116452)
First, `SRE_Pattern` does not exist on newer Python's, use
`type(re.compile(''))` like other Python extensions do. The dynamic type
is because some earlier versions of Python 3 do not have `re.Pattern`.
Second, `SBModule` has a `file` property, not a `path` property.
Commit: 5ae4d505c38872b3faaeea5779f6c25a9138bbc5
https://github.com/llvm/llvm-project/commit/5ae4d505c38872b3faaeea5779f6c25a9138bbc5
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h
A lldb/test/Shell/ObjectFile/ELF/elf-dynsym.test
Log Message:
-----------
Add support for reading the dynamic symbol table from PT_DYNAMIC (#116689)
Resubmissions of https://github.com/llvm/llvm-project/pull/112596 with
buildbot fixes.
Allow LLDB to parse the dynamic symbol table from an ELF file or memory
image in an ELF file that has no section headers. This patch uses the
ability to parse the PT_DYNAMIC segment and find the DT_SYMTAB,
DT_SYMENT, DT_HASH or DT_GNU_HASH to find and parse the dynamic symbol
table if the section headers are not present. It also adds a helper
function to read data from a .dynamic key/value pair entry correctly
from the file or from memory.
Commit: 204234a69c068032a1adac31f00b51f3b9efa778
https://github.com/llvm/llvm-project/commit/204234a69c068032a1adac31f00b51f3b9efa778
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.h
Log Message:
-----------
[mlir][SparseTensor][NFC] Pass tensor type to descriptor helper (#116468)
`getDescriptorFromTensorTuple` and `getMutDescriptorFromTensorTuple`
extract the tensor type from an `unrealized_conversion_cast` op that
serves as a workaround for missing 1:N dialect conversion support.
This commit changes these functions so that they explicitly receive the
tensor type as a function argument. This is in preparation of merging
the 1:1 and 1:N conversion drivers. The conversion patterns in this file
will soon start receiving multiple SSA values (`ValueRange`) from their
adaptors (instead of a single value that is the result of
`unrealized_conversion_cast`). It will no longer be possible to take the
tensor type from the `unrealized_conversion_cast` op. The
`unrealized_conversion_cast` workaround will disappear entirely.
Commit: cfc574a6cd13d2d0b77110b579c5cfcec744129f
https://github.com/llvm/llvm-project/commit/cfc574a6cd13d2d0b77110b579c5cfcec744129f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Use the OperandTransform field of a couple PatLeafs to simplify isel patterns. NFC
Commit: c51786b022bbff6c902cbcd2af5cc6535f6d9b5d
https://github.com/llvm/llvm-project/commit/c51786b022bbff6c902cbcd2af5cc6535f6d9b5d
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
R lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFDie.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/lib/DebugInfo/DWARF/DWARFDie.cpp
Log Message:
-----------
Revert "[lldb][dwarf] Compute fully qualified names on simplified template names with DWARFTypePrinter (#112811)"
This reverts commit 94d100f2ba81c2bf0ef495f68d66ba8c94c71d2a.
Reverted because of greendragon failure on the incremental arm64 bot
******************** TEST 'lldb-shell :: SymbolFile/DWARF/x86/simplified-template-names.cpp' FAILED ********************
Exit Code: 1
RUN: at line 7: /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/bin/clang --driver-mode=g++ --target=specify-a-target-or-use-a-_host-substitution --target=x86_64-pc-linux -g -gsimple-template-names /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp -o /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/test/Shell/SymbolFile/DWARF/x86/Output/simplified-template-names.cpp.tmp
/Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/bin/clang --driver-mode=g++ --target=specify-a-target-or-use-a-_host-substitution --target=x86_64-pc-linux -g -gsimple-template-names /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/llvm-project/lldb/test/Shell/SymbolFile/DWARF/x86/simplified-template-names.cpp -o /Users/ec2-user/jenkins/workspace/llvm.org/as-lldb-cmake/lldb-build/tools/lldb/test/Shell/SymbolFile/DWARF/x86/Output/simplified-template-names.cpp.tmp
ld: warning: -m is obsolete
ld: unknown option: --hash-style=gnu
clang: error: linker command failed with exit code 1 (use -v to see invocation)
Commit: 6626ed6f9fae79d35aba504f50bac4375686a03b
https://github.com/llvm/llvm-project/commit/6626ed6f9fae79d35aba504f50bac4375686a03b
Author: lialan <me at alanli.org>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-transforms.mlir
Log Message:
-----------
[MLIR] Fix `BubbleDownVectorBitCastForExtract` crash on non-static index (#116518)
Previously the patch was not expecting to handle non-static index, when
the index is a non constant value it will crash.
This patch is to make sure it return gracefully instead of crashing.
Commit: 6fe94c3bae596271c1f3b112d7635339a21c776d
https://github.com/llvm/llvm-project/commit/6fe94c3bae596271c1f3b112d7635339a21c776d
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M .github/new-issues-labeler.yml
M llvm/docs/DeveloperPolicy.rst
Log Message:
-----------
[Workflows] Enable commit access requests via GitHub issues (#100458)
This updates the auto-labeler to match a specific issue title that is
going to be used for requesting commit access and then add the
infrastructure:commit-access-request label.
This will notify the admin team who will be able to handle the request.
See
https://discourse.llvm.org/t/rfc-change-the-process-for-requesting-commit-access/80184
---------
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Commit: e17c91341be2f6a2d229ab44a4290e7d0ef2e094
https://github.com/llvm/llvm-project/commit/e17c91341be2f6a2d229ab44a4290e7d0ef2e094
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/python/mlir/extras/types.py
M mlir/test/python/ir/builtin_types.py
Log Message:
-----------
[mlir][python] Add `T.tf32` and missing tests for `tf32` (#116725)
Commit: cd418030de7ae75750bc4e48d1238baf03c675e5
https://github.com/llvm/llvm-project/commit/cd418030de7ae75750bc4e48d1238baf03c675e5
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Remove +a from the attribute test for zacas and zabha. NFC.
zacas and zabha don't require the 'a' or 'zaamo' extension after
https://github.com/llvm/llvm-project/pull/115694.
Commit: c526eb891bda371c0481fcdc1507adc496431d03
https://github.com/llvm/llvm-project/commit/c526eb891bda371c0481fcdc1507adc496431d03
Author: Greg Clayton <clayborg at gmail.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M lldb/test/Shell/ObjectFile/ELF/elf-dynsym.test
Log Message:
-----------
Fix buildbots with no x86 target.
Fix for: https://github.com/llvm/llvm-project/pull/116689
Commit: 31a4d2c2eb265708b2ff50f6f9c53685a3df8d10
https://github.com/llvm/llvm-project/commit/31a4d2c2eb265708b2ff50f6f9c53685a3df8d10
Author: vporpo <vporpodas at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Cleanup: Move callback registration from Scheduler to DAG (#116455)
This is a refactoring patch that moves the callback registration for
getting notified about new instructions from the scheduler to the DAG.
This makes sense from a design and testing point of view:
- the DAG should not rely on the scheduler for getting notified
- the notifiers don't need to be public
- it's easier to test the notifiers directly from within the DAG unit
tests
Commit: 1eaa17975dc568cff4fe31a79c0d147ef5c55301
https://github.com/llvm/llvm-project/commit/1eaa17975dc568cff4fe31a79c0d147ef5c55301
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/bail-out-one-loop.ll
Log Message:
-----------
[LoopInterchange] Bail out early if minimum loop nest is not met (#115128)
This patch bails out early if minimum depth
is not met. As it stands today, the pass computes
CacheCost before it attempts to do the transform.
This is not needed if minimum depth is not met.
This handles basic cases where depth is typically 1.
As the patch avoids unnecessary computation, it is aimed to improve
compile-time.
Commit: 08ef9396377cd60239a6312640f4fdc9c91a1703
https://github.com/llvm/llvm-project/commit/08ef9396377cd60239a6312640f4fdc9c91a1703
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/eh-frame-hdr.test
Log Message:
-----------
[BOLT] Overwrite .eh_frame_hdr in-place (#116730)
If the new EH frame header can fit into the original .eh_frame_hdr
section, overwrite it in-place and pad with zeroes.
Commit: a17f11baa1b622359547604555173384e220eef3
https://github.com/llvm/llvm-project/commit/a17f11baa1b622359547604555173384e220eef3
Author: Wael Yehia <wyehia at ca.ibm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
A compiler-rt/test/profile/ContinuousSyncMode/multi-threaded.cpp
M compiler-rt/test/profile/lit.cfg.py
Log Message:
-----------
[test][PGO] Add a multi-threaded test for continuous PGO.
Commit: ff9509e7d8ffac11ec25cea6c0dd7783097d3181
https://github.com/llvm/llvm-project/commit/ff9509e7d8ffac11ec25cea6c0dd7783097d3181
Author: Vasileios Porpodas <vporpodas at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
Log Message:
-----------
[SandboxVec][BottomUpVec][NFC] Add some comments
Commit: 661c593850715881d2805a59e90e6d87d8b9fbb8
https://github.com/llvm/llvm-project/commit/661c593850715881d2805a59e90e6d87d8b9fbb8
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-libcall-sincos-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll
M llvm/test/Other/optimize-inrange-gep.ll
M llvm/test/Transforms/Coroutines/coro-async.ll
M llvm/test/Transforms/FunctionAttrs/argmemonly.ll
A llvm/test/Transforms/FunctionAttrs/initializes.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
M llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll
M llvm/test/Transforms/PhaseOrdering/X86/unroll-vectorizer.ll
M llvm/test/Transforms/PhaseOrdering/memcpy-offset.ll
M llvm/test/Transforms/PhaseOrdering/pr95152.ll
Log Message:
-----------
[FunctionAttrs] Add the "initializes" attribute inference (#97373)
Add the "initializes" attribute inference.
This change is expected to have ~0.09% compile time regression, which
seems acceptable for interprocedural DSE.
https://llvm-compile-time-tracker.com/compare.php?from=9f10252c4ad7cffbbcf692fa9c953698f82ac4f5&to=56345c1cee4375eb5c28b8e7abf4803d20216b3b&stat=instructions%3Au
Commit: 738bdd49694f2722c9b58b6a1bb99eaa6c0ba051
https://github.com/llvm/llvm-project/commit/738bdd49694f2722c9b58b6a1bb99eaa6c0ba051
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
A llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
Log Message:
-----------
AMDGPU: Add V_CVT_PK_BF16_F32 for gfx950 (#116678)
Commit: 130a3150ec9cdaecdf9b0fa773b8c23a6b9bc527
https://github.com/llvm/llvm-project/commit/130a3150ec9cdaecdf9b0fa773b8c23a6b9bc527
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/MC/AMDGPU/mai-gfx950.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt
M llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
Log Message:
-----------
AMDGPU: Define v_mfma_f32_32x32x16_bf16 for gfx950 (#116679)
Unlike the existing gfx940 intrinsics using short/i16 in place of
bfloat, this uses the natural bfloat type.
Commit: 50224bd5ba009f02a012e22c0f87eba0028d6d88
https://github.com/llvm/llvm-project/commit/50224bd5ba009f02a012e22c0f87eba0028d6d88
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
A llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
Log Message:
-----------
AMDGPU: Handle gfx950 global_load_lds_* instructions (#116680)
Define global_load_lds_dwordx3 and global_load_dwordx4.
Oddly it seems dwordx2 was skipped.
Commit: 927032807dfdca5d94eb0a8707d38b605e95e407
https://github.com/llvm/llvm-project/commit/927032807dfdca5d94eb0a8707d38b605e95e407
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
A llvm/test/MC/AMDGPU/mubuf-gfx950.s
M llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
Log Message:
-----------
AMDGPU: Handle gfx950 96/128-bit buffer_load_lds (#116681)
Enforcing this limit in the clang builtin will come later.
Commit: 545917cb4b1c122b3626ea8d35fa7f93a44ae27f
https://github.com/llvm/llvm-project/commit/545917cb4b1c122b3626ea8d35fa7f93a44ae27f
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
Log Message:
-----------
[clangd] Harden incomingCalls() against possible misinterpretation of a range as pertaining to the wrong file (#111616)
`CallHierarchyIncomingCall::fromRanges` are interpreted as ranges in the
same file as the `CallHierarchyItem` representing the caller
(`CallHierarchyIncomingCall::from`).
In C/C++, it's possible for the calls to be in a different file than the caller,
as illustrated in the added test case.
With this patch, such calls are dropped, rather than their ranges being
incorrectly interpreted as pertaining to the wrong file.
Commit: 44a41b0660912a90be903a843e8b6f234fa0a2be
https://github.com/llvm/llvm-project/commit/44a41b0660912a90be903a843e8b6f234fa0a2be
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
Log Message:
-----------
[clangd] Check for other clangd extension capabilities under 'experimental' (#116531)
This is a follow-up to PR114699, with the same motivation: to support
clients which only support adding custom (language-specific or
server-specific) capabilities under 'experimental'.
Commit: 2e0a3c281b31eeffb1c12b53360f22760e246af2
https://github.com/llvm/llvm-project/commit/2e0a3c281b31eeffb1c12b53360f22760e246af2
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/DebugInfo/Generic/artificial-static-member.ll
Log Message:
-----------
[DebugInfo] Correct an overly-restrictive REQUIRES clause. (#116429)
Include a regular expression in the 'REQUIRES' clause, to run
the test on all matching targets (x86_64 *linux*).
The original patch restricted to test just to 'x86_64-linux'
https://github.com/llvm/llvm-project/pull/116327
Commit: 0488d1774b197513cf91d973e103f4e7de293c00
https://github.com/llvm/llvm-project/commit/0488d1774b197513cf91d973e103f4e7de293c00
Author: Florian Mayer <fmayer at google.com>
Date: 2024-11-18 (Mon, 18 Nov 2024)
Changed paths:
M compiler-rt/lib/hwasan/hwasan_platform_interceptors.h
M compiler-rt/lib/msan/tests/msan_test.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Log Message:
-----------
Reland "[Sanitizers] Intercept timer_create" (#113710) (#116717)
Original commit 2ec5c69b6872b8b474f3d37b9125d3d57d144d1b only
intercepted timer_create.
Because of how versioned libc symbols work, this could cause problems
where a newer `timer_create`
was used, and the result would be used by an older version. This would
cause crashes. This is why we
need to intercept all of the related functions.
Addresses https://github.com/llvm/llvm-project/issues/111847
Commit: 3b162f73d8027dcd8261666a40e9bdfb40f4dacc
https://github.com/llvm/llvm-project/commit/3b162f73d8027dcd8261666a40e9bdfb40f4dacc
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Features.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/CodeGen/AArch64/elf-pauthabi.c
A clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/Preprocessor/ptrauth_feature.c
Log Message:
-----------
[PAC][clang] Add signed GOT cc1 flag (#96160)
Add `-fptrauth-elf-got` clang cc1 flag and set `ptrauth_elf_got`
preprocessor feature and `PointerAuthELFGOT` LangOption correspondingly.
No additional checks like ensuring OS binary format is ELF are
performed: it should be done on clang driver level when a pauth-enabled
environment implying signed GOT enabled is requested.
If the cc1 flag is passed, "ptrauth-elf-got" IR module flag is set.
Commit: 456e60904b7b9de0a2bfabdac37ce9b8ac054750
https://github.com/llvm/llvm-project/commit/456e60904b7b9de0a2bfabdac37ce9b8ac054750
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms][NFC] Dialect Conversion: Delete dead code from `ConversionValueMapping` (#116758)
Commit: 55068dc3b7725f24de82dd4510162865c91a4f5e
https://github.com/llvm/llvm-project/commit/55068dc3b7725f24de82dd4510162865c91a4f5e
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/MainLoopBase.h
M lldb/include/lldb/Host/posix/MainLoopPosix.h
M lldb/include/lldb/Host/windows/MainLoopWindows.h
M lldb/source/Host/common/MainLoopBase.cpp
M lldb/source/Host/posix/MainLoopPosix.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/unittests/Host/MainLoopTest.cpp
Log Message:
-----------
[lldb] Add timed callbacks to the MainLoop class (#112895)
The motivating use case is being able to "time out" certain operations
(by adding a timed callback which will force the termination of the
loop), but the design is flexible enough to accomodate other use cases
as well (e.g. running a periodic task in the background).
The implementation builds on the existing "pending callback" mechanism,
by associating a time point with each callback -- every time the loop
wakes up, it runs all of the callbacks which are past their point, and
it also makes sure to sleep only until the next callback is scheduled to
run.
I've done some renaming as names like "TriggerPendingCallbacks" were no
longer accurate -- the function may no longer cause any callbacks to be
called (it may just cause the main loop thread to recalculate the time
it wants to sleep).
Commit: 980d5fb2d014f87fa3f6249e9196bb28d7afd9c6
https://github.com/llvm/llvm-project/commit/980d5fb2d014f87fa3f6249e9196bb28d7afd9c6
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[MLIR][omp] Add omp operations for OpenMP workshare (#101443)
Add the `omp.workshare` and `omp.workshare.loop_wrapper` operations used for the implementation of the `workshare` construct in flang.
Commit: 02b8ee281947f6cb39c7eb3c4bbba59322e9015b
https://github.com/llvm/llvm-project/commit/02b8ee281947f6cb39c7eb3c4bbba59322e9015b
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/MemoryBuiltins.cpp
A llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
Log Message:
-----------
[llvm] Improve llvm.objectsize computation by computing GEP, alloca and malloc parameters bound (#115522)
Using a naive expression walker, it is possible to compute valuable
information for
allocation functions, GEP and alloca, even in the presence of some
dynamic
information.
We don't rely on computeConstantRange to avoid taking advantage of
undefined behavior, which would be counter-productive wrt. usual
llvm.objectsize usage.
llvm.objectsize plays an important role in _FORTIFY_SOURCE definitions,
so improving its diagnostic in turns improves the security of compiled
application.
As a side note, as a result of recent optimization improvements, clang
no
longer passes
https://github.com/serge-sans-paille/builtin_object_size-test-suite
This commit restores the situation and greatly improves the scope of
code handled by the static version of __builtin_object_size.
Commit: 7d6713db600af1b4381149a0e794cbce99ca6cb2
https://github.com/llvm/llvm-project/commit/7d6713db600af1b4381149a0e794cbce99ca6cb2
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/workshare.f90
Log Message:
-----------
[flang][omp] Emit omp.workshare in frontend (#101444)
Emit the contents of OpenMP workshare constructs in `omp.workshare`.
Commit: 8bb21ae6c92c03b2487ee9b0df584c7a17446863
https://github.com/llvm/llvm-project/commit/8bb21ae6c92c03b2487ee9b0df584c7a17446863
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
Log Message:
-----------
[flang] Introduce custom loop nest generation for loops in workshare construct (#101445)
This alternative loop nest generation is used to generate an OpenMP loop nest instead of fir loops to facilitate parallelizing statements in an OpenMP `workshare` construct.
Commit: e7e5541616435b62da56e0a1fcc587c10b25321c
https://github.com/llvm/llvm-project/commit/e7e5541616435b62da56e0a1fcc587c10b25321c
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/OpenMP/Passes.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Passes/Pipelines.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/test/Fir/basic-program.fir
A flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
A flang/test/Transforms/OpenMP/lower-workshare-binding.mlir
A flang/test/Transforms/OpenMP/lower-workshare-cleanup.mlir
A flang/test/Transforms/OpenMP/lower-workshare-copyprivate.mlir
A flang/test/Transforms/OpenMP/lower-workshare-correct-parallelize.mlir
A flang/test/Transforms/OpenMP/lower-workshare-no-single.mlir
A flang/test/Transforms/OpenMP/lower-workshare-nowait.mlir
A flang/test/Transforms/OpenMP/lower-workshare-todo-cfg-dom.mlir
A flang/test/Transforms/OpenMP/lower-workshare-todo-cfg.mlir
M flang/tools/bbc/bbc.cpp
M flang/tools/tco/tco.cpp
Log Message:
-----------
[flang] Lower omp.workshare to other omp constructs (#101446)
Add a new pass that lowers an `omp.workshare` with its binding `omp.workshare.loop_wrapper` loop nests into other OpenMP constructs that can be lowered to LLVM.
More specifically, in order to preserve the sequential execution semantics of the code contained, it wraps portions that needs to be executed on a single thread in `omp.single` blocks, converts code that must be parallelized into `omp.wsloop` nests and inserts the appropriate synchronization.
Commit: 752dbd6112affa418e33910ac08bf9921f9c270b
https://github.com/llvm/llvm-project/commit/752dbd6112affa418e33910ac08bf9921f9c270b
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Interpreter/IncrementalExecutor.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
M clang/lib/Interpreter/Wasm.h
Log Message:
-----------
[clang-repl] Improve flags responsible for generating shared wasm binaries (#116735)
There are a couple changes in this PR that help getting clang-repl to
run in the browser. Using a jupyterlite instance for the example pasted
below
1) Updating flags responsible for generating shared wasm binaries that
need to be dynamically loaded Most Importantly as can be seen in the
changes `shared` and `allow-undefined` are crucial.
2) While exiting we encounter this.
Now as can be seen here
https://github.com/llvm/llvm-project/blob/cd418030de7ae75750bc4e48d1238baf03c675e5/clang/lib/Interpreter/Interpreter.cpp#L421-L430
We call cleanUP in the destructor. Now cleanUP through
IncrementalExecutor tries to deinitialize the JIT which wasn't even
intialized as runCtors in wasm.cpp is a no-op
https://github.com/llvm/llvm-project/blob/cd418030de7ae75750bc4e48d1238baf03c675e5/clang/lib/Interpreter/IncrementalExecutor.cpp#L94-L101
https://github.com/llvm/llvm-project/blob/cd418030de7ae75750bc4e48d1238baf03c675e5/clang/lib/Interpreter/Wasm.cpp#L107-L109
Commit: ead9ad2960ab72bf6142d8aeb164a097a7e407db
https://github.com/llvm/llvm-project/commit/ead9ad2960ab72bf6142d8aeb164a097a7e407db
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/Transforms/JumpThreading/PR33357-lvi-recursion.ll
M llvm/test/Transforms/JumpThreading/basic.ll
M llvm/test/Transforms/JumpThreading/crash.ll
M llvm/test/Transforms/JumpThreading/ddt-crash.ll
M llvm/test/Transforms/JumpThreading/ddt-crash4.ll
M llvm/test/Transforms/JumpThreading/landing-pad.ll
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/JumpThreading/pr9331.ll
M llvm/test/Transforms/JumpThreading/preserving-debugloc-br.ll
M llvm/test/Transforms/JumpThreading/unreachable-loops.ll
M llvm/test/Transforms/LCSSA/indirectbr.ll
M llvm/test/Transforms/LCSSA/invoke-dest.ll
M llvm/test/Transforms/LCSSA/pr28424.ll
M llvm/test/Transforms/LCSSA/pr28608.ll
M llvm/test/Transforms/LCSSA/remove-phis.ll
M llvm/test/Transforms/LCSSA/unused-phis.ll
M llvm/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll
M llvm/test/Transforms/LICM/alias-set-tracker-loss.ll
M llvm/test/Transforms/LICM/assume.ll
M llvm/test/Transforms/LICM/callbr-crash.ll
M llvm/test/Transforms/LICM/crash.ll
M llvm/test/Transforms/LICM/debug-value.ll
M llvm/test/Transforms/LICM/gc-relocate.ll
M llvm/test/Transforms/LICM/hoist-phi.ll
M llvm/test/Transforms/LICM/lcssa-ssa-promoter.ll
M llvm/test/Transforms/LICM/loopsink-pr39570.ll
M llvm/test/Transforms/LICM/outer-loop-deleted-before-licm.ll
M llvm/test/Transforms/LICM/pr32129.ll
M llvm/test/Transforms/LICM/pr37323.ll
M llvm/test/Transforms/LICM/pr38513.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/sink-promote.ll
M llvm/test/Transforms/LICM/sinking.ll
M llvm/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll
M llvm/test/Transforms/LoopDeletion/2017-07-11-incremental-dt.ll
M llvm/test/Transforms/LoopDeletion/bbi-59728.ll
M llvm/test/Transforms/LoopDeletion/crashbc.ll
M llvm/test/Transforms/LoopDeletion/pr53969.ll
M llvm/test/Transforms/LoopDeletion/simplify-then-delete.ll
M llvm/test/Transforms/LoopIdiom/non-canonical-loop.ll
M llvm/test/Transforms/LoopIdiom/scev-invalidation_topmostloop.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` from some regression tests [NFC] (#116739)
This PR removes tests with br i1 undef under
`llvm/tests/Transforms/JumpThreading, LCSSA, LICM, LoopDeletion,
LoopIdiom`.
Commit: 0a27e4eed4bb6ad83b5705558245c20f1083e6a1
https://github.com/llvm/llvm-project/commit/0a27e4eed4bb6ad83b5705558245c20f1083e6a1
Author: Ivan Radanov Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M offload/plugins-nextgen/common/src/JIT.cpp
Log Message:
-----------
[offload] Fix copy-paste defect in error message
Commit: 1e897ed28d26e192178247991158bd476e4a1106
https://github.com/llvm/llvm-project/commit/1e897ed28d26e192178247991158bd476e4a1106
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
Log Message:
-----------
[TTI][RISCV] Deduplicate type-based VP costing (#115983)
We have a lot of code in RISCVTTIImpl::getIntrinsicInstrCost for vp
intrinsics, which just forward the cost to the underlying non-vp cost
function.
However I just also noticed that there is generic code in BasicTTIImpl's
getIntrinsicInstrCost that does the same thing, added in #67178. The
only difference is that BasicTTIImpl doesn't yet handle it for
type-based costing. There doesn't seem to be any reason that it can't
since it's just inspecting the argument types.
This shuffles the VP costing up to handle both regular and type-based
costing, which allows us to deduplicate some of the VP specific costing
in RISCVTTIImpl by delegating it to BasicTTIImpl.h. More of those nodes
can be moved over to BasicTTIImpl.h later.
It's not NFC since it picks up a couple of VP nodes that had slipped
through the cracks. Future PRs can begin to move more of the code from
RISCVTTIImpl to BasicTTIImpl.
Commit: 7e85cb8a8a9de57ed10635b843662148a87b17e5
https://github.com/llvm/llvm-project/commit/7e85cb8a8a9de57ed10635b843662148a87b17e5
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
Log Message:
-----------
[AArch64][NFC] Add test as a representative of scalarizing a vector i… (#114107)
…nteger division
The last resort to vectorize a bundle of integer divisions is considered
scalarizing it. Currently, the cost estimates for scalarizing a vector
division can be considerably overestimated as is the scenario with this
motivating test case i.e. vector cost should not deviate much from the
scalar cost.
Future patch will try to improve the scalarization cost.
Commit: 3093b29b597b9a936a3e4d1c8bc4a7ccba8fc848
https://github.com/llvm/llvm-project/commit/3093b29b597b9a936a3e4d1c8bc4a7ccba8fc848
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
Log Message:
-----------
[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)
In a situation like the following:
```
undef %2.subreg = INST %1 ; DefMI (rematerializable),
; DefSubIdx = subreg
%3 = COPY %2 ; SrcIdx = DstIdx = 0
.... = SOMEINSTR %3, %2
```
there are no subranges for `%3` because the entire register is copied,
but after rematerialization the subrange of the rematerialized value
must be fixed up with the appropriate subranges for `.subreg`.
(To me this issue seemed a bit similar to the issue fixed by #96839, but
then related to rematerialization)
Commit: 3097c60928c773d8c7f97432491c0e4367b6215c
https://github.com/llvm/llvm-project/commit/3097c60928c773d8c7f97432491c0e4367b6215c
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/aarch64-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-no-scalarization-required.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/maximize-bandwidth-invalidate.ll
M llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-fp-ext-trunc-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
M llvm/test/Transforms/LoopVectorize/X86/fneg-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/mul_slm_16bit.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
M llvm/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
Log Message:
-----------
[LoopVectorize][NFC] Rewrite tests to check output of vplan cost model (#113697)
Currently it's very difficult to improve the cost model for tail-folded
loops because as soon as you add a VPInstruction::computeCost function
that adds the costs of instructions such as
VPInstruction::ActiveLaneMask
and VPInstruction::ExplicitVectorLength the assert in
LoopVectorizationPlanner::computeBestVF fails for some tests. This is
because the VF chosen by the legacy cost model doesn't match the vplan
cost model. See PR #90191. This assert is currently making it difficult
to improve the cost model.
Hopefully we will be in a position to remove the assert soon, however
in order to do that we have to fix up a whole bunch of tests that rely
upon the legacy cost model output. I've tried my best to update
these tests to use vplan output instead.
There is still work needed for the VF=1 case because the vplan cost
model is not printed out in this case. I've not attempted to fix those
in this patch.
Commit: 91c1699943a7f41c337d44b965c63bb6fc96de16
https://github.com/llvm/llvm-project/commit/91c1699943a7f41c337d44b965c63bb6fc96de16
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Sema/CheckExprLifetime.cpp
Log Message:
-----------
[clang] [NFC] Merge conditions (#116612)
Commit: 0775088234f1a98d1b18a2ff846d851509f5c023
https://github.com/llvm/llvm-project/commit/0775088234f1a98d1b18a2ff846d851509f5c023
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
A mlir/test/Dialect/Linalg/decompose-tensor-pack-tile.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-pack.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-unpack-tile.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-unpack.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-pack.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-unpack.mlir
A mlir/test/Dialect/Linalg/td/decompose-pack.mlir
R mlir/test/Dialect/Linalg/td/generalize-pack.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
Log Message:
-----------
[mlir] Rename `GeneralizeOuterUnitDims{Un}PackOpPattern`s (#116439)
Renames:
* `GeneralizeOuterUnitDimsPackOpPattern`,
* `GeneralizeOuterUnitDimsUnPackOpPattern`,
as
* `DecomposeOuterUnitDimsPackOpPattern`,
* `DecomposeOuterUnitDimsUnPackOpPattern`,
respectively. The new name better describes the underlying
transformation.
Commit: 6aa80f00574826a0c2f2972a659517a9bf1efece
https://github.com/llvm/llvm-project/commit/6aa80f00574826a0c2f2972a659517a9bf1efece
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/SemaCXX/builtin-bit-cast.cpp
Log Message:
-----------
[Clang] [NFC] Add single quotes around __builtin_bit_cast (#116120)
Fixes #116118
Commit: 8cd348c96a845e4afb3e924355e98b5558683d01
https://github.com/llvm/llvm-project/commit/8cd348c96a845e4afb3e924355e98b5558683d01
Author: Davide <39653004+Tazdevil971 at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/test/CodeGen/Mips/fp16-promote.ll
Log Message:
-----------
[MIPS] Updated MIPS N calling conventions so that fp16 arguments no longer cause a crash (#116569)
This PR fixes a bug introduced by #110199, which causes any half float
argument to crash the compiler on MIPS64.
Currently compiling this bit of code with `llc -mtriple=mips64`:
```
define void @half_args(half %a) nounwind {
entry:
ret void
}
```
Crashes with the following log:
```
LLVM ERROR: unable to allocate function argument #0
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: llc -mtriple=mips64
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'MIPS DAG->DAG Pattern Instruction Selection' on function '@half_args'
#0 0x000055a3a4013df8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x32d0df8)
#1 0x000055a3a401199e llvm::sys::RunSignalHandlers() (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x32ce99e)
#2 0x000055a3a40144a8 SignalHandler(int) Signals.cpp:0:0
#3 0x00007f00bde558c0 __restore_rt libc_sigaction.c:0:0
#4 0x00007f00bdea462c __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
#5 0x00007f00bde55822 gsignal ./signal/../sysdeps/posix/raise.c:27:6
#6 0x00007f00bde3e4af abort ./stdlib/abort.c:81:7
#7 0x000055a3a3f80e3c llvm::report_fatal_error(llvm::Twine const&, bool) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x323de3c)
#8 0x000055a3a2e20dfa (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x20dddfa)
#9 0x000055a3a2a34e20 llvm::MipsTargetLowering::LowerFormalArguments(llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&) const MipsISelLowering.cpp:0:0
#10 0x000055a3a3d896a9 llvm::SelectionDAGISel::LowerArguments(llvm::Function const&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x30466a9)
#11 0x000055a3a3e0b3ec llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x30c83ec)
#12 0x000055a3a3e09e21 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x30c6e21)
#13 0x000055a3a2aae1ca llvm::MipsDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) MipsISelDAGToDAG.cpp:0:0
#14 0x000055a3a3e07706 llvm::SelectionDAGISelLegacy::runOnMachineFunction(llvm::MachineFunction&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x30c4706)
#15 0x000055a3a3051ed6 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x230eed6)
#16 0x000055a3a35a3ec9 llvm::FPPassManager::runOnFunction(llvm::Function&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x2860ec9)
#17 0x000055a3a35ac3b2 llvm::FPPassManager::runOnModule(llvm::Module&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x28693b2)
#18 0x000055a3a35a499c llvm::legacy::PassManagerImpl::run(llvm::Module&) (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x286199c)
#19 0x000055a3a262abbb main (/home/davide/Ps2/rps2-tools/prefix/bin/llc+0x18e7bbb)
#20 0x00007f00bde3fc4c __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:74:3
#21 0x00007f00bde3fd05 call_init ./csu/../csu/libc-start.c:128:20
#22 0x00007f00bde3fd05 __libc_start_main at GLIBC_2.2.5 ./csu/../csu/libc-start.c:347:5
#23 0x000055a3a2624921 _start /builddir/glibc-2.39/csu/../sysdeps/x86_64/start.S:117:0
```
This is caused by the fact that after the change, `f16`s are no longer
lowered as `f32`s in calls.
Two possible fixes are available:
- Update calling conventions to properly support passing `f16` as
integers.
- Update `useFPRegsForHalfType()` to return `true` so that `f16` are
still kept in `f32` registers, as before #110199.
This PR implements the first solution to not introduce any more ABI
changes as #110199 already did.
As of what is the correct ABI for halfs, I don't think there is a
correct answer. GCC doesn't support halfs on MIPS, and I couldn't find
any information on old MIPS ABI manuals either.
Commit: 4818dd33d84fcf41c08419a9960cadd473d536a9
https://github.com/llvm/llvm-project/commit/4818dd33d84fcf41c08419a9960cadd473d536a9
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
Log Message:
-----------
[HLSL] Rename resource's "h" member to "__handle". NFC (#116696)
This makes it clearer that the handle is an implementation detail by
using a name that's reserved.
Commit: 497b1ae15f7984c673e2d7af7bb365645723ca93
https://github.com/llvm/llvm-project/commit/497b1ae15f7984c673e2d7af7bb365645723ca93
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/Type.h
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Assembler/target-type-properties.ll
Log Message:
-----------
[IR] Improve check for target extension types disallowed in globals. (#116639)
For target extension types that are not allowed to be used as globals,
also disallow them nested inside array and structure types.
Commit: f77126c549ced0db57d912bcd87145b1309843be
https://github.com/llvm/llvm-project/commit/f77126c549ced0db57d912bcd87145b1309843be
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-libcall-sincos-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/store-zero.ll
M llvm/test/Other/optimize-inrange-gep.ll
M llvm/test/Transforms/Coroutines/coro-async.ll
M llvm/test/Transforms/FunctionAttrs/argmemonly.ll
R llvm/test/Transforms/FunctionAttrs/initializes.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
M llvm/test/Transforms/PGOProfile/memprof_internal_linkage.ll
M llvm/test/Transforms/PhaseOrdering/X86/unroll-vectorizer.ll
M llvm/test/Transforms/PhaseOrdering/memcpy-offset.ll
M llvm/test/Transforms/PhaseOrdering/pr95152.ll
Log Message:
-----------
Revert "[FunctionAttrs] Add the "initializes" attribute inference (#97373)"
This reverts commit 661c593850715881d2805a59e90e6d87d8b9fbb8.
Multiple buildbot failures, e.g. https://lab.llvm.org/buildbot/#/builders/108/builds/6096
Commit: 4bd982d528ac2b2cb73d9fe6e534db84cfc16aaf
https://github.com/llvm/llvm-project/commit/4bd982d528ac2b2cb73d9fe6e534db84cfc16aaf
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
Log Message:
-----------
[HLSL] Fix resource kind for RasterizerOrderedStructuredBuffer (#116700)
This is a kind of StructuredBuffer, so it should be "Raw" and not
"Typed".
Commit: 43f84e7937d12a4d868a51244e9b3572812a1572
https://github.com/llvm/llvm-project/commit/43f84e7937d12a4d868a51244e9b3572812a1572
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
M clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p2-cxx0x.cpp
Log Message:
-----------
[Clang] Enhance diagnostic by attaching source location to deduced type in trailing return without auto (#115786)
Fixes #78694
Commit: 738a047ed6380efdfd4b64968881675347d7f915
https://github.com/llvm/llvm-project/commit/738a047ed6380efdfd4b64968881675347d7f915
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCXX/warn-shadow.cpp
Log Message:
-----------
[Clang] Skip shadow warnings for enum constants in distinct class scopes (#115656)
Fixes #62588
Commit: d4f2b71c3fd89da4dbdec0091a97a6a2c411145d
https://github.com/llvm/llvm-project/commit/d4f2b71c3fd89da4dbdec0091a97a6a2c411145d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86] Fix position of immediate argument in AVX512 VPCMP comparisons (#116646)
The 'i' arg was being put between the 'm' and 'b' args instead of afterwards like other avx512 instructions (VCMPPS/D, VPERMILPS/D etc.).
Commit: 51ad2901ca54a01a72db71622b116eb27ea6dcf2
https://github.com/llvm/llvm-project/commit/51ad2901ca54a01a72db71622b116eb27ea6dcf2
Author: Yihe Li <winmikedows at hotmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/Expr.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p3.cpp
M clang/test/Sema/c2x-nodiscard.c
M clang/test/SemaCXX/warn-unused-result.cpp
Log Message:
-----------
[Clang] Improve diagnostic on `[[nodiscard]]` attribute (#112521)
A follow-up to #112289.
When diagnosing an unused return value, if the diagnostic
is triggered by an attribute attached to a type, the type name
is now included in the diagnostic.
---------
Co-authored-by: Sirraide <aeternalmail at gmail.com>
Commit: b3e2b1a7eb258a7c9c55691d08342eface083499
https://github.com/llvm/llvm-project/commit/b3e2b1a7eb258a7c9c55691d08342eface083499
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.h
Log Message:
-----------
[clang-tidy][NFC] fix typo in ExceptionAnalyzer; `replace count()>0` with `contains` (#116635)
Commit: b2ec416aa5bcd89c4bc295163d60e5a2ecb99212
https://github.com/llvm/llvm-project/commit/b2ec416aa5bcd89c4bc295163d60e5a2ecb99212
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/test/CodeGen/arm-mve-intrinsics/compare.c
Log Message:
-----------
[ARM] Fix NaN behaviour for MVE compare intrinsics (#116371)
The MVE intrinsics are defined as having the same behaviour as the
instructions which they correspond to. In particular, the vcmpleq and
vcmpltq intrinsics correspond to the VCMP instruction with the LE or LT
condition. However, these instructions with these two conditions do not
match the normal IEEE754 behaviour for NaNs, they return true if either
operand is a NaN, instead of false. Therefore we need to generate `fcmp`
IR instructions with the `ule` and `ult` conditions, instead of `ole`
and `olt`.
This differs from AdvSIMD, where only instructions with the EQ, GE and
GT conditions are available, and the intrinsics for the others are
defined by swapping the condition and operand order, so the results
match the IEEE754 behaviour for NaNs.
Commit: 61726add1b03a13906bd618a784d040a182e5968
https://github.com/llvm/llvm-project/commit/61726add1b03a13906bd618a784d040a182e5968
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
M llvm/test/MC/AArch64/SVE/fexpa.s
Log Message:
-----------
[AArch64] Update predicate for FEXPA (#116613)
This patch updates predicate and backend tests for FEXPA instructions to
match [latest
spec](https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions/FEXPA--Floating-point-exponential-accelerator-).
Commit: 6f53ae6e613f5f7011c1752b94038114f4e1cc94
https://github.com/llvm/llvm-project/commit/6f53ae6e613f5f7011c1752b94038114f4e1cc94
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
Log Message:
-----------
[X86] Properly chain PROBED_ALLOCA / SEG_ALLOCA (#116508)
These nodes should appear between CALLSEQ_START / CALLSEQ_END.
Previously, they could be scheduled after CALLSEQ_END because the nodes
didn't update the chain.
The change in a test is due to X86 call frame optimizer pass bailing out
for a particular call when CALLSEQ_START / CALLSEQ_END are not in the
same basic block. This happens because SEG_ALLOCA is expanded into a
sequence of basic blocks early. It didn't bail out before because the
closing CALLSEQ_END was scheduled before SEG_ALLOCA, in the same basic
block as CALLSEQ_START.
While here, simplify creation of these nodes: allocating a virtual
register and copying `Size` into it were unnecessary.
Commit: 95ab42661e8d1f57a4ef8e9d058b44627af0e58d
https://github.com/llvm/llvm-project/commit/95ab42661e8d1f57a4ef8e9d058b44627af0e58d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
Log Message:
-----------
[X86] Attempt to canonicalize vXf64 SHUFPD shuffle masks with undef elts to improve further folding (#116419)
Currently when creating a SHUFPD immediate mask, any undef shuffle elements are set to 0, which can limit options for further shuffle combining.
This patch attempts to canonicalize the mask to improve folding: first by detecting a per-lane broadcast style mask (which can allow us to fold to UNPCK instead), and second ensure any undef elements are set to an 'inplace' value to improve chances of the SHUFPD later folding to a BLENDPD (or be bypassed in a SimplifyMultipleUseDemandedVectorElts call).
This is very similar to canonicalization we already attempt in getV4X86ShuffleImm for vXi32/vXf32 SHUFPS/SHUFD shuffles.
Commit: 843498d4545b86fbd9c5b83d28bd39a22df52ef4
https://github.com/llvm/llvm-project/commit/843498d4545b86fbd9c5b83d28bd39a22df52ef4
Author: Peter Smith <peter.smith at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
A lld/test/ELF/aarch64-thunk-bti-multipass.s
M lld/test/ELF/aarch64-thunk-bti.s
Log Message:
-----------
[LLD][AArch64] Add test for missing AArch64 BTI thunk (#116665)
A follow up to PR #116402 to add a regression test. The original change
fixed the reproducer but that was not suitable to use as a regression
test.
This test case will fail with a LLD prior to #116402.
The disassembly for the thunk that starts as a short thunk but is later
a long thunk isn't quite right. It is missing a $d mapping symbol. I
think this can be fixed, but I've not done that in this patch to keep it
test only. It is not a regression introduced in #116402.
I've also removed a spurious --threads=1 I noticed in the original test
aarch64-thunk-bti.s
Commit: 7dcefb37a42e61ec6763f0c1e48a7a2e8ea2f6b1
https://github.com/llvm/llvm-project/commit/7dcefb37a42e61ec6763f0c1e48a7a2e8ea2f6b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86] Tidyup up AVX512 FPCLASS instruction naming (#116661)
FPCLASS is a unary instruction with an immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name
Commit: 129a1a27da34eab1e358f4a403f05e8efe44c586
https://github.com/llvm/llvm-project/commit/129a1a27da34eab1e358f4a403f05e8efe44c586
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/tools/amdgpu-arch/AMDGPUArch.cpp
R clang/tools/amdgpu-arch/AMDGPUArchByHSA.cpp
A clang/tools/amdgpu-arch/AMDGPUArchByKFD.cpp
M clang/tools/amdgpu-arch/CMakeLists.txt
Log Message:
-----------
[amdgpu-arch] Replace use of HSA with reading sysfs directly (#116651)
Summary:
For Linux systems, we currently use the HSA library to determine the
installed GPUs. However, this isn't really necessary and adds a
dependency on the HSA runtime as well as a lot of overhead. Instead,
this patch uses the `sysfs` interface exposed by `amdkfd` to do this
directly.
Commit: cac6f2114974ca57e34600e21ae8df063c7edc10
https://github.com/llvm/llvm-project/commit/cac6f2114974ca57e34600e21ae8df063c7edc10
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/unique-dep-matrix.ll
Log Message:
-----------
[LoopInterchange] Make the entries of the Dependency Matrix unique (#116195)
The entries in the dependency matrix can contain a lot of duplicates,
which is unnecessary and results in more checks that we can avoid, and
this patch adds that.
Commit: 8a6a76b1e122536858531a8612cbbe6869803393
https://github.com/llvm/llvm-project/commit/8a6a76b1e122536858531a8612cbbe6869803393
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
Log Message:
-----------
[clangd] Let DefineOutline tweak handle member function templates (#112345)
Commit: b24acc06e1d465b3e3e4e28515dd437f6a7454f2
https://github.com/llvm/llvm-project/commit/b24acc06e1d465b3e3e4e28515dd437f6a7454f2
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
A flang/test/Fir/target-rewrite-integer-loongarch64.fir
Log Message:
-----------
[Flang][LoongArch] Add sign extension for i32 arguments and returns in function signatures. (#116146)
In loongarch64 LP64D ABI, `unsigned 32-bit` types, such as unsigned int,
are stored in general-purpose registers as proper sign extensions of
their 32-bit values. Therefore, Flang also follows it if a function
needs to be interoperable with C.
Reference:
https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#Fundamental-types
Commit: a59976bea8ad76f18119a11391dc8ba3e6ba07d5
https://github.com/llvm/llvm-project/commit/a59976bea8ad76f18119a11391dc8ba3e6ba07d5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll
Log Message:
-----------
[InstCombine] Drop noundef attributes in `foldCttzCtlz` (#116718)
Closes https://github.com/llvm/llvm-project/issues/112068.
Commit: 42ed7757835122a63477b5783215e1100cd0b709
https://github.com/llvm/llvm-project/commit/42ed7757835122a63477b5783215e1100cd0b709
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstSimplify/logic-of-fcmps.ll
Log Message:
-----------
[InstSimplify] Generalize `simplifyAndOrOfFCmps` to handle fabs (#116590)
This patch generalizes https://github.com/llvm/llvm-project/issues/81027
to handle pattern `and/or (fcmp ord/uno X, 0), (fcmp pred fabs(X), Y)`.
Alive2: https://alive2.llvm.org/ce/z/tsgUrz
The correctness is straightforward because `fcmp ord/uno X, 0.0` is
equivalent to `fcmp ord/uno fabs(X), 0.0`. We may generalize it to
handle fneg as well.
Address comment
https://github.com/llvm/llvm-project/pull/116065#pullrequestreview-2434796846
Commit: 55fad5e980efbcc4a581057c558fedaadf91e877
https://github.com/llvm/llvm-project/commit/55fad5e980efbcc4a581057c558fedaadf91e877
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/tools/amdgpu-arch/AMDGPUArchByKFD.cpp
Log Message:
-----------
[amdgpu-arch] Fix unused StringRef result
Commit: 12180717cb1f94741c1cc63a9684aa20af7b6140
https://github.com/llvm/llvm-project/commit/12180717cb1f94741c1cc63a9684aa20af7b6140
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[NFC][LoopVectorize] Introduce new getEstimatedRuntimeVF function (#116247)
There are lots of places where we try to estimate the runtime
vectorisation factor based on the getVScaleForTuning TTI hook.
I've added a new getEstimatedRuntimeVF function and taught
several places in the vectoriser to use this new function.
Commit: c4030c896de00efa5eb2f79bba7902c5198ba893
https://github.com/llvm/llvm-project/commit/c4030c896de00efa5eb2f79bba7902c5198ba893
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
Log Message:
-----------
[RISCV] Fix FP64 DinX R Regclass (#116688)
This was a typo in llvm/llvm-project#112983 that didn't cause build
failures but is still wrong.
Commit: b03a747fc0fc27ddcad3b50f2117d8150ee262f1
https://github.com/llvm/llvm-project/commit/b03a747fc0fc27ddcad3b50f2117d8150ee262f1
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang] constexpr built-in reduce mul function. (#116626)
Part of #51787.
Follow up of #116243.
This patch adds constexpr support for the built-in reduce mul function.
Commit: 2153672ba32741de19a063ed26a2a5ed4b1c4b59
https://github.com/llvm/llvm-project/commit/2153672ba32741de19a063ed26a2a5ed4b1c4b59
Author: Zichen Lu <mikaovo2000 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/CompilationInterfaces.h
M mlir/include/mlir/Target/LLVM/ModuleToObject.h
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Target/LLVM/ModuleToObject.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/unittests/Target/LLVM/SerializeNVVMTarget.cpp
Log Message:
-----------
[MLIR] Add callback functions for ModuleToObject (#116007)
In ModuleToObject flow, users may want to add some callback functions
invoked with LLVM IR/ISA for debugging or other purposes.
Commit: 01a1ca72e86e293822dedb7fb1bd6f2095f2dbe4
https://github.com/llvm/llvm-project/commit/01a1ca72e86e293822dedb7fb1bd6f2095f2dbe4
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libcxx/test/std/utilities/utility/pairs/pairs.pair/ctor.default.pass.cpp
Log Message:
-----------
[libc++][NFC] Format a pait test
I'll be modifying this test in a future PR.
Commit: 4f0403fe96c0e93a1e75cbca6077c46ea3a5aad8
https://github.com/llvm/llvm-project/commit/4f0403fe96c0e93a1e75cbca6077c46ea3a5aad8
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/sinksplat.ll
Log Message:
-----------
[CodeGen][AArch64] Sink splat operands of FMul instructions (#116222)
Sink shuffle operands of FMul instructions if these are splats, as we
can generate lane-indexed variants for these.
Commit: 75a04c656061fb72c9259c4ae5fb8e41c396dd65
https://github.com/llvm/llvm-project/commit/75a04c656061fb72c9259c4ae5fb8e41c396dd65
Author: WÁNG Xuěruì <git at xen0n.name>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
Log Message:
-----------
[LoongArch][NFC] Fix the operand constraint of AMCAS instructions (#114508)
The `rd` operand of AMCAS instructions is both read and written, because
of the nature of compare-and-swap operations, but currently it is not
declared as such. Fix it for upcoming codegen enablement changes. In
order to do that, a piece of LoongArchAsmParser logic that relied on
TableGen-erated enum variants being ordered in a specific way needs
updating; this will be addressed in a following refactor. No functional
change intended.
While at it, restore vertical alignment for the definition lines.
Suggested-by: tangaac <tangyan01 at loongson.cn>
Link:
https://github.com/llvm/llvm-project/pull/114398#discussion_r1825362676
Commit: 9e0ea8c8816d9f5837ad3357be32dddce28c7fb1
https://github.com/llvm/llvm-project/commit/9e0ea8c8816d9f5837ad3357be32dddce28c7fb1
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add extra test for preserving !llvm.access.group
Add variant with different metadata on all loads, for
https://github.com/llvm/llvm-project/pull/115868
Commit: c727b48287cc96888f9e262f23d53cf635cf3b3d
https://github.com/llvm/llvm-project/commit/c727b48287cc96888f9e262f23d53cf635cf3b3d
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
A llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls (#116075)
On loongarch64 with lsx extension, we select `VBITREV_W` for `v4i32 (xor
X, (shl splat(1), Y))`:
https://github.com/llvm/llvm-project/blob/8e6630391699116641cf390a10476295b7d4b95c/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td#L1583-L1584
And `vsplat_imm_eq_1` is defined as:
https://github.com/llvm/llvm-project/blob/8e6630391699116641cf390a10476295b7d4b95c/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td#L77-L87
For the `(bitconvert (v4i32 (build_vector)))` case, the pattern is
expected to be:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (bitconvert:{ *:[v4i32] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplat_imm_eq_1>>, v4i32:{ *:[v4i32] }:$vk))
RESULT: (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```
However, `simplifyTree` drops the `bitconvert` node and its predicates:
https://github.com/llvm/llvm-project/blob/8e6630391699116641cf390a10476295b7d4b95c/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp#L3036-L3062
Then llvm will match `vsplat_imm_eq_1` for any v4i32 splats and cause a
miscompilation:
```
PATTERN: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vk))
RESULT: (VBITREV_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vj, v4i32:{ *:[v4i32] }:$vk)
```
This patch adds additional checks for predicates associated with the
trivial bitconvert node. Unused patterns in the LoongArch target are
also removed.
Fixes https://github.com/llvm/llvm-project/issues/116008.
Commit: 681939e1545193b428a5f59175017c1c3741ea32
https://github.com/llvm/llvm-project/commit/681939e1545193b428a5f59175017c1c3741ea32
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
Log Message:
-----------
[LAA] Add phi test variant for cross-iteration dependence (NFC)
Commit: 4728ac750295af12ba484ef4b7df4f7c4893eb4c
https://github.com/llvm/llvm-project/commit/4728ac750295af12ba484ef4b7df4f7c4893eb4c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/COFF/DLL.cpp
Log Message:
-----------
[LLD][COFF][NFC] Always align null chunks (#116677)
Currently, null chunks always follow other aligned chunks, so this patch
is NFC. However, it will become observable once support for ARM64X
imports is added. The import tables are shared between the native and EC
views. They are usually very similar, but in cases where they differ,
ARM64X relocations handle the discrepancies. If a DLL is only imported
by EC code, the native view will see it as importing zero functions from
this DLL (with ARM64X relocations replacing those null chunks with
actual imports). In this scenario, the null chunks may appear as the
very first chunks, meaning there is nothing else forcing their
alignment.
Commit: ee4fb3a8761b0abe231a8fdc127cd668cd9478f7
https://github.com/llvm/llvm-project/commit/ee4fb3a8761b0abe231a8fdc127cd668cd9478f7
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[llvm][docs] Correct setence in How To Add A Builder
Looks like a few different phrasings got mashed up together.
Commit: a8744066e9ef252b687c1206ccbd1a6e3ae1c890
https://github.com/llvm/llvm-project/commit/a8744066e9ef252b687c1206ccbd1a6e3ae1c890
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/include/clang/Frontend/FrontendAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/Interpreter/PartialTranslationUnit.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/Interpreter.cpp
Log Message:
-----------
[clang-repl] Include consistency using the default clang actions. (#116610)
This patch improves the code reuse of the actions system and adds
several improvements for easier debugging via clang-repl
--debug-only=clang-repl.
The change inimproves the consistency of the TUKind when actions are
handled within a WrapperFrontendAction. In this case instead of falling
back to default TU_Complete, we forward to the TUKind of the ASTContext
which presumably was created by the intended action. This enables the
incremental infrastructure to reuse code.
This patch also clones the first llvm::Module because the first PTU now
can come from -include A.h and the presumption of llvm::Module being
empty does not hold. The changes are a first step to fix the issues with
`clang-repl --cuda`.
Commit: edf56f1fa27dce36c2b537290c26fec1af1a1140
https://github.com/llvm/llvm-project/commit/edf56f1fa27dce36c2b537290c26fec1af1a1140
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
A llvm/test/Transforms/LoopInterchange/call-instructions-remarks.ll
M llvm/test/Transforms/LoopInterchange/call-instructions.ll
A llvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar-remark.ll
M llvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
M llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
M llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
M llvm/test/Transforms/LoopInterchange/interchange-no-deps.ll
M llvm/test/Transforms/LoopInterchange/interchanged-loop-nest-3.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-dependencies-1.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-loop-nest-3.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-tightly-nested.ll
Log Message:
-----------
[LoopInterchange] Don't rely on ASSERTS build for tests. NFC. (#116780)
A lot of interchange tests unnecessary relied on a build with ASSERTS
enabled. Instead, simply check the IR output for both negative and
positive tests so that we don't rely on debug messages. This increases
test coverage as these tests will now also run with non-assert builds.
For a couple of files keeping some of the debug tests was useful, so
separated out them out and moved them to a similarly named *-remarks.ll
file.
Commit: f69646e51c61a6f3b7e1bc5c1df7d720026edfde
https://github.com/llvm/llvm-project/commit/f69646e51c61a6f3b7e1bc5c1df7d720026edfde
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.td
Log Message:
-----------
[XCore] Pattern match LADD/LSUB/LMUL/MACCU/MACCS/CRC8 (#116245)
Commit: bdf00e2216280edef1ec91ccc07987db92197b59
https://github.com/llvm/llvm-project/commit/bdf00e2216280edef1ec91ccc07987db92197b59
Author: Yadong Chen <cyd.matt at qq.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir
M mlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/Dialect/SPIRV/IR/structure-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/abi-load-store.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
M mlir/test/Dialect/SPIRV/Transforms/layout-decoration.mlir
M mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
M mlir/test/Target/SPIRV/array-two-step-roundtrip.mlir
M mlir/test/Target/SPIRV/array.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/global-variable.mlir
M mlir/test/Target/SPIRV/loop.mlir
M mlir/test/Target/SPIRV/matrix.mlir
M mlir/test/Target/SPIRV/memory-ops.mlir
M mlir/test/Target/SPIRV/physical-storage-buffer.mlir
M mlir/test/Target/SPIRV/undef.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define AccessChainOp assembly (#116545)
see #73359
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.
Changes:
- updates the AccessChainOp defined in SPIRVMemoryOps.td to use
assemblyFormat.
- Removes part print/parse from MemoryOps.cpp which is now generated by
assemblyFormat
- Updates tests to updated format
Commit: 03d8831fa8ef5b7e32172c718b550a454645faea
https://github.com/llvm/llvm-project/commit/03d8831fa8ef5b7e32172c718b550a454645faea
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/test/Transforms/InstCombine/ptrmask.ll
Log Message:
-----------
[InstCombine] Handle constant GEP expr in `SimplifyDemandedUseBits` (#116794)
Closes https://github.com/llvm/llvm-project/issues/116775.
Commit: abac5be673a2053cceab8ce25009722e45021b9f
https://github.com/llvm/llvm-project/commit/abac5be673a2053cceab8ce25009722e45021b9f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
Log Message:
-----------
[InstCombine] Fix APInt ctor assertion
The (extended) bit width might not fit into the (non-extended)
type, resulting in an incorrect truncation of the compared value.
Fix this by using m_SpecificInt(), which is both simpler and
handles this correctly.
Fixes the assertion failure reported in:
https://github.com/llvm/llvm-project/pull/114539#issuecomment-2485799395
Commit: 26a89d2d0d73bc1ea4869c3409ce15059e4cae8e
https://github.com/llvm/llvm-project/commit/26a89d2d0d73bc1ea4869c3409ce15059e4cae8e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Make access.group metadata tags distinct in test.
Make access.group metadata tags used in b56e03fccd distinct.
Commit: af41c55673ab4342310f19bd2ef506803e9dc91c
https://github.com/llvm/llvm-project/commit/af41c55673ab4342310f19bd2ef506803e9dc91c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/CompilationInterfaces.h
M mlir/include/mlir/Target/LLVM/ModuleToObject.h
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Target/LLVM/ModuleToObject.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/unittests/Target/LLVM/SerializeNVVMTarget.cpp
Log Message:
-----------
Revert "[MLIR] Add callback functions for ModuleToObject" (#116811)
Reverts llvm/llvm-project#116007
Bot is broken.
Commit: 27dcae53eb9ea7b4d722d650e63567ca54e12d7d
https://github.com/llvm/llvm-project/commit/27dcae53eb9ea7b4d722d650e63567ca54e12d7d
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
A lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
Log Message:
-----------
[lldb] Convert file address to load address when reading memory for DW_OP_piece (#116411)
When parsing an optimized value and reading a piece from a file address,
LLDB tries to read the data from memory using that address.
This patch converts file address to load address before reading the
memory.
Fixes #111313
Fixes #97484
Commit: aff98e4be05a1060e489ce62a88ee0ff365e571a
https://github.com/llvm/llvm-project/commit/aff98e4be05a1060e489ce62a88ee0ff365e571a
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMScheduleM7.td
M llvm/lib/Target/ARM/ARMScheduleM85.td
M llvm/test/CodeGen/ARM/urem-seteq-illegal-types.ll
Log Message:
-----------
[ARM] Stop gluing 1-bit shifts (#116547)
1. When two (or more) nodes are glued, DAG scheduler will always
schedule them as one piece, i.e. it will not allow any instructions to
be scheduled between them. It does so because if nodes are glued this
usually means that there is an implicit register dependency between
them, and an intervening node could clobber this physical register. When
emitting such nodes into machine IR, they will also be stuck together,
e.g.:
```
%9:gpr = MOVsrl_glue killed %8, implicit-def $cpsr
%10:gpr = RRX %3, implicit $cpsr
```
2. If a node has Glue result, SelectionDAG will not try to CSE this
node. If it did, it would break the implicit physical register
dependency. In practice this means that if a node with Glue result has
multiple uses, it has to be duplicated before each use. This the reason
for `ARMTargetLowering::duplicateCmp` to exist.
When using normal data dependency, dependent nodes can freely be
scheduled around. If there is a physical register dependency between
nodes, the physical register will be copied to/from a virtual register,
allowing other nodes to intervene between them. The resulting machine IR
might look like this:
```
%9:gpr = LSRs1 killed %8, implicit-def $cpsr
%10:gpr = COPY $cpsr
%11:gpr = ORRrsi killed %9, %3, 242, 14 /* CC::al */, $noreg, $noreg
%12:gpr = BICri killed %11, -2147483648, 14 /* CC::al */, $noreg, $noreg
$cpsr = COPY %10
%13:gpr = RRX %3, implicit $cpsr
```
The two copies are likely to be eliminated by register coalescer, given
that there are no instructions between them that clobber this physical
register. If the copies are unwanted in the first place (they could be
expensive or impossible), DAG scheduler will try to avoid inserting them
wherever possible, and the resulting machine IR will look like this:
```
%9:gpr = LSRs1 killed %8, implicit-def $cpsr
%10:gpr = ORRrsi killed %9, %3, 242, 14 /* CC::al */, $noreg, $noreg
%11:gpr = BICri killed %10, -2147483648, 14 /* CC::al */, $noreg, $noreg
%12:gpr = RRX %3, implicit $cpsr
```
On ARM, arithmetic operations and LSLS already use the new data flow
approach. This patch extends it to include 1-bit shifts.
Pull Request: https://github.com/llvm/llvm-project/pull/116547
Commit: 8e4423eb0888e5fe381a23ec1fa6969f2d096ed1
https://github.com/llvm/llvm-project/commit/8e4423eb0888e5fe381a23ec1fa6969f2d096ed1
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
A llvm/test/CodeGen/PowerPC/global-merge-aix-sections.ll
Log Message:
-----------
[AsmPrinter] Fix handling in emitGlobalConstantImpl for AIX (#116255)
When GlobalMerge creates a MergedGlobal of statics all initialized to
zero, emitGlobalConstantImpl sees a ConstantAggregateZero. This results
in just emitting zeros followed by labels for the aliases. We need to
handle it more like how emitGlobalConstantStruct does by emitting each
global inside the aggregate.
---------
Co-authored-by: Hubert Tong <hubert.reinterpretcast at gmail.com>
Commit: b0afa6bab9581abc91f23c854b3bb45095cbb057
https://github.com/llvm/llvm-project/commit/b0afa6bab9581abc91f23c854b3bb45095cbb057
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[clang] Change some placeholders from undef to poison [NFC]
Commit: 64e3466fd09ec0b02f27ec15a176611fe65ed961
https://github.com/llvm/llvm-project/commit/64e3466fd09ec0b02f27ec15a176611fe65ed961
Author: Alexey Karyakin <akaryaki at quicinc.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
M lld/test/ELF/hexagon-jump-error.s
M lld/test/ELF/hexagon.s
Log Message:
-----------
[lld][Hexagon] Fix R_HEX_B22_PCREL range checks (#115925)
Range checks for R_HEX_B22_PCREL did not account for the fact that
offset is measured in instructions, not bytes.
Add a test for all range-checked relocations.
Commit: de6d1683d4163a384ce529bf9bd70bb9bcd16a41
https://github.com/llvm/llvm-project/commit/de6d1683d4163a384ce529bf9bd70bb9bcd16a41
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
R lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-O3.c
Log Message:
-----------
Revert "[lldb] Convert file address to load address when reading memory for DW_OP_piece" (#116824)
Reverts llvm/llvm-project#116411
Commit: 21fc36bb193740a4e79e22a8d04fea09d394d27c
https://github.com/llvm/llvm-project/commit/21fc36bb193740a4e79e22a8d04fea09d394d27c
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
Log Message:
-----------
Revert "[FunctionAttrs] Add the "initializes" attribute inference" (#116825)
Reverts llvm/llvm-project#97373
clang tests fail
Commit: b3995aa338a2837626d31ae8fffc340d95b888ca
https://github.com/llvm/llvm-project/commit/b3995aa338a2837626d31ae8fffc340d95b888ca
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-cse.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
Log Message:
-----------
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
In graphics shaders it is better overall to use NSA encoding for IMAGE
instructions, because the benefit of less constrained register
allocation outweighs the cost of larger encoding. In particular NSA form
often avoids the need for extra V_MOV_B32 instructions between IMAGE
instructions, which can allow the IMAGE instructions to be claused.
Note that in GFX12 there is no longer a bit in the encoding to choose
between NSA and non-NSA forms, so this only affects GFX10 and GFX11.
Commit: 03506bc0a99fd53d0f4e3d0bd77eb2f7bad96102
https://github.com/llvm/llvm-project/commit/03506bc0a99fd53d0f4e3d0bd77eb2f7bad96102
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/TextAPI/InterfaceFile.cpp
M llvm/unittests/TextAPI/TextStubV5Tests.cpp
Log Message:
-----------
[TextAPI] Add missing attribute to remove/merge/extract operations (#116729)
Commit: 48591953e97b9ecf32e60fe0233ca0ba2765184e
https://github.com/llvm/llvm-project/commit/48591953e97b9ecf32e60fe0233ca0ba2765184e
Author: Kai Luo <gluokai at gmail.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
A llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s
Log Message:
-----------
[Thumb2][ARMAsmParser] Fix processing of `t2{LDR,STR}{*}_{PRE,POST}_imm` when changing to its concrete form (#116757)
`t2{LDR,STR}{*}_{PRE,POST}_imm` is pseudo instruction and is expected to
be `t2{LDR,STR}{*}_{PRE,POST}`. During building the new MCInst of
`t2{LDR,STR}{*}_{PRE,POST}`, the order of operands looks incorrect.
Fixes https://github.com/llvm/llvm-project/issues/97020.
---------
Co-authored-by: Kai Luo <luokai at vivo.com>
Commit: 30fad6a97611ac397bdaa429730851f53752d013
https://github.com/llvm/llvm-project/commit/30fad6a97611ac397bdaa429730851f53752d013
Author: Aaron Puchert <aaron.puchert at sap.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ThreadSafetyAnalysis.rst
Log Message:
-----------
Thread safety analysis: Implement MutexLocker factory functions in documentation
We skipped adding definitions in 54bfd0484615 because we'd emit false
positive warnings on the closing braces. But these have been fixed in
commit e64ef634bbd9.
Commit: 0d9dc421143a0acd414a23f343b555c965a471f1
https://github.com/llvm/llvm-project/commit/0d9dc421143a0acd414a23f343b555c965a471f1
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/test/CAPI/execution_engine.c
M mlir/test/mlir-cpu-runner/simple.mlir
M mlir/unittests/ExecutionEngine/Invoke.cpp
Log Message:
-----------
[MLIR] Add SystemZ arg extensions for some tests (#116314)
The SystemZ ABI requires that i32 values should be extended when passed
between functions.
This patch fixes some tests that were lacking this, either by adding
some SystemZ specific inlinings of test functions or by disabling the
verification of this with the CL option controlling this.
Fixes #115564
Commit: d37554b69b414ee00eacfd35eaa2e051b1ade2d7
https://github.com/llvm/llvm-project/commit/d37554b69b414ee00eacfd35eaa2e051b1ade2d7
Author: Benson Chu <bensonchu457 at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
Log Message:
-----------
[ARM] Specifically delineate between different GPRCS2 positions
Currently, the relative position of GPRCS2 (with respect to other
instructions in the prologue of a function) can be different depending
on the type of ARMSubtarget::PushPopSplitVariant.
When the PushPopSpiltVariant is SplitR11WindowsSEH, GPRCS2 comes
after both GPRCS1 and DPRCS2:
GPRCS1
DPRCS1
GPRCS2
However, in all other cases, GPRCS2 comes before DPRCS1, like so:
GPRCS1
GPRCS2
DPRCS1
This makes the MI walking code in ARMFrameLowering::emitPrologue a bit
confusing. If GPRCS2Size is non-zero, we also have to check the
PushPopSplitVariant to know if we will encounter the DPRCS1 push
instruction first or the GPRCS2 push instruction first.
This commit changes to SplitR11WindowsSEH such that the spill area is
as follows:
GPRCS1
DPRCS1
GPRCS3
This disambiguates a lot of the ARMFrameLowering.cpp MI traversal
code.
Commit: 1bfcf89107349b03ac8ab113387ced0deef4fc4c
https://github.com/llvm/llvm-project/commit/1bfcf89107349b03ac8ab113387ced0deef4fc4c
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] port a8744066e9ef252b687c1206ccbd1a6e3ae1c890
Commit: 8b2dff960d9d987c583c3a6d5729f01d101dc401
https://github.com/llvm/llvm-project/commit/8b2dff960d9d987c583c3a6d5729f01d101dc401
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Utility/DiagnosticsRendering.cpp
M lldb/unittests/Utility/DiagnosticsRenderingTest.cpp
Log Message:
-----------
[lldb] Fix a positioning bug in diagnostics output (#116711)
The old code did not take the indentation into account.
Commit: 3e552ed58980d240993d7e937dd38c404c03ed66
https://github.com/llvm/llvm-project/commit/3e552ed58980d240993d7e937dd38c404c03ed66
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
Add release notes for LLDB inline diagnostics (#116841)
Commit: 6b4f67545d87d5305cbbc20a678fb97ede995579
https://github.com/llvm/llvm-project/commit/6b4f67545d87d5305cbbc20a678fb97ede995579
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Utility/DiagnosticsRendering.cpp
M lldb/unittests/Utility/DiagnosticsRenderingTest.cpp
Log Message:
-----------
[lldb] Improve rendering of inline diagnostics on the same column (#116727)
depends on https://github.com/llvm/llvm-project/pull/116711
[lldb] Improve rendering of inline diagnostics on the same column by
fixing the indentation and printing these annotations in the original
order.
Before
a+b+c;
^ ^ ^
| | error: 3
| |note: 2b
| error: 2a
error: 1
After
a+b+c;
^ ^ ^
| | error: 3
| error: 2a
| note: 2b
error: 1
Commit: 0611a668d1389c8573e83eeafa6d5f6172c4cbc2
https://github.com/llvm/llvm-project/commit/0611a668d1389c8573e83eeafa6d5f6172c4cbc2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
Log Message:
-----------
[ARM] Fix a warning
This patch fixes:
llvm/lib/Target/ARM/ARMFrameLowering.cpp:1404:39: error: unused
variable 'PushPopSplit' [-Werror,-Wunused-variable]
Commit: 197e0125c3ed991f11d97d27e529c02af06e9f37
https://github.com/llvm/llvm-project/commit/197e0125c3ed991f11d97d27e529c02af06e9f37
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libc/src/__support/OSUtil/gpu/exit.cpp
M libc/src/__support/RPC/rpc.h
M libc/src/__support/RPC/rpc_util.h
M libc/src/stdio/gpu/vfprintf_utils.h
M libc/src/stdlib/gpu/abort.cpp
Log Message:
-----------
[libc] Replace usage of GPU helpers with ones from 'gpuintrin.h' (#116454)
Summary:
These are provided by a resource header now, cut these from the
dependencies and only provide the ones we use for RPC.
Commit: c84a99dfd391eb4d89aff8d6453016045098b444
https://github.com/llvm/llvm-project/commit/c84a99dfd391eb4d89aff8d6453016045098b444
Author: Michele Scandale <michele.scandale at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/InlineAdvisor.h
M llvm/unittests/Analysis/InlineAdvisorPlugin/InlineAdvisorPlugin.cpp
M llvm/unittests/Analysis/PluginInlineAdvisorAnalysisTest.cpp
Log Message:
-----------
[InlineAdvisor] Update documentation for `PluginInlineAdvisorAnalysis` (NFC). (#116715)
This commit updates the documentation for `PluginInlineAdvisorAnalysis`
based on the feedback in PR#114615 suggesting that
`registerAnalysisRegistrationCallback` should be the preferred method to
register the plugin inline advisor analysis.
Commit: def22f4e718daa74c2d0c03a32e32d4913a46278
https://github.com/llvm/llvm-project/commit/def22f4e718daa74c2d0c03a32e32d4913a46278
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libc/src/__support/RPC/rpc.h
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/RPC/rpc_util.h
Log Message:
-----------
[libc] Pull last dependencies into rpc_util.h (#116693)
Summary:
Last bit in-place to remove the dependencies on LLVM libc headers. This
just pulls the `sleep_briefly`, `std::optinal` and `type_traits`
definitions into the
`rpc_util.h` header. This duplicates some code for now but will soon be
moved into the `include/rpc` directory. At that point I will remove all
the `LIBC_INLINE` and just make it `RPC_INLINE`. Internal use will then
have a wrapper to make it all LIBC namespaced, implementations will then
implement their own handling.
Commit: 39e65b87066f6de43b1c57ff08cb6ce95219ce15
https://github.com/llvm/llvm-project/commit/39e65b87066f6de43b1c57ff08cb6ce95219ce15
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
Log Message:
-----------
[llvm-mca][x86] Add AVX512 VMOVNTDQA instruction test coverage
Commit: 8bdf13b11638d2f3e6792a573fc2be830a03790a
https://github.com/llvm/llvm-project/commit/8bdf13b11638d2f3e6792a573fc2be830a03790a
Author: apple-fcloutier <75502309+apple-fcloutier at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Parse/ParseObjc.cpp
A clang/test/SemaObjC/method-param-named-id.m
Log Message:
-----------
[ObjC] Name lookup in methods shouldn't allow shadowing types (#116683)
Arguably as a bug, Clang has previously not mixed up Objective-C
parameter names with types. This allows developers to write parameter
names that _should_ shadow type names, but don't. For instance:
@interface Foo
-(void)foo:(int)id bar:(id)name; // OK
@end
Commit 97788089988a2ace63d717cadbcfe3443f380f9c changed the way that
parameters are parsed to bring it more in line with how C parameters are
parsed, but it breaks the example above. Given an expectation that the
change wouldn't introduce source breaks, this is not something we can go
forward with.
97788089988a2ace63d717cadbcfe3443f380f9c did this so that late-parsed
attributes could reference Objective-C parameters. This change buffers
Objective-C parameter info until after all parameters are parsed and
turns them into parameter declarations before realizing late-parsed
attributes instead.
Radar-ID: 139996306
Commit: 2186a008c98e8bb6738fe9120441d6bd15c272f3
https://github.com/llvm/llvm-project/commit/2186a008c98e8bb6738fe9120441d6bd15c272f3
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
Log Message:
-----------
[HLSL] Fix placement of `const` for resource operator[] (#116698)
We had an incorrect AST here - We want `const T &`, not `T &const`.
Commit: b28eebf9264a6b6843b15d4e17be70604f3e4ad8
https://github.com/llvm/llvm-project/commit/b28eebf9264a6b6843b15d4e17be70604f3e4ad8
Author: Yashas Andaluri <quic_yandalur at quicinc.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/RDFGraph.cpp
A llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir
Log Message:
-----------
[RDF] Fix cover check when linking refs to defs (#113888)
During RDF graph construction, linkRefUp method links a register ref to
its upward reaching defs until all RegUnits of the ref have been covered
by defs.
However, when a sub-register def covers some, but not all, of the
RegUnits of a previous super-register def, a super-register ref is not
linked to the super-register def.
This can result in certain super register defs being dead code
eliminated.
This patch fixes the cover check for a register ref. A def must be
skipped only when all RegUnits of that def have already been covered by
a previously seen def.
Commit: dd78d7c7be5b8948cf5841e8033e59adebf230ad
https://github.com/llvm/llvm-project/commit/dd78d7c7be5b8948cf5841e8033e59adebf230ad
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/Editline.h
M lldb/source/Host/common/Editline.cpp
A lldb/test/API/terminal/TestEditlineCompletions.py
Log Message:
-----------
[lldb] Improve editline completion formatting (#116456)
This patch improves the formatting of editline completions. The current
implementation is naive and doesn't account for the terminal width.
Concretely, the old implementation suffered from the following issues:
- We would unconditionally pad to the longest completion. If that
completion exceeds the width of the terminal, that would result in a lot
of superfluous white space and line wrapping.
- When printing the description, we wouldn't account for the presence of
newlines, and they would continue without leading padding.
The new code accounts for both. If the completion exceeds the available
terminal width, we show what fits on the current lined followed by
ellipsis. We also no longer pad beyond the length of the current line.
Finally, we print the description line by line, with the proper leading
padding. If a line of the description exceeds the available terminal
width, we print ellipsis and won't print the next line.
Before:
```
Available completions:
_regexp-attach -- Attach to process by ID or name.
_regexp-break -- Set a breakpoint using one of several shorthand
formats.
_regexp-bt -- Show backtrace of the current thread's call sta
ck. Any numeric argument displays at most that many frames. The argument 'al
l' displays all threads. Use 'settings set frame-format' to customize the pr
inting of individual frames and 'settings set thread-format' to customize th
e thread header. Frame recognizers may filter thelist. Use 'thread backtrace
-u (--unfiltered)' to see them all.
_regexp-display -- Evaluate an expression at every stop (see 'help
target stop-hook'.)
```
After:
```
Available completions:
_regexp-attach -- Attach to process by ID or name.
_regexp-break -- Set a breakpoint using one of several shorth...
_regexp-bt -- Show backtrace of the current thread's call ...
_regexp-display -- Evaluate an expression at every stop (see 'h...
```
rdar://135818198
Commit: 61057b0f6fa8975c2ebc20ed339d59d28bbc6b03
https://github.com/llvm/llvm-project/commit/61057b0f6fa8975c2ebc20ed339d59d28bbc6b03
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/docs/use/links.rst
Log Message:
-----------
[lldb/www] Garbage collect old videos and add new ones (#116838)
Fixes #66476
Commit: 68b7ab127f580bdc422c0dde4bfcd4a2daaeb630
https://github.com/llvm/llvm-project/commit/68b7ab127f580bdc422c0dde4bfcd4a2daaeb630
Author: ddubov100 <155631080+ddubov100 at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Interfaces/TilingInterface.td
Log Message:
-----------
[MLIR] Fully qualify entities in the ::mlir namespace in TilingInterface.td. (#116765)
Adding mlir namespace to TilingInterface.td.
Otherwise it can't be used with dialects not nested under the mlir
namespace.
Commit: d8a1c6d72739c99f4b52a84e907b96b685b44c5e
https://github.com/llvm/llvm-project/commit/d8a1c6d72739c99f4b52a84e907b96b685b44c5e
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/test/Parser/cxx2c-delete-with-message.cpp
Log Message:
-----------
[Clang] update reasoned delete diagnostic kind to use Extension, making it pedantic only (#114713)
Fixes #109311
---
https://github.com/llvm/llvm-project/issues/109311#issuecomment-2422963686
Commit: 79682c4d57620e623fb30271cc8003d0c9e14a01
https://github.com/llvm/llvm-project/commit/79682c4d57620e623fb30271cc8003d0c9e14a01
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
Log Message:
-----------
[SLP]Check if the buildvector root is not a part of the graph before deletion
If the buildvector root has no uses, it might be still needed as a part
of the graph, so need to check that it is not a part of the graph before
deletion.
Fixes #116852
Commit: eff60d83b0533954eda153fbbabb3e99d46bde94
https://github.com/llvm/llvm-project/commit/eff60d83b0533954eda153fbbabb3e99d46bde94
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
Log Message:
-----------
[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.
This addresses some failures I've seen in testing on real code.
Commit: ca79e126482084fe4681dd777fdd2948d4e7c81b
https://github.com/llvm/llvm-project/commit/ca79e126482084fe4681dd777fdd2948d4e7c81b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Handle implicit global in cuf kernel and nested statement (#116846)
Update the implicit global detection by looking for them in the CUF
kernel and also update to a walk so nested `fir.address_of` in nested
statement are also accounted for.
Commit: 565a9ac7df3815ed038938942be4cf1471de4755
https://github.com/llvm/llvm-project/commit/565a9ac7df3815ed038938942be4cf1471de4755
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
Log Message:
-----------
[SPIR-V] Disable Machine Sink pass in SPIR-V Backend (#116060)
Some standard passes that optimize machine instructions in SSA form uses
MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
break the CFG. MachineSink is among such passes (see for example
https://github.com/llvm/llvm-project/blob/1884ffc41c20b1e08b30eef4e8ebbcc54543a139/llvm/lib/CodeGen/MachineSink.cpp#L630),
so this PR disables the pass to ensure correctness of the generated
code.
There is a reproducer of the issue that demonstrates how MachineSink is
able to generate an invalid code for the SPIR-V Backend
```
error: line 6837: OpPhi must appear within a non-entry block before all non-OpPhi instructions (except for OpLine, which can be mixed with OpPhi).
%z_fra_3_1 = OpPhi %uint %and187 %4250 %inc194 %4257 %uint_0 %4264
```
The reproducer is a part of SYCL end-to-end test suite
(https://github.com/intel/llvm/blob/sycl/sycl/test-e2e/DeviceLib/imf_fp32_rounding_test.cpp).
At the moment it doesn't seem feasible to make it a part of the SPIR-V
Backend test suite due to a far too big size of the intermediate LLVM IR
that causes the problem.
Commit: 996553228f8b2f3219451a2514bd6f9380f13e28
https://github.com/llvm/llvm-project/commit/996553228f8b2f3219451a2514bd6f9380f13e28
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/BinarySection.h
M bolt/lib/Core/BinarySection.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/eh-frame-overwrite.test
Log Message:
-----------
[BOLT] Overwrite .eh_frame and .gcc_except_table (#116755)
Under --use-old-text or --strict, we completely rewrite contents of EH
frames and exception tables sections. If new contents of either section
do not exceed the size of the original section, rewrite the section
in-place.
Commit: 5681f756c058204d7e41d065f91c5f3c36a434a7
https://github.com/llvm/llvm-project/commit/5681f756c058204d7e41d065f91c5f3c36a434a7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/docs/use/links.rst
Log Message:
-----------
Fix broken link
Commit: 5b79152937722a5b80c92146b7c2453401739d5f
https://github.com/llvm/llvm-project/commit/5b79152937722a5b80c92146b7c2453401739d5f
Author: David Green <david.green at arm.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/phi.ll
Log Message:
-----------
[AArch64] Make sure there is test coverage for ptr phis. NFC
Commit: 174899f738b31216750ac59562475966b0b0be42
https://github.com/llvm/llvm-project/commit/174899f738b31216750ac59562475966b0b0be42
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Utility/DiagnosticsRendering.cpp
Log Message:
-----------
[lldb] Refactor helper by using iterators and in-place edits (NFC) (#116876)
Based on post-commit review feedback by Felipe Piovezan!
Commit: df13acf344a4233777789d0052b3d09bec6a5180
https://github.com/llvm/llvm-project/commit/df13acf344a4233777789d0052b3d09bec6a5180
Author: Alexander Shaposhnikov <ashaposhnikov at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
A clang/test/SemaCUDA/spirv-attrs.cu
Log Message:
-----------
[CudaSPIRV] Add support for optional spir-v attributes (#116589)
Add support for optional spir-v attributes.
Test plan:
ninja check-all
Commit: 27046bad9751e85ba79db9248ff1f36e9d4d19eb
https://github.com/llvm/llvm-project/commit/27046bad9751e85ba79db9248ff1f36e9d4d19eb
Author: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
Log Message:
-----------
[mlir][XeGPU] Add a builder for xegpu.create_nd_tdesc op. (#116472)
The builder is needed to support dynamic meref as source operand in
xegpu.create_nd_tdesc op.
Commit: 47ef5c4b7f85bc1c8a859d721db9fd1dde7b8d8e
https://github.com/llvm/llvm-project/commit/47ef5c4b7f85bc1c8a859d721db9fd1dde7b8d8e
Author: annuasd <97934297+annuasd at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/lib/Bindings/Python/DialectQuant.cpp
M mlir/python/mlir/_mlir_libs/_mlir/dialects/quant.pyi
M mlir/test/python/dialects/quant.py
Log Message:
-----------
[mlir][Bindings] Fix missing return value of functions and incorrect type hint in pyi. (#116731)
The zero points of UniformQuantizedPerAxisType should be List[int].
And there are two methods missing return value.
Co-authored-by: 牛奕博 <niuyibo at niuyibodeMacBook-Pro.local>
Commit: e3ff649abe975c04aa179622c6f4757e7aa66aaf
https://github.com/llvm/llvm-project/commit/e3ff649abe975c04aa179622c6f4757e7aa66aaf
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Target/Thread.cpp
Log Message:
-----------
[lldb] Fix comment in ~Thread (NFC) (#116850)
Commit: 1073e9049bb2483a6ff554cbc5da1c2fd0b9d75d
https://github.com/llvm/llvm-project/commit/1073e9049bb2483a6ff554cbc5da1c2fd0b9d75d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
AMDGPU: Clean up more real instruction predicate overrides (#116868)
In general real instructions should not have manually specified
predicates.
Commit: 1c1fbf51b5ec9657e5da7fa94ee892273255544a
https://github.com/llvm/llvm-project/commit/1c1fbf51b5ec9657e5da7fa94ee892273255544a
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/test/wasm/tls-non-shared-memory.s
M lld/wasm/Symbols.cpp
M lld/wasm/Symbols.h
M lld/wasm/SyntheticSections.cpp
Log Message:
-----------
[lld][WebAssembly] Fix TLS-relative relocations when linking without shared memory (#116136)
TLS-relative relocations always need to be relative the TLS section
since they get added to `__tls_base` at runtime.
Without this change the tls base address was effectively being added to
the final value twice in this case.
This only effects code the is built with `-pthread` but linked without
shared memory (i.e. without threads).
Fixes: https://github.com/emscripten-core/emscripten/issues/22880
Commit: 076513646cfd922b42ea0e87e2f07397a3ff41a4
https://github.com/llvm/llvm-project/commit/076513646cfd922b42ea0e87e2f07397a3ff41a4
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/InstCombine/intersect-accessgroup.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
Log Message:
-----------
[Local] Only intersect llvm.access.group metadata if instr moves. (#115868)
Preserve llvm.access.group metadata on the replacement instruction, if
it does not move. In that case, the program would be UB, if the parallel
property encoded in the metadata does not hold.
This matches the LangRef recently updated in #116220
PR https://github.com/llvm/llvm-project/pull/115868
Commit: 4d7df40c084d9c551761027f873a59ac83cb398d
https://github.com/llvm/llvm-project/commit/4d7df40c084d9c551761027f873a59ac83cb398d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Materialize constant src in memory (#116851)
When the src of the data transfer is a constant, it needs to be
materialized in memory to be able to perform a data transfer.
```
subroutine sub1()
real, device :: a(10)
integer :: I
do i = 5, 10
a(i) = -4.0
end do
end
```
Commit: 41c86ca714a68eea8c73cf57fba28718d466660b
https://github.com/llvm/llvm-project/commit/41c86ca714a68eea8c73cf57fba28718d466660b
Author: Petr Penzin <penzin.dev at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add TT-Ascalon-d8 processor (#115100)
Ascalon is an out-of-order CPU core from Tenstorrent. Overview:
https://tenstorrent.com/ip/tt-ascalon
Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be
added in a separate PR.
---------
Co-authored-by: Anton Blanchard <antonb at tenstorrent.com>
Commit: 012dd8be4b5a4c00deb22345c630990f160b3aa3
https://github.com/llvm/llvm-project/commit/012dd8be4b5a4c00deb22345c630990f160b3aa3
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/CMakeLists.txt
Log Message:
-----------
[libcxx] Passthrough the necessary CMake variables to benchmarks (#116644)
This addresses the issue uncovered by #115361. Previously, we weren't
building benchmarks in many cases due to the following block:
https://github.com/llvm/llvm-project/blob/e58949632e91477af58d983f3b66369e6a2c8233/libcxx/CMakeLists.txt#L162-L172
We need to passthrough the necessary variables into the benchmarks
subbuild and use correct syntax.
Commit: 7c41b5ccdcf0f5de1b9b254693635283faff3658
https://github.com/llvm/llvm-project/commit/7c41b5ccdcf0f5de1b9b254693635283faff3658
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.h
A compiler-rt/test/rtsan/report_error_summary.cpp
Log Message:
-----------
[rtsan] Add support for ReportErrorSummary (#116424)
Adding support for the extra SUMMARY line that is output by most
compilers. This also adds the ability for end-users to specify their own
handlers for reporting these errors (see the test).
Commit: 3c8818cf2deaa050817ecec1c99cf939295feced
https://github.com/llvm/llvm-project/commit/3c8818cf2deaa050817ecec1c99cf939295feced
Author: Chris Apple <cja-private at pm.me>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Log Message:
-----------
[rtsan] Add more file descriptor interceptors - dup*, lseek (#116853)
# Why we think these are real-time unsafe
They correspond directly to system calls in linux and OSX, they are
manipulating a shared resource, which likely takes some operating-system
synchronization.
Commit: 944478dd62a78f6bb43d4da210643affcc4584b6
https://github.com/llvm/llvm-project/commit/944478dd62a78f6bb43d4da210643affcc4584b6
Author: Aaron Puchert <aaronpuchert at alice-dsl.net>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
A clang/tools/clang-shlib/simple_version_script.map.in
M llvm/CMakeLists.txt
Log Message:
-----------
Introduce symbol versioning for clang-cpp (#116556)
The situation that required symbol versions on the LLVM shared library
can also happen for clang-cpp, although it is less common: different
tools require different versions of the library, and through transitive
dependencies a process ends up with multiple copies of clang-cpp. This
causes havoc with ELF, because calls meant to go one version of the
library end up with another.
I've also considered introducing a symbol version globally, but for
example the clang (C) library and other targets outside of LLVM/Clang,
e.g. libc++, would not want that. So it's probably best if we keep it to
those libraries.
Commit: 3a63407686313f46f9abc664fd10b01f4359ee27
https://github.com/llvm/llvm-project/commit/3a63407686313f46f9abc664fd10b01f4359ee27
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__atomic/atomic.h
R libcxx/include/__atomic/atomic_base.h
M libcxx/include/atomic
M libcxx/include/barrier
M libcxx/include/latch
M libcxx/include/module.modulemap
M libcxx/include/semaphore
M libcxx/src/barrier.cpp
Log Message:
-----------
[libc++] Make __atomic_base into an implementation detail of std::atomic (#115764)
The __atomic_base base class is only useful to conditionalize the
operations we provide inside std::atomic. It shouldn't be used directly
from other places in the library which can use std::atomic directly
instead.
Since we've granularized our includes, using std::atomic directly should
not make much of a difference compile-time wise.
This patch starts using std::atomic directly from other classes like
std::barrier and std::latch. Changing this shouldn't be an ABI break
since both classes have the same size and layout.
The benefits of this patch are isolating other parts of the code base
from implementation details of std::atomic and simplifying the mental
model for std::atomic's layers of implementation by making it clear that
__atomic_base is only an implementation detail of std::atomic.
Commit: d8bd7f11c8c781646406e76731dd8d76ed5425dd
https://github.com/llvm/llvm-project/commit/d8bd7f11c8c781646406e76731dd8d76ed5425dd
Author: Kyle Wang <ec1wng at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[mlir] Support ROCDL::ReadlaneOp (#116593)
Support ROCDL::ReadlaneOp to solve
https://github.com/ROCm/triton-internal/issues/411.
Commit: 581f755a2a22910da8a9a160c4ea5efeb43a40b4
https://github.com/llvm/llvm-project/commit/581f755a2a22910da8a9a160c4ea5efeb43a40b4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 3a6340768631
Commit: 21df32511b558b2c1e24fe23f677fffaad4da333
https://github.com/llvm/llvm-project/commit/21df32511b558b2c1e24fe23f677fffaad4da333
Author: Perry Gibson <Wheest at users.noreply.github.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/value.py
Log Message:
-----------
[mlir,python] Expose replaceAllUsesExcept to Python bindings (#115850)
Problem originally described in [the forums
here](https://discourse.llvm.org/t/mlir-python-expose-replaceallusesexcept/83068/1).
Using the MLIR Python bindings, the method
[`replaceAllUsesWith`](https://mlir.llvm.org/doxygen/classmlir_1_1Value.html#ac56b0fdb6246bcf7fa1805ba0eb71aa2)
for `Value` is exposed, e.g.,
```python
orig_value.replace_all_uses_with(
new_value
)
```
However, in my use-case I am separating a block into multiple blocks, so
thus want to exclude certain Operations from having their Values
replaced (since I want them to diverge).
Within Value, we have
[`replaceAllUsesExcept`](https://mlir.llvm.org/doxygen/classmlir_1_1Value.html#a9ec8d5c61f8a6aada4062f609372cce4),
where we can pass the Operations which should be skipped.
This is not currently exposed in the Python bindings: this PR fixes
this. Adds `replace_all_uses_except`, which works with individual
Operations, and lists of Operations.
Commit: d29a50f358e71a695b23e456d66ed2924617deb9
https://github.com/llvm/llvm-project/commit/d29a50f358e71a695b23e456d66ed2924617deb9
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lldb/source/Target/RegisterContextUnwind.cpp
Log Message:
-----------
Revert "[lldb] Allow fetching of RA register when above fault handler (#98566)"
This reverts commit fd424179dcb3417fc0675f77d2bf06c750dd1c33.
This patch has two problems. First, it is unnecessary, Pavel landed
a fix a week or so before mine which solves this problem in
bbd54e08b08f5ccd38c4665178e65c58f7b14459 . Second, the fix is
incorrect; for a function above a trap handler, where all registers
are available, this patch would have lldb fetch the return address
register from frame 0. This might be 10 frames up in the stack;
the frame 0 return address register is incorrect. The change would
have been correct a short bit later than this, but Pavel's fix is
executed earlier in the function and none of this is needed.
Commit: e72209db3586ee03f433fe30c3bfac6c9c4d9d6f
https://github.com/llvm/llvm-project/commit/e72209db3586ee03f433fe30c3bfac6c9c4d9d6f
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
Log Message:
-----------
[MachineSink] Fix stable sort comparator (#116705)
Fix the comparator in `stable_sort()` to satisfy the strict weak
ordering requirement.
In https://github.com/llvm/llvm-project/pull/115367 this comparator was
changed to use `getCycleDepth()` when `shouldOptimizeForSize()` is true.
However, I mistakenly changed to logic so that we use `LHSFreq <
RHSFreq` if **either** of them are zero. This causes us to fail the last
requirment (https://en.cppreference.com/w/cpp/named_req/Compare).
> if comp(a, b) == true and comp(b, c) == true then comp(a, c) == true
Commit: 73216cd71229fc7ccd380c334d45f809787f41b1
https://github.com/llvm/llvm-project/commit/73216cd71229fc7ccd380c334d45f809787f41b1
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
Log Message:
-----------
[flang] Rework CUDA kernel DO host array check (#116301)
Don't worry about derived type components unless they are pointers or
allocatables.
Commit: 300370c27b31ced572b957b6efdbb2bcee277392
https://github.com/llvm/llvm-project/commit/300370c27b31ced572b957b6efdbb2bcee277392
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-io.cpp
M flang/test/Semantics/io03.f90
M flang/test/Semantics/io04.f90
M flang/test/Semantics/undef-result01.f90
Log Message:
-----------
[flang] Catch I/O statement error (#116647)
Fortran doesn't have unformatted internal I/O, so catch attempts to use
internal units without a format or namelist specifier.
Fixes https://github.com/llvm/llvm-project/issues/116586.
Commit: d20f55fbd5786f056ff8417bddc7c47df6c7f90b
https://github.com/llvm/llvm-project/commit/d20f55fbd5786f056ff8417bddc7c47df6c7f90b
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/pointer02.f90
Log Message:
-----------
[flang] Silence bogus error on local proc pointer initializer (#116663)
A procedure pointer is allowed to be initialized with the subprogram in
which it is local, assuming that other requirements are satisfied.
Add a good test for local procedure pointer initialization, as no test
existed for the error message in question.
Fixes https://github.com/llvm/llvm-project/issues/116566.
Commit: a54e8b2cc45f079881ee8013143494e9a1315929
https://github.com/llvm/llvm-project/commit/a54e8b2cc45f079881ee8013143494e9a1315929
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/tools.cpp
A flang/test/Semantics/smp-def02.f90
Log Message:
-----------
[flang] Silence bogus error about insufficiently defined interfaces (#116694)
The interfaces of separate module procedures are sufficiently well
defined in a submodule to be used in a local generic interface; the
compiler just needed to work a little harder to find them.
Fixes https://github.com/llvm/llvm-project/issues/116567.
Commit: 6e4821487fcab23bf9ca7f7c667826956bee4d1b
https://github.com/llvm/llvm-project/commit/6e4821487fcab23bf9ca7f7c667826956bee4d1b
Author: vporpo <vporpodas at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
Log Message:
-----------
[SandboxVec][DAG] Register callback for erase instr (#116742)
This patch adds the callback registration logic in the DAG's constructor
and the corresponding deregistration logic in the destructor. It also
implements the code that makes sure that SchedBundle and DGNodes can be
safely destroyed in any order.
Commit: e394fecd5b351e9108d0600c872759d8dea88a42
https://github.com/llvm/llvm-project/commit/e394fecd5b351e9108d0600c872759d8dea88a42
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/docs/Bufferization.md
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/include/mlir/Dialect/Func/Transforms/Passes.td
M mlir/lib/Dialect/Func/Transforms/CMakeLists.txt
R mlir/lib/Dialect/Func/Transforms/FuncBufferize.cpp
R mlir/test/Dialect/Func/func-bufferize.mlir
M mlir/test/Dialect/Transform/test-pass-application.mlir
M mlir/test/Integration/Dialect/MemRef/verify-memref.mlir
Log Message:
-----------
[mlir][func] Remove `func-bufferize` pass (#114152)
The dialect conversion-based bufferization passes have been migrated to
One-Shot Bufferize about two years ago. To clean up the code base, this
commit removes the `func-bufferize` pass, one of the few remaining parts
of the old infrastructure. Most bufferization passes have already been
removed.
Note for LLVM integration: If you depend on this pass, migrate to
One-Shot Bufferize or copy the pass to your codebase.
Commit: 066dd91ad8c5d80bf7a301cd9d77aa8267cd4dcd
https://github.com/llvm/llvm-project/commit/066dd91ad8c5d80bf7a301cd9d77aa8267cd4dcd
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
Log Message:
-----------
[BOLT] Offset LPStart to avoid unnecessary instructions (#116713)
For C++ exception handling, when we write a call site table, we must
avoid emitting 0-value offsets for landing pads unless the call site has
no landing pad. However, 0 can be a real offset from the start of the
FDE if the FDE corresponds to a function fragment that starts with a
landing pad. In such cases, we used to emit a trap instruction at the
start of the fragment to guarantee non-zero LP offset.
To avoid emitting unnecessary trap instructions, we can instead set
LPStart to an offset from the FDE. If we emit it as [FDEStart - 1], then
all real offsets from LPStart in FDE become non-negative.
Commit: f981ee7efc3e0be0d91d2163c0e04e01a134b4a6
https://github.com/llvm/llvm-project/commit/f981ee7efc3e0be0d91d2163c0e04e01a134b4a6
Author: lialan <me at alanli.org>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
Log Message:
-----------
[MLIR] extend `getCompressedMaskOp` support in `VectorEmulateNarrowType` (#116122)
Previously when `numFrontPadElems` is not zero, `getCompressedMaskOp`
produces wrong result if the mask generator op is a
`vector.create_mask`.
This patch resolves the issue by including `numFrontPadElems` into the
mask generation.
Signed-off-by: Alan Li <me at alanli.org>
Commit: 673b5dd380e8457c887d5b321195d81ea90f134d
https://github.com/llvm/llvm-project/commit/673b5dd380e8457c887d5b321195d81ea90f134d
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
R clang/tools/clang-shlib/simple_version_script.map.in
M llvm/CMakeLists.txt
Log Message:
-----------
Revert "Introduce symbol versioning for clang-cpp (#116556)"
This reverts commit 944478dd62a78f6bb43d4da210643affcc4584b6.
Reverted because of following error on greendragon
ld: unknown options: --version-script
clang: error: linker command failed with exit code 1 (use -v to see invocation)
Commit: 2187738508478372409132ee636393086b46746f
https://github.com/llvm/llvm-project/commit/2187738508478372409132ee636393086b46746f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
Log Message:
-----------
[RISCV] Add additional CHECK prefixes to fixed-vectors-strided-load-store-asm.ll. NFC
We had 2 RUN lines with conflicting output sharing prefixes. The
script unfortunately did not report the error.
Commit: 01cd7ad2ba222b0fc400a820a9ef176131a82a06
https://github.com/llvm/llvm-project/commit/01cd7ad2ba222b0fc400a820a9ef176131a82a06
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFCommon.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-global.f90
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Do not generate NVVM target attribute when creating the module (#116882)
Leave it to the `NVVMAttachTargetPass` so we can set compute capability
and features.
Commit: 46389ebc4f4185700ed3322db533fdbd5de7f9a3
https://github.com/llvm/llvm-project/commit/46389ebc4f4185700ed3322db533fdbd5de7f9a3
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/test/Integration/Dialect/MemRef/verify-memref.mlir
Log Message:
-----------
[mlir][memref] Fix broken test after #114152 (#116898)
Commit: 58280c0e97ee8f843db0fc2719c7e599831d6626
https://github.com/llvm/llvm-project/commit/58280c0e97ee8f843db0fc2719c7e599831d6626
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Update test after #116882
Commit: 04de524c7e5d4dfe3ec6cdd83dcb6dfed46f3e8b
https://github.com/llvm/llvm-project/commit/04de524c7e5d4dfe3ec6cdd83dcb6dfed46f3e8b
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][arith] Fix build after #114152 (part 2) (#116901)
Since #114152, `MLIRFuncTransforms` no longer depends on
`MLIRBufferizationDialect`. This commit adds a missing dependency that
is no longer transitively included.
Commit: 1df199812296d6f4d1698ac228f3e85d29e96e29
https://github.com/llvm/llvm-project/commit/1df199812296d6f4d1698ac228f3e85d29e96e29
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][arith] Fix build after #114152 (part 3) (#116903)
Since https://github.com/llvm/llvm-project/pull/114152,
`MLIRFuncTransforms` no longer depends on `MLIRBufferizationTransforms`.
This commit adds a missing dependency that is no longer transitively
included.
Commit: 50e38cc85663de27cfed59b8f09edf3437fbf164
https://github.com/llvm/llvm-project/commit/50e38cc85663de27cfed59b8f09edf3437fbf164
Author: Vladimir Vereschaka <vvereschaka at accesssoftek.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M clang/cmake/caches/CrossWinToARMLinux.cmake
Log Message:
-----------
[CMake] Update CMake cache file for the ARM/Aarch64 cross toolchain builds. NFC. (#116744)
Forcely disable the libc++ benchmarks on Windows build hosts. The
benchmark configuration currently does not support the cross builds on
Windows hosts.
Also removed unnecessary `CMAKE_CROSSCOMPILING` CMake option.
Commit: 40c8938ff8447fc46bd2aa1605e3147cc38ffb8d
https://github.com/llvm/llvm-project/commit/40c8938ff8447fc46bd2aa1605e3147cc38ffb8d
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
A flang/test/HLFIR/bufferize-workshare.fir
A flang/test/Integration/OpenMP/workshare-array-array-assign.f90
A flang/test/Integration/OpenMP/workshare-axpy.f90
A flang/test/Integration/OpenMP/workshare-scalar-array-assign.f90
A flang/test/Integration/OpenMP/workshare-scalar-array-mul.f90
A flang/test/Transforms/OpenMP/should-use-workshare-lowering.mlir
Log Message:
-----------
[flang] Introduce hlfir.elemental lowerings to omp.workshare_loop_nest (#104748)
This patch adds parallelization support for the following expression in OpenMP
workshare constructs:
* Elemental procedures in array expressions
Commit: fa22100d57631bbb0a507dd27e3ebb24b1354623
https://github.com/llvm/llvm-project/commit/fa22100d57631bbb0a507dd27e3ebb24b1354623
Author: Ivan Radanov Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
R flang/test/HLFIR/bufferize-workshare.fir
R flang/test/Integration/OpenMP/workshare-array-array-assign.f90
R flang/test/Integration/OpenMP/workshare-axpy.f90
R flang/test/Integration/OpenMP/workshare-scalar-array-assign.f90
R flang/test/Integration/OpenMP/workshare-scalar-array-mul.f90
R flang/test/Transforms/OpenMP/should-use-workshare-lowering.mlir
Log Message:
-----------
Revert "[flang] Introduce hlfir.elemental lowerings to omp.workshare_loop_nest (#104748)"
This reverts commit 40c8938ff8447fc46bd2aa1605e3147cc38ffb8d.
Linking errors in buildbot build
Commit: 461e58e75dc3e2a0d6e0448c1ebcb8bd14e3d65c
https://github.com/llvm/llvm-project/commit/461e58e75dc3e2a0d6e0448c1ebcb8bd14e3d65c
Author: Aaron Puchert <aaronpuchert at alice-dsl.net>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
A clang/tools/clang-shlib/simple_version_script.map.in
M llvm/CMakeLists.txt
Log Message:
-----------
Introduce symbol versioning for clang-cpp (#116556)
The situation that required symbol versions on the LLVM shared library
can also happen for clang-cpp, although it is less common: different
tools require different versions of the library, and through transitive
dependencies a process ends up with multiple copies of clang-cpp. This
causes havoc with ELF, because calls meant to go one version of the
library end up with another.
I've also considered introducing a symbol version globally, but for
example the clang (C) library and other targets outside of LLVM/Clang,
e.g. libc++, would not want that. So it's probably best if we keep it to
those libraries.
Commit: 8234c612eda1cdff702f5ede1d7db7baf3bf0e47
https://github.com/llvm/llvm-project/commit/8234c612eda1cdff702f5ede1d7db7baf3bf0e47
Author: WÁNG Xuěruì <git at xen0n.name>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
M llvm/test/MC/LoongArch/Basic/Integer/invalid64.s
Log Message:
-----------
[LoongArch] Record the special AMO operand constraint with TableGen (#114398)
Depends on #114508
The LoongArch Reference Manual says that the 3-register atomic memory
operations cannot have their rd equal to either rj or rk [^1], and both
GNU as and LLVM IAS enforce the constraint for non-zero rd. However,
currently LoongArch AsmParser is checking for the opcode with a direct
numerical comparison on the opcode, which is enum-typed: the fact that
all AMO insns have adjacent numerical values is merely a coincidence,
and it is better to not rely on the current TableGen implementation
behavior.
Instead, start to leverage the target-specific flags field of
MCInstrDesc, and record the constraint with TableGen, so we can stop
treating the opcode value as number. In doing so, we also have to mark
whether the instruction is AMCAS, because the operand index of rj and rk
for the AMCAS instructions is different.
While documenting the new flag, it was found that v1.10 of the Manual
did not specify the similar constraint for the AMCAS instructions.
Experiments were done on a Loongson 3A6000 (LA664 uarch) and it turned
out that at least AMCAS will still signal INE with `rd == rj`. The `rd
== rk` case should be a no-op according to the semantics, but as it is
meaningless to perform CAS with the "old value" same as the "new value",
it is not worth special-casing. So the current behavior of also
enforcing the constraint for AMCAS is kept.
[^1]: if `rd == rj` an INE would be signaled; if `rd == rk` it is UB.
Commit: b246d5f0556114d9a454bf2471f9c0577f1dce2f
https://github.com/llvm/llvm-project/commit/b246d5f0556114d9a454bf2471f9c0577f1dce2f
Author: Aaron Puchert <aaronpuchert at alice-dsl.net>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/tools/clang-shlib/CMakeLists.txt
Log Message:
-----------
Disable symbol versions for clang-cpp also with MSVC
It seems we can get there with MSVC if LLVM_BUILD_LLVM_DYLIB_VIS is set.
Slightly surprising because I didn't know that MSVC supports the flag
-Bsymbolic-functions, but let's play it safe.
Commit: 314e9b1cffbda767e9f4ac088a3caea80a9212bb
https://github.com/llvm/llvm-project/commit/314e9b1cffbda767e9f4ac088a3caea80a9212bb
Author: lifengxiang1025 <lifengxiang at kuaishou.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[llvm-profdata] fix typo (#116754)
Commit: a2e266b3463844b92b082698aaf201fdd8757c32
https://github.com/llvm/llvm-project/commit/a2e266b3463844b92b082698aaf201fdd8757c32
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Add computeUndriftMap (#116478)
This patch adds computeUndriftMap, a function to compute mappings from
source locations in the MemProf profile to source locations in the IR.
Commit: f97c610d1f824bcd3e078560c836aaaffaaf69b0
https://github.com/llvm/llvm-project/commit/f97c610d1f824bcd3e078560c836aaaffaaf69b0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[memprof] Add MemProfReader::takeMemProfData (#116769)
This patch adds MemProfReader::takeMemProfData, a function to return
the complete MemProf profile from the reader. We can directly pass
its return value to InstrProfWriter::addMemProfData without having to
deal with the indivual components of the MemProf profile. The new
function is named "take", but it doesn't do std::move yet because of
type differences (DenseMap v.s. MapVector).
The end state I'm trying to get to is roughly as follows:
- MemProfReader accepts IndexedMemProfData as a parameter as opposed
to the three individual components (frames, call stacks, and
records).
- MemProfReader keeps IndexedMemProfData as a class member without
decomposing it into its individual components.
- MemProfReader returns IndexedMemProfData like:
IndexedMemProfData takeMemProfData() {
return std::move(MemProfData);
}
Commit: 1f4d91ecb8529678a3d3919d7523743bd21942ca
https://github.com/llvm/llvm-project/commit/1f4d91ecb8529678a3d3919d7523743bd21942ca
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/ExecutionEngine/ExecutionEngine.cpp
M llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
M llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF.cpp
M llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/ExecutionEngine/MCJIT/MCJIT.cpp
M llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/DebugUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDebugObjectRegistrar.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/IRTransformLayer.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Mangling.cpp
M llvm/lib/ExecutionEngine/Orc/MapperJITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/MemoryMapper.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/SpeculateAnalyses.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderVTune.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/RegisterEHFrames.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
M llvm/lib/ExecutionEngine/SectionMemoryManager.cpp
Log Message:
-----------
[ExecutionEngine] Remove unused includes (NFC) (#116749)
Identified with misc-include-cleaner.
Commit: e9c8106a90d49e75bac87341ade57c6049357a97
https://github.com/llvm/llvm-project/commit/e9c8106a90d49e75bac87341ade57c6049357a97
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Object/TapiFile.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
Log Message:
-----------
[Object] Remove unused includes (NFC) (#116750)
Identified with misc-include-cleaner.
Commit: 4f1b20f023626a2ae9aab627e918974ce81199fe
https://github.com/llvm/llvm-project/commit/4f1b20f023626a2ae9aab627e918974ce81199fe
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/ProfileData/PGOCtxProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
Log Message:
-----------
[ProfileData] Remove unused includes (NFC) (#116751)
Identified with misc-include-cleaner.
Commit: 27d25d1c12a34d0cfd47416e77cd83b7b768f1e7
https://github.com/llvm/llvm-project/commit/27d25d1c12a34d0cfd47416e77cd83b7b768f1e7
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M libc/docs/gpu/rpc.rst
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/src/__support/RPC/rpc.h
M libc/src/stdio/gpu/file.h
M libc/src/stdio/gpu/vfprintf_utils.h
M libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
Log Message:
-----------
[libc] Increase RPC opcode to 32-bit and use a class byte (#116905)
Summary:
Currently, the RPC interface uses a basic opcode to communicate with the
server. This currently is 16 bits. There's no reason for this to be 16
bits, because on the GPU a 32-bit write is the same as a 16-bit write
performance wise.
Additionally, I am now making all the `libc` based opcodes qualified
with the 'c' type, mimiciing how Linux handles `ioctls` all coming from
the same driver. This will make it easier to extend the interface when
it's exported directly.
Commit: 0ff8b79160509b25fd913ffa320b9dab5b87b55e
https://github.com/llvm/llvm-project/commit/0ff8b79160509b25fd913ffa320b9dab5b87b55e
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTestVerilog.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Stop crashing on slightly off Verilog module headers (#116000)
This piece of code made the program crash.
```Verilog
function pkg::t get
(int t = 2,
int f = 2);
```
The way the code is supposed to be parsed is that UnwrappedLineParser
should identify the function header, and then TokenAnnotator should
recognize the result. But the code in UnwrappedLineParser would
mistakenly not recognize it due to the `::`. Then TokenAnnotator would
recognize the comma both as TT_VerilogInstancePortComma and
TT_VerilogTypeComma. The code for annotating the instance port comma
used `setFinalizedType`. The program would crash when it tried to set
it to another type.
The code in UnwrappedLineParser now recognizes the `::` token.
The are other cases in which TokenAnnotator would recognize the comma as
both of those types, for example if the `function` keyword is removed.
The type is now set using `setType` instead so that the program does not
crash. The developer no longer knows why he used `setFinalizedType`
back then.
Commit: 2bf6751522e8683d719d5651a4555147dd7d6acd
https://github.com/llvm/llvm-project/commit/2bf6751522e8683d719d5651a4555147dd7d6acd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
Log Message:
-----------
[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.
This restores the code to its original state before I experimented
with making i32 a legal type.
Commit: c6bce68f9a357d13b4ad85a1a0b74ce4ee768885
https://github.com/llvm/llvm-project/commit/c6bce68f9a357d13b4ad85a1a0b74ce4ee768885
Author: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Coroutines/ABI.h
Log Message:
-----------
[NFC] [Coroutines] Use std::move to avoid copying (#116776)
Commit: fa4d1860d20a5afa6f96673ba02a99f09f69869c
https://github.com/llvm/llvm-project/commit/fa4d1860d20a5afa6f96673ba02a99f09f69869c
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/ELF/OutputSections.cpp
M lld/ELF/OutputSections.h
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.h
Log Message:
-----------
[ELF] Move PhdrEntry to SyntheticSections
The next change will change Partition::phdrs to a unique_ptr vector,
which requires PhdrEntry to be a complete type.
And make OutputSection::getLMA out-of-line, since it should not include
either SyntheticSections.h or Writer.h.
Commit: a52032448efb5d24af9c57418580206f17931401
https://github.com/llvm/llvm-project/commit/a52032448efb5d24af9c57418580206f17931401
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Avoid make<PhdrEntry>
Store them in Partition::phdrs instead.
Commit: 37e39667ccdbf96645515ff6ad8f86d499f472e8
https://github.com/llvm/llvm-project/commit/37e39667ccdbf96645515ff6ad8f86d499f472e8
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-19 (Tue, 19 Nov 2024)
Changed paths:
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
M lld/ELF/Thunks.cpp
M lld/ELF/Thunks.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Make ThunkCreator take ownership of thunks
This removes many SpecificAlloc instantiations and makes my lld (x86-64
Release+Assertions) smaller by ~36k.
Commit: 1ff22f8a71b8557018b4a877aff08c194970a909
https://github.com/llvm/llvm-project/commit/1ff22f8a71b8557018b4a877aff08c194970a909
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][vector] Add more tests for ConvertVectorToLLVM (9/n) (#116795)
Adds tests with scalable vectors for the Vector-To-LLVM conversion pass.
Covers the following Ops:
* `vector.load`,
* `vector.store`.
In addition:
* For consistency with other tests, renamed test function names
(e.g. `@vector_load_op_nontemporal` -> `vector_load_nontemporal`)
* Moved `@vector_load_0d` near other test for `vector.load` (as opposed
to next to `@vector_store_0d`).
Commit: 560dd940f5731fc255b67dde076427cabcddb149
https://github.com/llvm/llvm-project/commit/560dd940f5731fc255b67dde076427cabcddb149
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/lib/Sema/JumpDiagnostics.cpp
Log Message:
-----------
[clang] [NFC] In GetDiagForGotoScopeDecl(), limit Init to inside the if condition (#116080)
Commit: d33673ab05e5027b78a21eb3ecd9c0ae9a0ace9f
https://github.com/llvm/llvm-project/commit/d33673ab05e5027b78a21eb3ecd9c0ae9a0ace9f
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/test/Dialect/Vector/eliminate-masks.mlir
Log Message:
-----------
[mlir][vector][nfc] Update test for mask elimination (#112130)
Updates one example so that:
* it uses `vector.mask`,
* upper loop bound is a multiple of the loop step,
* use `vector.outerproduct` instead of "test.some_computation".
This makes this example a bit closer to realistic cases, which has
always been the goal for this test.
Commit: 0394e08bfbb110d606ace49bd10d951eb904e5d6
https://github.com/llvm/llvm-project/commit/0394e08bfbb110d606ace49bd10d951eb904e5d6
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M lldb/source/Target/StackFrame.cpp
M lldb/test/API/source-manager/TestSourceManager.py
Log Message:
-----------
[lldb] Reword the "line 0" warning (#116827)
We got a bug report that this message is confusing. In this particular
case, the line zero was due to compiler tail merging (in optimized
code). The main issue was the "no source code" part: in this case it's
kind of incorrect because -- even though we can't really know that --
the address is arguably associated with *multiple* lines of source code.
I've tried to make the new wording more neutral, and added a wink
towards compiler optimizations. I left out the "compiler generated" part
of the message because I couldn't find a way to squeeze that in nicely.
I'm also not entirely sure what it was referring to -- if this was
(just) function prologue/epilogue, then maybe leaving it out is fine, as
we're not likely to stop there anyway (?)
I also left out the function name, because:
- for template functions it gets rather long
- it's already present in the message, potentially twice (once in the
"frame summary" line and once in the snippet of code we show for the
function declaration)
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 3a5cf6d99b9988a013da3a87ab8f117e5c541f4b
https://github.com/llvm/llvm-project/commit/3a5cf6d99b9988a013da3a87ab8f117e5c541f4b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86ReplaceableInstrs.def
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
M llvm/utils/TableGen/X86ManualFoldTables.def
M llvm/utils/TableGen/X86ManualInstrMapping.def
Log Message:
-----------
[X86] Rename AVX512 VEXTRACT/INSERT??x? to VEXTRACT/INSERT??X? (#116826)
Use uppercase in the subvector description ("32x2" -> "32X4" etc.) - matches what we already do in VBROADCAST??X?, and we try to use uppercase for all x86 instruction mnemonics anyway (and lowercase just for the arg description suffix).
Commit: 67a1fdb014790a38a205d28e1748634de34471dd
https://github.com/llvm/llvm-project/commit/67a1fdb014790a38a205d28e1748634de34471dd
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/IR/attribute.mlir
Log Message:
-----------
[mlir][IR] Treat `tf32` as 19-bit float (#116738)
TF32 is a variant of F32 that is truncated to 19 bits. There used to be
special handling in `FloatType::getWidth()` so that TF32 was treated as
a 32-bit float in some places. (Some places use `FloatType::getWidth`,
others directly query the `APFloat` semantics.) This caused problems
because `FloatType::getWidth` did not agree with the underlying
`APFloat` semantics.
In particular, creating an elements attr / array attr with `tf32`
element type crashed. E.g.:
```
"foo"() {attr = dense<4.0> : tensor<tf32>} : () -> ()
mlir-opt: llvm-project/llvm/lib/Support/APFloat.cpp:4108: void llvm::detail::IEEEFloat::initFromAPInt(const fltSemantics *, const APInt &): Assertion `api.getBitWidth() == Sem->sizeInBits' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
```
```
"foo"() {f32attr = array<tf32: 1024.>} : () -> ()
mlir-opt: llvm-project/mlir/lib/AsmParser/AttributeParser.cpp:847: void (anonymous namespace)::DenseArrayElementParser::append(const APInt &): Assertion `data.getBitWidth() % 8 == 0' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
```
It is unclear why the special handling for TF32 is needed. For
reference: #107372
Commit: 1e32a7d42c8cec56246c124bdc4292ae294f8884
https://github.com/llvm/llvm-project/commit/1e32a7d42c8cec56246c124bdc4292ae294f8884
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
Log Message:
-----------
[AA] Rename CaptureInfo -> CaptureAnalysis (NFC) (#116842)
I'd like to use the name CaptureInfo to represent the new attribute
proposed at
https://discourse.llvm.org/t/rfc-improvements-to-capture-tracking/81420,
but it's already taken by AA, and I can't think of great alternatives
(CaptureEffects would be something of a stretch).
As such, I'd like to rename CaptureInfo -> CaptureAnalysis in AA, which
also seems like the more accurate terminology.
Commit: 596bfb804ba70241ce2ac7d387505c9562e09632
https://github.com/llvm/llvm-project/commit/596bfb804ba70241ce2ac7d387505c9562e09632
Author: Dragan Mladjenovic <Dragan.Mladjenovic at syrmia.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
Log Message:
-----------
[MLIR][AMDGPU] Support gpu::ShuffleMode::DOWN lowering in ROCDL (#106237)
Commit: d49ee7d54fe2142976494c1c9b930820f0f62259
https://github.com/llvm/llvm-project/commit/d49ee7d54fe2142976494c1c9b930820f0f62259
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update SelectionDAG maintainers (#116408)
bogner is listed as the current SDAG maintainer, but mostly works on
DirectX nowadays and isn't directly involved with SDAG work anymore.
Add RKSimon and topperc as new SelectionDAG maintainers.
Commit: ac38ab594f1b7c9a9f67007f7684e4d46b2588be
https://github.com/llvm/llvm-project/commit/ac38ab594f1b7c9a9f67007f7684e4d46b2588be
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M compiler-rt/lib/lsan/lsan_common.cpp
Log Message:
-----------
[lsan] Use VReport if not REGISTERS_AVAILABLE (#116555)
Certain tests (many are from lld/test) run `... '2>&1 | count 0` to
ensure that there is no stderr message.
GetRegistersAndSP may rarely fail, leading to
a spurious failure like (with a local hack to make `count` dump the
input):
```
+ /home/ray/llvm/out/asan/bin/ld.lld func1-gcs.o func2-gcs.o func3-gcs.o -o /dev/null -z gcs-report=warning -z gcs=never
+ /home/ray/llvm/out/asan/bin/count 0
Expected 0 lines, got 1.
==2403039==Unable to get registers from thread 2403018.
```
The failure can reliably be reproduced by running `ninja check-lld` a
few times under asan+lsan (see the bot
sanitizer-x86_64-linux-bootstrap-asan).
Commit: ddc0c5c7a3bb39067f11c87ab7ca0ed934ad27e7
https://github.com/llvm/llvm-project/commit/ddc0c5c7a3bb39067f11c87ab7ca0ed934ad27e7
Author: Raul Tambre <raul at tambre.ee>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/cmake/config-ix.cmake
Log Message:
-----------
[CMake] Do all availability checks with -D_GNU_SOURCE (#116640)
When compiling LLVM with -std=c++ instead of -std=gnu we'd fail to detect many newer POSIX functions.
We define it for the whole of LLVM anyway so moving the definition to the top fixes detection of a bunch of these on such setups.
Keeping it at the top also avoids accidentally introducing new dependent checks before it being defined.
Commit: aeb88f6778756ea889918308241a2b34bd7f64e2
https://github.com/llvm/llvm-project/commit/aeb88f6778756ea889918308241a2b34bd7f64e2
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
Log Message:
-----------
Fix test failures introduced by PR #113697 (#116941)
Don't match the entire floating point debug output since it's prone to
rounding errors depending upon the target.
Commit: bca846d462e989a6e7a2ef085dbf367aeca106bd
https://github.com/llvm/llvm-project/commit/bca846d462e989a6e7a2ef085dbf367aeca106bd
Author: David Green <david.green at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
Log Message:
-----------
[AArch64] Improve mull generation (#114997)
This attempts to clean up and improve where we generate smull/umull
using known-bits. For v2i64 types (where no mul is present), we try to
create mull more aggressively to avoid scalarization.
Commit: 34881138ed94709d09f690a27cd457d6a830f123
https://github.com/llvm/llvm-project/commit/34881138ed94709d09f690a27cd457d6a830f123
Author: JaydeepChauhan14 <167076022+JaydeepChauhan14 at users.noreply.github.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
Log Message:
-----------
[NFC] Fixed indentation issue (#116942)
Commit: 5310855316a8356d5862714a21e1e6344f84225e
https://github.com/llvm/llvm-project/commit/5310855316a8356d5862714a21e1e6344f84225e
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
Log Message:
-----------
[clangd] Fix erroneous qualification of template type parameters (#116821)
...in DefineOutline tweak.
E.g. moving the following definition:
`template<typename T> struct S { T f^oo() const { return T(); } };`
would result in:
`template<typename T> S<T>::T S::foo() const { return T(); }`
instead of:
`template<typename T> T S::foo() const { return T(); }`
Commit: 9111d531d85a743986ebc51b68fc1734086531ea
https://github.com/llvm/llvm-project/commit/9111d531d85a743986ebc51b68fc1734086531ea
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
R flang/CODE_OWNERS.TXT
A flang/Maintainers.txt
Log Message:
-----------
[flang] Rename Code Owners to Maintainers (#116009)
https://llvm.org/docs/DeveloperPolicy.html#maintainers
Commit: 92604d7c8061615dfb77568cc9cb2169f648290a
https://github.com/llvm/llvm-project/commit/92604d7c8061615dfb77568cc9cb2169f648290a
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenMP/Todo/map-mapper.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
A flang/test/Semantics/OpenMP/map-clause-symbols.f90
M flang/test/Semantics/OpenMP/map-clause.f90
Log Message:
-----------
[flang][OpenMP]Add parsing support for MAP(MAPPER(name) ...) (#116274)
This prepares for using the DECLARE MAPPER construct.
A check in lowering will say "Not implemented" when trying to use a
mapper as some code is required to tie the mapper to the declared one.
Senantics check for the symbol generated.
Commit: b7ddb97ac2cfb57f17c7f68815606cbd57918417
https://github.com/llvm/llvm-project/commit/b7ddb97ac2cfb57f17c7f68815606cbd57918417
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
A flang/test/Lower/OpenMP/Todo/scope-allocate.f90
A flang/test/Lower/OpenMP/Todo/scope-firstprivate.f90
Log Message:
-----------
[flang][OpenMP]Add TODO checking for scope allocate and firstprivate (#116801)
For the situation where scope is implemented to 5.1 standard, check that
the 5.2 are still "not yet implemented" (or some other partial
implementation).
Commit: 288f05f63e5f3246657aca9561d75b2aa02cb6f5
https://github.com/llvm/llvm-project/commit/288f05f63e5f3246657aca9561d75b2aa02cb6f5
Author: Md Asghar Ahmad Shahid <md.asghar.ahmad.shahid at intel.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Log Message:
-----------
[NFC][MLIR][Linalg] Refactor linalg.matmul tablegen ODS and related C++ code. (#116377)
This commit refactors part of the code in preparation for the migration
of other *matmul* variants from OpDSL to ODS.
Moves getDefaultIndexingmaps() helper into the MatmulOp class.
Commit: 2b5214b9e16cdc784def1d521ce38074a2e8c90f
https://github.com/llvm/llvm-project/commit/2b5214b9e16cdc784def1d521ce38074a2e8c90f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
IR: de-duplicate two CmpInst routines (NFC) (#116866)
De-duplicate the functions getSignedPredicate and getUnsignedPredicate,
nearly identical versions of which were present in CmpInst and ICmpInst,
creating less confusion.
Commit: 9bccf61f5fd20a52f997b23a56c13ada72c46eae
https://github.com/llvm/llvm-project/commit/9bccf61f5fd20a52f997b23a56c13ada72c46eae
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
A llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-vscale-tune.ll
Log Message:
-----------
[AArch64][LV] Set MaxInterleaving to 4 for Neoverse V2 and V3 (#100385)
Set the maximum interleaving factor to 4, aligning with the number of available
SIMD pipelines. This increases the number of vector instructions in the vectorised
loop body, enhancing performance during its execution. However, for very low
iteration counts, the vectorised body might not execute at all, leaving only the
epilogue loop to run. This issue affects e.g. cam4_r from SPEC FP, which
experienced a performance regression. To address this, the patch reduces the
minimum epilogue vectorisation factor from 16 to 8, enabling the epilogue to be
vectorised and largely mitigating the regression.
Commit: 09c41246ed58344892a1a82f7256a4ad6e1c49d7
https://github.com/llvm/llvm-project/commit/09c41246ed58344892a1a82f7256a4ad6e1c49d7
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
Log Message:
-----------
[AMDGPU] Fix restores in chain functions (#116193)
When spilling a VGPR in `emitPrologue`, chain functions prefer to use
offsets to access the stack instead of the SP.
This patch fixes `emitEpilogue` to do the same. It also brings back some
test coverage that was lost in #93526, when WWM registers started being
shifted to the lowest available range (which meant that tests that were
originally spilling v8 would shift to spill v0, which is a scratch
register for chain functions and didn't get spilled).
Change-Id: Icb07fccd859b563cd45f74c25ae578ecb38bdeeb
Commit: 9568f88b7f05015a438ed8beb4f4d07782c34dc2
https://github.com/llvm/llvm-project/commit/9568f88b7f05015a438ed8beb4f4d07782c34dc2
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-binop-cmp.ll
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
Log Message:
-----------
InstCombine: support floating-point equivalences (#114975)
Since cd16b07 (IR: introduce CmpInst::isEquivalence), there is now an
isEquivalence routine in CmpInst that we can use to determine
equivalence in foldSelectValueEquivalence. Implement this, extending it
to include floating-point equivalences as well.
Commit: 62bf5840a63fbe0856c47df3f9ed6b8f1202b385
https://github.com/llvm/llvm-project/commit/62bf5840a63fbe0856c47df3f9ed6b8f1202b385
Author: Xi Ruoyao <xry111 at xry111.site>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Basic/BuiltinsLoongArchLSX.def
M clang/lib/Headers/lasxintrin.h
M clang/lib/Headers/lsxintrin.h
Log Message:
-----------
[LoongArch][Clang] Make the parameters and return value of {x,}vorn.v builti ns `unsigned char` vectors (#114514)
All other bitwise vector builtins use `unsigned char` vector operands,
so it does not make too much sense to use `signed char` for the orn
operation alone.
The same change has been also proposed for GCC:
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/667065.html.
Depends on #114513.
Commit: 77bf34c3154408eb49eda171fbf4d50e3d66f019
https://github.com/llvm/llvm-project/commit/77bf34c3154408eb49eda171fbf4d50e3d66f019
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/lse_atomics/windows.inc
Log Message:
-----------
[AArch64][compiler-rt] Add LSE support for Windows. (#116706)
Commit: 408659c5b5c7d745042ae71db344d1ed10601512
https://github.com/llvm/llvm-project/commit/408659c5b5c7d745042ae71db344d1ed10601512
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
Log Message:
-----------
[RISCV] Merge GPRPair and GPRF64Pair (#116094)
As suggested by Craig, this tries to merge the two sets of register
classes created in #112983, GPRPair* and GPRF64Pair*.
- I added some explicit annotations to `RISCVInstrInfoD.td` which fixed
the type inference issues I was seeing from tablegen for select
patterns.
- I've had to make the behaviour of `splitValueIntoRegisterParts` and
`joinRegisterPartsIntoValue` cover more cases, because you cannot
bitcast to/from untyped (the bitcast would otherwise have been inserted
automatically by TargetLowering code).
- I apparently didn't need to change `getNumRegisters` again, which
continues to tell me there's a bug in the code for tied inputs. I added
some more test coverage of this case but it didn't seem to help find the
asserts I was finding before - I think the difference is between the
default behaviour for integers which doesn't apply to floats.
- There's still a difference between BuildGPRPair and BuildPairF64 (and
the same for SplitGPRPair and SplitF64). I'm not happy with this, I
think it's quite confusing, as they're very similar, just differing in
whether they give a `untyped` or a `f64`. I haven't really worked out
how the DAGCombiner copes if one meets the other, I know we have some of
this for the f64 variants already, but they're a lot more complex than
the GPRPair variants anyway.
Commit: 1b792252e3d52dc60ddadac1ba8f1ad7b40d60c9
https://github.com/llvm/llvm-project/commit/1b792252e3d52dc60ddadac1ba8f1ad7b40d60c9
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
Log Message:
-----------
[AMDGPU] Remove hasPostISelHook for atomics. NFC. (#116791)
This is not required since 2147b6c89d44 changed that way that no-ret
atomic ops are selected.
Commit: 5f1a7f274969728801f20a0239848f5f93a39baa
https://github.com/llvm/llvm-project/commit/5f1a7f274969728801f20a0239848f5f93a39baa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s
Log Message:
-----------
[X86] Fix scheduler class for EVEX VMOVNTDQA variants and cleanup Skylake/Icelake resource usage (#116946)
Ensure we use the SchedWriteVecMoveLSNT class for all (V)MOVNTDQA instructions, remove unnecessary scheduler overrides and adjust resource pipe usage to match uops.info/Agner numbers
Commit: 0a1795f781163a8e7b72fee492f87ab27d5e3995
https://github.com/llvm/llvm-project/commit/0a1795f781163a8e7b72fee492f87ab27d5e3995
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
Log Message:
-----------
[SDAG] Generalize FSINCOS type legalization (NFC) (#116848)
There's nothing that specific to FSINCOS about these; they could be used
for similar nodes in the future.
Commit: 18b02bbf441660683df7f3925946984203d49bab
https://github.com/llvm/llvm-project/commit/18b02bbf441660683df7f3925946984203d49bab
Author: DianQK <dianqk at dianqk.net>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemorySSAUpdater.h
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
A llvm/test/Transforms/LICM/PR116813-memoryssa-outdated.ll
Log Message:
-----------
[LICM] allow MemoryAccess creation failure (#116813)
Fixes #116809.
After running some passes (SimpleLoopUnswitch, LoopInstSimplify, etc.),
MemorySSA might be outdated, and the instruction `I` may have become a
non-memory touching instruction.
LICM has already handled this, but it does not pass
`CreationMustSucceed=false` to `createDefinedAccess`.
Commit: af0e0ded7be29a7007c08105a0329e85cd937499
https://github.com/llvm/llvm-project/commit/af0e0ded7be29a7007c08105a0329e85cd937499
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ExprConstant.cpp
M clang/test/Sema/constant_builtins_vector.cpp
Log Message:
-----------
[clang] constexpr built-in reduce and function. (#116822)
Part of #51787.
Follow up of #116626.
This patch adds constexpr support for the built-in reduce and function.
Commit: d0522f4a9af84a3b402586f71cacd3c14269711a
https://github.com/llvm/llvm-project/commit/d0522f4a9af84a3b402586f71cacd3c14269711a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s
Log Message:
-----------
[X86] Fix PSHUFB port usage on Skylake/Icelake
MMX PSHUFB has an additional Port0 dependency (as do most MMX instructions) - confirmed with uops.info
Commit: b32a441e087827ee6ff32e35a7cea02b14341293
https://github.com/llvm/llvm-project/commit/b32a441e087827ee6ff32e35a7cea02b14341293
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-20 (Wed, 20 Nov 2024)
Changed paths:
M .github/new-issues-labeler.yml
M bolt/include/bolt/Core/BinarySection.h
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Core/BinarySection.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/eh-frame-hdr.test
A bolt/test/eh-frame-overwrite.test
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.h
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
M clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp
M clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
M clang/cmake/caches/CrossWinToARMLinux.cmake
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSafetyAnalysis.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsLoongArchLASX.def
M clang/include/clang/Basic/BuiltinsLoongArchLSX.def
M clang/include/clang/Basic/Cuda.h
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticRefactoringKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_mve_defs.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/FrontendAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/Interpreter/PartialTranslationUnit.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/lasxintrin.h
M clang/lib/Headers/lsxintrin.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/IncrementalExecutor.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/Wasm.cpp
M clang/lib/Interpreter/Wasm.h
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/JumpDiagnostics.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/GlobalModuleIndex.cpp
M clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RasterizerOrderedStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p3.cpp
M clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p2-cxx0x.cpp
M clang/test/CodeGen/AArch64/elf-pauthabi.c
M clang/test/CodeGen/PowerPC/musttail-forward-declaration-inline.c
M clang/test/CodeGen/PowerPC/musttail-forward-declaration-weak.c
M clang/test/CodeGen/PowerPC/musttail-indirect.cpp
M clang/test/CodeGen/PowerPC/musttail-inline.c
M clang/test/CodeGen/PowerPC/musttail-undefined.c
M clang/test/CodeGen/PowerPC/musttail-weak.c
M clang/test/CodeGen/PowerPC/musttail.c
M clang/test/CodeGen/X86/x86_64-PR42672.c
M clang/test/CodeGen/arm-mve-intrinsics/compare.c
A clang/test/CodeGen/ptrauth-module-flags.c
A clang/test/CodeGen/scoped-fence-ops.c
A clang/test/CodeGenCUDASPIRV/spirv-attrs.cu
M clang/test/CodeGenOpenCL/amdgpu-features.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx950.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/module-output.cppm
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/pragma-attribute-strict-subjects.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M clang/test/Modules/no-eager-load.cppm
M clang/test/Modules/same-decl-in-different-modules.cppm
M clang/test/OpenMP/for_simd_loop_messages.cpp
M clang/test/OpenMP/masked_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/master_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/parallel_for_simd_messages.cpp
M clang/test/OpenMP/parallel_masked_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/parallel_master_taskloop_simd_linear_messages.cpp
M clang/test/OpenMP/simd_linear_messages.cpp
M clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp
M clang/test/OpenMP/taskloop_simd_linear_messages.cpp
M clang/test/Parser/cxx2c-delete-with-message.cpp
M clang/test/Parser/pragma-attribute.cpp
M clang/test/ParserHLSL/hlsl_resource_handle_attrs.hlsl
M clang/test/Preprocessor/ptrauth_feature.c
M clang/test/Refactor/Extract/ObjCProperty.m
M clang/test/Sema/asm.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/c2x-nodiscard.c
M clang/test/Sema/constant_builtins_vector.cpp
M clang/test/Sema/pragma-attribute-strict-subjects.c
A clang/test/SemaCUDA/spirv-attrs.cu
M clang/test/SemaCXX/builtin-bit-cast.cpp
M clang/test/SemaCXX/warn-shadow.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-warning-data-invocation.cpp
M clang/test/SemaCXX/warn-unused-result.cpp
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaHLSL/BuiltIns/StructuredBuffers.hlsl
M clang/test/SemaObjC/comptypes-legal.m
A clang/test/SemaObjC/method-param-named-id.m
M clang/test/SemaOpenCL/access-qualifier.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950-param.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx950.cl
M clang/tools/amdgpu-arch/AMDGPUArch.cpp
R clang/tools/amdgpu-arch/AMDGPUArchByHSA.cpp
A clang/tools/amdgpu-arch/AMDGPUArchByKFD.cpp
M clang/tools/amdgpu-arch/CMakeLists.txt
M clang/tools/clang-shlib/CMakeLists.txt
A clang/tools/clang-shlib/simple_version_script.map.in
M clang/unittests/Format/FormatTestVerilog.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/lse_atomics/windows.inc
M compiler-rt/lib/hwasan/hwasan_platform_interceptors.h
M compiler-rt/lib/lsan/lsan_common.cpp
M compiler-rt/lib/msan/tests/msan_test.cpp
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.h
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
A compiler-rt/test/profile/ContinuousSyncMode/multi-threaded.cpp
M compiler-rt/test/profile/ContinuousSyncMode/online-merging.c
M compiler-rt/test/profile/lit.cfg.py
A compiler-rt/test/rtsan/report_error_summary.cpp
R flang/CODE_OWNERS.TXT
A flang/Maintainers.txt
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Optimizer/OpenMP/Passes.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Passes/Pipelines.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-io.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Driver/dynamic-linker.f90
M flang/test/Driver/isysroot.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/CUDA/cuda-device-global.f90
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
M flang/test/Fir/basic-program.fir
A flang/test/Fir/target-rewrite-integer-loongarch64.fir
A flang/test/Lower/OpenMP/Todo/map-mapper.f90
A flang/test/Lower/OpenMP/Todo/scope-allocate.f90
A flang/test/Lower/OpenMP/Todo/scope-firstprivate.f90
M flang/test/Lower/OpenMP/workshare.f90
M flang/test/Parser/OpenMP/map-modifiers.f90
A flang/test/Semantics/OpenMP/map-clause-symbols.f90
M flang/test/Semantics/OpenMP/map-clause.f90
M flang/test/Semantics/io03.f90
M flang/test/Semantics/io04.f90
A flang/test/Semantics/pointer02.f90
A flang/test/Semantics/smp-def02.f90
M flang/test/Semantics/undef-result01.f90
A flang/test/Transforms/OpenMP/lower-workshare-alloca.mlir
A flang/test/Transforms/OpenMP/lower-workshare-binding.mlir
A flang/test/Transforms/OpenMP/lower-workshare-cleanup.mlir
A flang/test/Transforms/OpenMP/lower-workshare-copyprivate.mlir
A flang/test/Transforms/OpenMP/lower-workshare-correct-parallelize.mlir
A flang/test/Transforms/OpenMP/lower-workshare-no-single.mlir
A flang/test/Transforms/OpenMP/lower-workshare-nowait.mlir
A flang/test/Transforms/OpenMP/lower-workshare-todo-cfg-dom.mlir
A flang/test/Transforms/OpenMP/lower-workshare-todo-cfg.mlir
M flang/tools/bbc/bbc.cpp
M flang/tools/tco/tco.cpp
M libc/docs/gpu/rpc.rst
M libc/fuzzing/__support/hashtable_fuzz.cpp
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/src/__support/HashTable/generic/bitmask_impl.inc
M libc/src/__support/OSUtil/gpu/exit.cpp
M libc/src/__support/RPC/rpc.h
M libc/src/__support/RPC/rpc_client.h
M libc/src/__support/RPC/rpc_util.h
M libc/src/__support/hash.h
M libc/src/math/generic/exp10m1f16.cpp
M libc/src/math/generic/tanhf16.cpp
M libc/src/stdio/gpu/file.h
M libc/src/stdio/gpu/vfprintf_utils.h
M libc/src/stdlib/gpu/abort.cpp
M libc/test/src/__support/HashTable/group_test.cpp
M libc/test/src/__support/HashTable/table_test.cpp
M libc/utils/gpu/server/llvmlibc_rpc_server.h
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/include/CMakeLists.txt
M libcxx/include/__atomic/atomic.h
R libcxx/include/__atomic/atomic_base.h
M libcxx/include/atomic
M libcxx/include/barrier
M libcxx/include/bit
M libcxx/include/charconv
M libcxx/include/compare
M libcxx/include/expected
M libcxx/include/future
M libcxx/include/latch
M libcxx/include/mdspan
M libcxx/include/memory_resource
M libcxx/include/module.modulemap
M libcxx/include/ranges
M libcxx/include/semaphore
M libcxx/include/string
M libcxx/src/barrier.cpp
M libcxx/test/benchmarks/CMakeLists.txt
M libcxx/test/benchmarks/ContainerBenchmarks.h
M libcxx/test/benchmarks/deque.bench.cpp
M libcxx/test/benchmarks/vector_operations.bench.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/std/containers/sequences/vector/vector.modifiers/common.h
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/thread/futures/futures.async/async.pass.cpp
M libcxx/test/std/utilities/utility/pairs/pairs.pair/ctor.default.pass.cpp
M lld/COFF/DLL.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
M lld/ELF/OutputSections.cpp
M lld/ELF/OutputSections.h
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Thunks.cpp
M lld/ELF/Thunks.h
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
A lld/test/ELF/aarch64-thunk-bti-multipass.s
M lld/test/ELF/aarch64-thunk-bti.s
M lld/test/ELF/hexagon-jump-error.s
M lld/test/ELF/hexagon.s
M lld/test/wasm/tls-non-shared-memory.s
M lld/wasm/Symbols.cpp
M lld/wasm/Symbols.h
M lld/wasm/SyntheticSections.cpp
M lldb/bindings/interface/SBTargetExtensions.i
M lldb/docs/use/links.rst
M lldb/include/lldb/Host/Editline.h
M lldb/include/lldb/Host/MainLoopBase.h
M lldb/include/lldb/Host/posix/MainLoopPosix.h
M lldb/include/lldb/Host/windows/MainLoopWindows.h
M lldb/include/lldb/Target/ThreadPlanStack.h
M lldb/source/Host/common/Editline.cpp
M lldb/source/Host/common/MainLoopBase.cpp
M lldb/source/Host/posix/MainLoopPosix.cpp
M lldb/source/Host/windows/MainLoopWindows.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Target/ThreadPlanStack.cpp
M lldb/source/Utility/DiagnosticsRendering.cpp
M lldb/test/API/lang/cpp/stl/TestStdCXXDisassembly.py
M lldb/test/API/source-manager/TestSourceManager.py
A lldb/test/API/terminal/TestEditlineCompletions.py
M lldb/test/Shell/ObjectFile/ELF/elf-dynsym.test
M lldb/test/Shell/Unwind/windows-unaligned-x86_64.test
M lldb/unittests/Host/MainLoopTest.cpp
M lldb/unittests/Utility/DiagnosticsRenderingTest.cpp
M llvm/CMakeLists.txt
M llvm/Maintainers.md
M llvm/cmake/config-ix.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/InlineAdvisor.h
M llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
M llvm/include/llvm/Analysis/MemorySSAUpdater.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/IR/DerivedTypes.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/ProfileData/MemProfReader.h
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/Coroutines/ABI.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/ExecutionEngine/ExecutionEngine.cpp
M llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
M llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF.cpp
M llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
M llvm/lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/ExecutionEngine/MCJIT/MCJIT.cpp
M llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp
M llvm/lib/ExecutionEngine/Orc/CompileUtils.cpp
M llvm/lib/ExecutionEngine/Orc/DebugObjectManagerPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/DebugUtils.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDebugObjectRegistrar.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/IRTransformLayer.cpp
M llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Mangling.cpp
M llvm/lib/ExecutionEngine/Orc/MapperJITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/MemoryMapper.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/OrcABISupport.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/SpeculateAnalyses.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderVTune.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/RegisterEHFrames.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCOFF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
M llvm/lib/ExecutionEngine/SectionMemoryManager.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/DIExpressionOptimizer.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Type.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Object/Archive.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/MachOUniversal.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Object/TapiFile.cpp
M llvm/lib/Object/TapiUniversal.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/ProfileData/PGOCtxProfReader.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
M llvm/lib/Target/ARM/ARMScheduleM7.td
M llvm/lib/Target/ARM/ARMScheduleM85.td
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
M llvm/lib/Target/Mips/MipsCallingConv.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/VE/VEInstrInfo.td
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86ReplaceableInstrs.def
M llvm/lib/Target/X86/X86SchedIceLake.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SchedSkylakeClient.td
M llvm/lib/Target/X86/X86SchedSkylakeServer.td
M llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TextAPI/InterfaceFile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/LoopAccessAnalysis/select-dependence.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Assembler/target-type-properties.ll
M llvm/test/Bitcode/summary_version.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
R llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
A llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/popcount.ll
A llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
M llvm/test/CodeGen/AArch64/sinksplat.ll
A llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/adjust-writemask-cse.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
A llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
A llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
A llvm/test/CodeGen/AMDGPU/lds-size-pal-gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/ARM/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/DirectX/flatten-array.ll
A llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir
A llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
M llvm/test/CodeGen/Mips/fp16-promote.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
A llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
A llvm/test/CodeGen/NVPTX/misched_func_call.ll
A llvm/test/CodeGen/PowerPC/global-merge-aix-sections.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/DebugInfo/Generic/artificial-static-member.ll
M llvm/test/MC/AArch64/SVE/fexpa.s
M llvm/test/MC/AMDGPU/flat-scratch-gfx940.s
M llvm/test/MC/AMDGPU/gfx940_asm_features.s
A llvm/test/MC/AMDGPU/gfx950-unsupported.s
A llvm/test/MC/AMDGPU/gfx950_asm_features.s
A llvm/test/MC/AMDGPU/gfx950_asm_vop1.s
A llvm/test/MC/AMDGPU/gfx950_asm_vop1_dpp16.s
A llvm/test/MC/AMDGPU/gfx950_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx950_invalid_encoding.txt
A llvm/test/MC/AMDGPU/mai-gfx950.s
A llvm/test/MC/AMDGPU/mubuf-gfx950.s
M llvm/test/MC/Disassembler/AMDGPU/gfx940_features.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop1.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx950_mai.txt
M llvm/test/MC/LoongArch/Basic/Integer/invalid64.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
A llvm/test/ThinLTO/X86/Inputs/memprof-old-stackid-summary.bc
A llvm/test/ThinLTO/X86/memprof-old-stackid-summary.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/intersect-accessgroup.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/ptrmask.ll
M llvm/test/Transforms/InstCombine/select-binop-cmp.ll
M llvm/test/Transforms/InstCombine/select-value-equivalence.ll
M llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll
M llvm/test/Transforms/InstSimplify/logic-of-fcmps.ll
M llvm/test/Transforms/JumpThreading/PR33357-lvi-recursion.ll
M llvm/test/Transforms/JumpThreading/basic.ll
M llvm/test/Transforms/JumpThreading/crash.ll
M llvm/test/Transforms/JumpThreading/ddt-crash.ll
M llvm/test/Transforms/JumpThreading/ddt-crash4.ll
M llvm/test/Transforms/JumpThreading/landing-pad.ll
M llvm/test/Transforms/JumpThreading/pr22086.ll
M llvm/test/Transforms/JumpThreading/pr9331.ll
M llvm/test/Transforms/JumpThreading/preserving-debugloc-br.ll
M llvm/test/Transforms/JumpThreading/unreachable-loops.ll
M llvm/test/Transforms/LCSSA/indirectbr.ll
M llvm/test/Transforms/LCSSA/invoke-dest.ll
M llvm/test/Transforms/LCSSA/pr28424.ll
M llvm/test/Transforms/LCSSA/pr28608.ll
M llvm/test/Transforms/LCSSA/remove-phis.ll
M llvm/test/Transforms/LCSSA/unused-phis.ll
M llvm/test/Transforms/LICM/2009-12-10-LICM-Indbr-Crash.ll
A llvm/test/Transforms/LICM/PR116813-memoryssa-outdated.ll
M llvm/test/Transforms/LICM/alias-set-tracker-loss.ll
M llvm/test/Transforms/LICM/assume.ll
M llvm/test/Transforms/LICM/callbr-crash.ll
M llvm/test/Transforms/LICM/crash.ll
M llvm/test/Transforms/LICM/debug-value.ll
M llvm/test/Transforms/LICM/gc-relocate.ll
M llvm/test/Transforms/LICM/hoist-phi.ll
M llvm/test/Transforms/LICM/lcssa-ssa-promoter.ll
M llvm/test/Transforms/LICM/loopsink-pr39570.ll
M llvm/test/Transforms/LICM/outer-loop-deleted-before-licm.ll
M llvm/test/Transforms/LICM/pr32129.ll
M llvm/test/Transforms/LICM/pr37323.ll
M llvm/test/Transforms/LICM/pr38513.ll
M llvm/test/Transforms/LICM/pr50367.ll
M llvm/test/Transforms/LICM/sink-promote.ll
M llvm/test/Transforms/LICM/sinking.ll
M llvm/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll
M llvm/test/Transforms/LoopDeletion/2017-07-11-incremental-dt.ll
M llvm/test/Transforms/LoopDeletion/bbi-59728.ll
M llvm/test/Transforms/LoopDeletion/crashbc.ll
M llvm/test/Transforms/LoopDeletion/pr53969.ll
M llvm/test/Transforms/LoopDeletion/simplify-then-delete.ll
M llvm/test/Transforms/LoopIdiom/non-canonical-loop.ll
M llvm/test/Transforms/LoopIdiom/scev-invalidation_topmostloop.ll
A llvm/test/Transforms/LoopInterchange/bail-out-one-loop.ll
A llvm/test/Transforms/LoopInterchange/call-instructions-remarks.ll
M llvm/test/Transforms/LoopInterchange/call-instructions.ll
A llvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar-remark.ll
M llvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
M llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
M llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
M llvm/test/Transforms/LoopInterchange/interchange-no-deps.ll
M llvm/test/Transforms/LoopInterchange/interchanged-loop-nest-3.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-dependencies-1.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-loop-nest-3.ll
M llvm/test/Transforms/LoopInterchange/not-interchanged-tightly-nested.ll
A llvm/test/Transforms/LoopInterchange/unique-dep-matrix.ll
M llvm/test/Transforms/LoopVectorize/AArch64/aarch64-predication.ll
M llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-no-scalarization-required.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/maximize-bandwidth-invalidate.ll
A llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-fp-ext-trunc-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-vscale-tune.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
M llvm/test/Transforms/LoopVectorize/X86/fneg-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/mul_slm_16bit.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
M llvm/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
A llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
A llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
A llvm/test/tools/llvm-mca/AMDGPU/gfx950.s
A llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx512vl.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s
M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vl.s
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx950.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-exegesis/lib/X86/Target.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/Analysis/InlineAdvisorPlugin/InlineAdvisorPlugin.cpp
M llvm/unittests/Analysis/PluginInlineAdvisorAnalysisTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
M llvm/unittests/TextAPI/TextStubV5Tests.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SchedulerTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/X86ManualFoldTables.def
M llvm/utils/TableGen/X86ManualInstrMapping.def
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M mlir/docs/Bufferization.md
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Affine/Utils.h
M mlir/include/mlir/Dialect/Func/Transforms/Passes.h
M mlir/include/mlir/Dialect/Func/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Interfaces/TilingInterface.td
M mlir/lib/Bindings/Python/DialectQuant.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOps.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Func/Transforms/CMakeLists.txt
R mlir/lib/Dialect/Func/Transforms/FuncBufferize.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.h
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/dialects/quant.pyi
M mlir/python/mlir/extras/types.py
M mlir/test/CAPI/execution_engine.c
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir
M mlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Affine/affine-expand-index-ops.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/invalid.mlir
R mlir/test/Dialect/Func/func-bufferize.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-pack-tile.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-pack.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-unpack-tile.mlir
A mlir/test/Dialect/Linalg/decompose-tensor-unpack.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-pack.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-unpack-tile.mlir
R mlir/test/Dialect/Linalg/generalize-tensor-unpack.mlir
A mlir/test/Dialect/Linalg/td/decompose-pack.mlir
R mlir/test/Dialect/Linalg/td/generalize-pack.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/Dialect/SPIRV/IR/structure-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/abi-load-store.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
M mlir/test/Dialect/SPIRV/Transforms/layout-decoration.mlir
M mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
M mlir/test/Dialect/Transform/test-pass-application.mlir
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir
M mlir/test/Dialect/Vector/vector-emulate-narrow-type.mlir
M mlir/test/Dialect/Vector/vector-transforms.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/Integration/Dialect/MemRef/verify-memref.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/Target/SPIRV/array-two-step-roundtrip.mlir
M mlir/test/Target/SPIRV/array.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/global-variable.mlir
M mlir/test/Target/SPIRV/loop.mlir
M mlir/test/Target/SPIRV/matrix.mlir
M mlir/test/Target/SPIRV/memory-ops.mlir
M mlir/test/Target/SPIRV/physical-storage-buffer.mlir
M mlir/test/Target/SPIRV/undef.mlir
M mlir/test/lib/Dialect/Linalg/TestLinalgTransforms.cpp
M mlir/test/mlir-cpu-runner/simple.mlir
M mlir/test/python/dialects/affine.py
M mlir/test/python/dialects/quant.py
M mlir/test/python/ir/builtin_types.py
M mlir/test/python/ir/value.py
M mlir/unittests/ExecutionEngine/Invoke.cpp
M offload/DeviceRTL/CMakeLists.txt
M offload/plugins-nextgen/common/src/JIT.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
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