[all-commits] [llvm/llvm-project] 8234c6: [LoongArch] Record the special AMO operand constra...

[WÁNG Xuěruì via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8234c612eda1cdff702f5ede1d7db7baf3bf0e47
      https://github.com/llvm/llvm-project/commit/8234c612eda1cdff702f5ede1d7db7baf3bf0e47
  Author: WÁNG Xuěruì <git at xen0n.name>
  Date:   2024-11-20 (Wed, 20 Nov 2024)

  Changed paths:
    M llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
    M llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
    M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
    M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h
    M llvm/test/MC/LoongArch/Basic/Integer/invalid64.s

  Log Message:
  -----------
  [LoongArch] Record the special AMO operand constraint with TableGen (#114398)

Depends on #114508

The LoongArch Reference Manual says that the 3-register atomic memory
operations cannot have their rd equal to either rj or rk [^1], and both
GNU as and LLVM IAS enforce the constraint for non-zero rd. However,
currently LoongArch AsmParser is checking for the opcode with a direct
numerical comparison on the opcode, which is enum-typed: the fact that
all AMO insns have adjacent numerical values is merely a coincidence,
and it is better to not rely on the current TableGen implementation
behavior.

Instead, start to leverage the target-specific flags field of
MCInstrDesc, and record the constraint with TableGen, so we can stop
treating the opcode value as number. In doing so, we also have to mark
whether the instruction is AMCAS, because the operand index of rj and rk
for the AMCAS instructions is different.

While documenting the new flag, it was found that v1.10 of the Manual
did not specify the similar constraint for the AMCAS instructions.
Experiments were done on a Loongson 3A6000 (LA664 uarch) and it turned
out that at least AMCAS will still signal INE with `rd == rj`. The `rd
== rk` case should be a no-op according to the semantics, but as it is
meaningless to perform CAS with the "old value" same as the "new value",
it is not worth special-casing. So the current behavior of also
enforcing the constraint for AMCAS is kept.

[^1]: if `rd == rj` an INE would be signaled; if `rd == rk` it is UB.



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