[all-commits] [llvm/llvm-project] 41c86c: [RISCV] Add TT-Ascalon-d8 processor (#115100)

[Petr Penzin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41c86ca714a68eea8c73cf57fba28718d466660b
      https://github.com/llvm/llvm-project/commit/41c86ca714a68eea8c73cf57fba28718d466660b
  Author: Petr Penzin <penzin.dev at gmail.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add TT-Ascalon-d8 processor (#115100)

Ascalon is an out-of-order CPU core from Tenstorrent. Overview:
https://tenstorrent.com/ip/tt-ascalon

Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be
added in a separate PR.

---------

Co-authored-by: Anton Blanchard <antonb at tenstorrent.com>



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