[all-commits] [llvm/llvm-project] 565a9a: [SPIR-V] Disable Machine Sink pass in SPIR-V Backe...

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 565a9ac7df3815ed038938942be4cf1471de4755
      https://github.com/llvm/llvm-project/commit/565a9ac7df3815ed038938942be4cf1471de4755
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-11-19 (Tue, 19 Nov 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

  Log Message:
  -----------
  [SPIR-V] Disable Machine Sink pass in SPIR-V Backend (#116060)

Some standard passes that optimize machine instructions in SSA form uses
MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
break the CFG. MachineSink is among such passes (see for example
https://github.com/llvm/llvm-project/blob/1884ffc41c20b1e08b30eef4e8ebbcc54543a139/llvm/lib/CodeGen/MachineSink.cpp#L630),
so this PR disables the pass to ensure correctness of the generated
code.

There is a reproducer of the issue that demonstrates how MachineSink is
able to generate an invalid code for the SPIR-V Backend

```
error: line 6837: OpPhi must appear within a non-entry block before all non-OpPhi instructions (except for OpLine, which can be mixed with OpPhi).
  %z_fra_3_1 = OpPhi %uint %and187 %4250 %inc194 %4257 %uint_0 %4264
```

The reproducer is a part of SYCL end-to-end test suite
(https://github.com/intel/llvm/blob/sycl/sycl/test-e2e/DeviceLib/imf_fp32_rounding_test.cpp).
At the moment it doesn't seem feasible to make it a part of the SPIR-V
Backend test suite due to a far too big size of the intermediate LLVM IR
that causes the problem.



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