[all-commits] [llvm/llvm-project] 900c05: [RISCV] Add an implementation of findRepresentativ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 900c0565314618ec142b020cea1f9c86e2f8282b
      https://github.com/llvm/llvm-project/commit/900c0565314618ec142b020cea1f9c86e2f8282b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-18 (Mon, 18 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h

  Log Message:
  -----------
  [RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64. (#116165)

This is an alternative fix for #81192. This allows the SelectionDAG
scheduler to be able to find a representative register class for i32 on
RV64. The representative register class is the super register class with
the largest spill size that is also legal. The default implementation of
findRepresentativeClass only works for legal types which i32 is not for
RV64.

I did some investigation of why tablegen uses i32 in output patterns on
RV64. It appears it comes down to a function called
ForceArbitraryInstResultType that picks a type for the output
pattern when the isel pattern isn't specific enough. I believe it picks
the smallest type(lowested numbered) to resolve the conflict.

A similar issue occurs for f16 and bf16 which both use the FPR16
register class. If the isel pattern doesn't specify, tablegen may find
both f16 and bf16 and may pick bf16 from Zfh pattern when Zfbfmin isn't
present. Since bf16 isn't legal in that case, findRepresentativeClass
will fail.

For i8, i16, i32, this patch calls the base class with XLenVT to get the
representative class since XLenVT is always legal.

For bf16/f16, we call the base class with f32 since all of the f16/bf16
extensions depend on either F or Zfinx which will make f32 a legal type.
The final representative register class further depends on whether D or
Zdinx is also enabled, but that should be handled by the default
implementation.



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