[all-commits] [llvm/llvm-project] 9d7026: [RISCV] Correct the precedence in isVRegClass (#11...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d7026500df1023cee67c5bd10119e1ca9805241
      https://github.com/llvm/llvm-project/commit/9d7026500df1023cee67c5bd10119e1ca9805241
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-11-18 (Mon, 18 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h

  Log Message:
  -----------
  [RISCV] Correct the precedence in isVRegClass (#116579)

Right shift has higher precedence than bitwise and, so it should be
parentheses around & operator. This case works as expected because
IsVRegClassShift is 0, other cases will fail.



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