[all-commits] [llvm/llvm-project] eed9af: [RISCV][GISel] Make loads/stores with s16 register...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eed9af95e6133e94449c7be585bc3b5fad8ad769
      https://github.com/llvm/llvm-project/commit/eed9af95e6133e94449c7be585bc3b5fad8ad769
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-17 (Sun, 17 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.

This is needed to support Zfh loads/stores.

This requires supporting extends from sext/zext form i16 and s16
G_FREEZE to support the current tests we have.



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