[all-commits] [llvm/llvm-project] 6a0905: [RISCV][GISel] Add isel patterns for i16 load/stor...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a0905d11ede27f2ac52338dc9d4bcd5c6e8a2f5
      https://github.com/llvm/llvm-project/commit/6a0905d11ede27f2ac52338dc9d4bcd5c6e8a2f5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Add isel patterns for i16 load/store (#116293)

In order to support f16 load/store we need to make load/stores with s16
register type legal. If regbank selection doesn't pick the FPR bank,
we'll be left with a GPR load or store which we don't have isel patterns
for from SelectionDAG.

In order to add the patterns we need to make i16 a legal type for the
GPR register class.

Tests are currently disabling the legality check because I haven't
update the legalizer yet.



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