[all-commits] [llvm/llvm-project] 40afff: [mlir][LLVM] Add disjoint flag (#115855)

[lfrenot via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40afff7bd95090a75bc68a0d26b8017cc0ae65c1
      https://github.com/llvm/llvm-project/commit/40afff7bd95090a75bc68a0d26b8017cc0ae65c1
  Author: lfrenot <leon.frenot at ens-lyon.fr>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
    M mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
    M mlir/lib/Target/LLVMIR/ModuleImport.cpp
    M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
    M mlir/test/Dialect/LLVMIR/roundtrip.mlir
    A mlir/test/Target/LLVMIR/Import/disjoint.ll
    A mlir/test/Target/LLVMIR/disjoint.mlir

  Log Message:
  -----------
  [mlir][LLVM] Add disjoint flag (#115855)

The implementation is mostly based on the one existing for the exact
flag.

disjoint means that for each bit, that bit is zero in at least one of
the inputs. This allows the Or to be treated as an Add since no carry
can occur from any bit. If the disjoint keyword is present, the result
value of the or is a [poison
value](https://llvm.org/docs/LangRef.html#poisonvalues) if both inputs
have a one in the same bit position. For vectors, only the element
containing the bit is poison.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications