[all-commits] [llvm/llvm-project] 4e1db6: [AArch64][SVE] Add AArch64ISD nodes for wide add i...

[James Chesterman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e1db6a318775d9d0c49357baea6ca02fe5b5389
      https://github.com/llvm/llvm-project/commit/4e1db6a318775d9d0c49357baea6ca02fe5b5389
  Author: James Chesterman <James.Chesterman at arm.com>
  Date:   2024-11-15 (Fri, 15 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

  Log Message:
  -----------
  [AArch64][SVE] Add AArch64ISD nodes for wide add instructions (#115895)

When lowering from a partial reduction to a pair of wide adds,
previously the corresponding intrinsics were returned as nodes. Now
there are AArch64ISD nodes that are returned.



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