[all-commits] [llvm/llvm-project] 6d91d7: [RISCV][NFC] Split branch-relaxation test
Paul Kirth via All-commits
all-commits at lists.llvm.org
Thu Nov 14 09:39:03 PST 2024
Branch: refs/heads/users/ilovepi/spr/libcxxabi-always-link-against-libzircon-for-fuchsia-targets
Home: https://github.com/llvm/llvm-project
Commit: 6d91d7ce6aeb46d948a5a476909825b71b0c84a2
https://github.com/llvm/llvm-project/commit/6d91d7ce6aeb46d948a5a476909825b71b0c84a2
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll
A llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll
R llvm/test/CodeGen/RISCV/branch-relaxation.ll
Log Message:
-----------
[RISCV][NFC] Split branch-relaxation test
This change splits the llvm/test/CodeGen/RISCV/branch-relaxation.ll test
which contained comments saying that different test functions were valid
or not on rv32/rv64. Not only was this confusing, but the inline
assembly in the test was being passed values wider than xlen on rv32.
Commit: 06e08696248ac01754c87c22cc8a4b797ef46430
https://github.com/llvm/llvm-project/commit/06e08696248ac01754c87c22cc8a4b797ef46430
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Profile/YAMLProfileWriter.cpp
Log Message:
-----------
[BOLT] Fix warnings
This patch fixes:
bolt/lib/Profile/StaleProfileMatching.cpp:694:24: error: unused
variable 'BinHash' [-Werror,-Wunused-variable]
bolt/lib/Profile/YAMLProfileWriter.cpp:206:61: error: missing field
'GUID' initializer [-Werror,-Wmissing-field-initializers]
bolt/lib/Profile/YAMLProfileReader.cpp:840:16: error: unused
variable 'MatchedWithPseudoProbes' [-Werror,-Wunused-variable]
Commit: 2c6424e691e32f79bc303203deb1c91634d62286
https://github.com/llvm/llvm-project/commit/2c6424e691e32f79bc303203deb1c91634d62286
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Ignore trivial functions and [[clang::noescape]]. (#114897)
This PR makes webkit.UncountedLambdaCapturesChecker ignore trivial
functions as well as the one being passed to an argument with
[[clang::noescape]] attribute. This dramatically reduces the false
positive rate for this checker.
To do this, this PR replaces VisitLambdaExpr in favor of checking
lambdas via VisitDeclRefExpr and VisitCallExpr. The idea is that if a
lambda is defined but never called or stored somewhere, then capturing
whatever variable in such a lambda is harmless.
VisitCallExpr explicitly looks for direct invocation of lambdas and
registers its DeclRefExpr to be ignored in VisitDeclRefExpr. If a lambda
is being passed to a function, it checks whether its argument is
annotated with [[clang::noescape]]. If it's not annotated such, it
checks captures for their safety.
Because WTF::switchOn could not be annotated with [[clang::noescape]] as
function type parameters are variadic template function so we hard-code
this function into the checker.
In order to check whether "this" pointer is ref-counted type or not, we
override TraverseDecl and record the most recent method's declaration.
In addition, this PR fixes a bug in isUnsafePtr that it was erroneously
checking whether std::nullopt was returned by isUncounted and
isUnchecked as opposed to the actual boolean value.
Finally, this PR also converts the accompanying test to use -verify and
adds a bunch of tests.
Commit: 789de766b5fc9c8ffa6e808a8baf0e585ac2e818
https://github.com/llvm/llvm-project/commit/789de766b5fc9c8ffa6e808a8baf0e585ac2e818
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Object/ELF.cpp
Log Message:
-----------
[NFC,SHT_LLVM_BB_ADDR_MAP] Fix undefined behaviour in ELF.cpp. (#115830)
`BBEntries` is defined outside of the loop and is used after move which
is undefined behavior.
Commit: b8d6659bff25458693c99a7c53372afcf6d66d7d
https://github.com/llvm/llvm-project/commit/b8d6659bff25458693c99a7c53372afcf6d66d7d
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
A llvm/test/CodeGen/AArch64/block-placement-optimize-branches.ll
M llvm/test/CodeGen/X86/conditional-tailcall.ll
Log Message:
-----------
[CodeLayout] Do not flip branch condition when using optsize (#114607)
* Do not use profile data when flipping a branch condition when
optimizing for size. This should improving outlining and ICF due to more
uniform instruction sequences.
* Refactor `optimizeBranches()` to use early `continue`s
* Use the correct debug location for `insertBranch()`
Commit: 57c33acac8c74eb071ede35d819918d8bd00e45b
https://github.com/llvm/llvm-project/commit/57c33acac8c74eb071ede35d819918d8bd00e45b
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/test/CodeGen/X86/sink-blockfreq.ll
Log Message:
-----------
[MachineSink] Sink into consistent blocks for optsize funcs (#115367)
Do not consider profile data when choosing a successor block to sink
into for optsize functions. This should result in more consistent
instruction sequences which will improve outlining and ICF. We've
observed a slight codesize improvement in a large binary. This is
similar reasoning to https://github.com/llvm/llvm-project/pull/114607.
Using profile data to select a block to sink into was original added in
https://github.com/llvm/llvm-project/commit/d04f7596e79d7c5cf7e4249ad62690afaecd01ec.
Commit: ae7392bf5c5d4c34c901ba4f472282206e68bf7b
https://github.com/llvm/llvm-project/commit/ae7392bf5c5d4c34c901ba4f472282206e68bf7b
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
A clang/test/Analysis/store-dump-orders.cpp
Log Message:
-----------
Reapply "[analyzer][NFC] Make RegionStore dumps deterministic" (#115884)
This is reapplies #115615 without using tuples. The eager call of
`getRegion()` and `getOffset()` could cause crashes when the Store had
symbolic bindings.
Here I'm fixing the crash by lazily calling those getters.
Also, the tuple version poorly sorted the Clusters. The memory spaces
should have come before the regular clusters.
Now, that is also fixed here, demonstrated by the test.
Commit: 1791b25f43f4e6a0b21284ce8076cfab160cb61a
https://github.com/llvm/llvm-project/commit/1791b25f43f4e6a0b21284ce8076cfab160cb61a
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[clang][CIR] Change buildX functions to emitX (#115568)
The buildX naming convention originated when the CIRGen implementation
was planned to be substantially different from original CodeGen. CIRGen
is now a much closer adaption of CodeGen, and the emitX to buildX
renaming just makes things more confusing, since CodeGen also has some
helper functions whose names start with build or Build, so it's not
immediately clear which CodeGen function corresponds to a CIRGen buildX
function. Rename the buildX functions back to emitX to fix this.
Commit: 2b5b57c5cf78af66b5b9f514c4b51b4adc9a80df
https://github.com/llvm/llvm-project/commit/2b5b57c5cf78af66b5b9f514c4b51b4adc9a80df
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
Log Message:
-----------
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
Currently all implicit-def instructions are part of
bb prolog. We should only include the wwm-register's
implicit definitions into the BB prolog. The other
vector class registers' implicit defs when exist at
the bb top might cause interference when pushed the
LR_split copy insertion downwards. The SplitKit is
very strict on altering the insertion points and will
assert such instances.
Commit: 3431d133ccfa75d16964be455238e2a1da0c2004
https://github.com/llvm/llvm-project/commit/3431d133ccfa75d16964be455238e2a1da0c2004
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Implement instruction cost for vp.reduce.* #114184
The VP variants simply return the same costs as the non-VP variants.
This assumes that reductions are VL predicated, and that VL predication
has no additional cost.
Commit: 853d52b8384951167214f81066e316d78f389c28
https://github.com/llvm/llvm-project/commit/853d52b8384951167214f81066e316d78f389c28
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Support derived type in cuf.data_transfer conversion (#115557)
Support derived type in `cuf.data_transfer` conversion by computing
their size in bytes.
Commit: dfb864a735da9153ab8a4bb107d4b01ac81ee364
https://github.com/llvm/llvm-project/commit/dfb864a735da9153ab8a4bb107d4b01ac81ee364
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115810)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
This patch introduces alias:
using DiagsInGroup = std::map<std::string, GroupInfo, std::less<>>;
because the raw type is a bit mouthful.
Commit: c784d321d90a3609caeacfb525b7ccadd41a5195
https://github.com/llvm/llvm-project/commit/c784d321d90a3609caeacfb525b7ccadd41a5195
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
Log Message:
-----------
[ThinLTO] Use heterogenous lookups with std::map (NFC) (#115812)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 4048c64306e23b622443bbe7293057a9b07a13bb
https://github.com/llvm/llvm-project/commit/4048c64306e23b622443bbe7293057a9b07a13bb
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/DWARFEmitter.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
Log Message:
-----------
[llvm] Remove redundant control flow statements (NFC) (#115831)
Identified with readability-redundant-control-flow.
Commit: a93cbd4e762799206ae6e6c45f4a7d0da7e56513
https://github.com/llvm/llvm-project/commit/a93cbd4e762799206ae6e6c45f4a7d0da7e56513
Author: Finn Plummer <50529406+inbelic at users.noreply.github.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
Log Message:
-----------
[SPIRV] Audit `select` Result in SPIRVInstructionSelector (#115193)
- as per the definition of `select` in GlobalISel/InstructionSelector.h
the return value is a boolean denoting if the select was successful
- doing `Result |=` is incorrect as all inserted instructions should be
succesful, hence we change to using `Result &=`
- ensure that the return value of all BuildMI instructions are
propagated correctly
Commit: 13ced90b007fdab3d0ecbe032ead2650d3e7717e
https://github.com/llvm/llvm-project/commit/13ced90b007fdab3d0ecbe032ead2650d3e7717e
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
M libc/include/llvm-libc-types/stdfix-types.h
Log Message:
-----------
[libc] {u}lkbits broken on riscv32 (#115799)
- Re-enabled ulkbits and lkbits for Risc-V
- Bumped `int_lk_t` to a `signed long long` and a `uint_ulk_t` to an
`unsigned long long` to guarantee they both fit in 8 bytes, which `long
_Accum` and `unsigned long _Accum` are defaulted to on 32bit
architectures.
This is probably inconvenient on systems that have a word size larger
than 64 bits?
#115778
Commit: c284326755b446c811d2bf0ee5f461b493ebf920
https://github.com/llvm/llvm-project/commit/c284326755b446c811d2bf0ee5f461b493ebf920
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/test/src/__support/CMakeLists.txt
Log Message:
-----------
[libc] Disable block test on AMDGPU as well
Summary:
Recently started failing on AMDGPU as well, will disable until I can
bisect it.
Commit: aaa37d6755e635bbd62ba58896acd54ceef64610
https://github.com/llvm/llvm-project/commit/aaa37d6755e635bbd62ba58896acd54ceef64610
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/Target/PowerPC/CMakeLists.txt
M llvm/lib/Target/PowerPC/PPC.h
R llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-used-with-stringpool.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
M llvm/test/CodeGen/PowerPC/licm-remat.ll
M llvm/test/CodeGen/PowerPC/merge-private.ll
R llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir
M llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll
R llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir
M llvm/test/CodeGen/PowerPC/mergeable-string-pool-pr92991.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool-tls.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
M llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll
M llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
Log Message:
-----------
[PPC] Replace PPCMergeStringPool with GlobalMerge for Linux (#114850)
Enable merging all constants without looking at use in GlobalMerge by
default to replace PPCMergeStringPool pass on Linux.
Commit: ba572abeb4fa698d04222877d10d1c547b6c2c01
https://github.com/llvm/llvm-project/commit/ba572abeb4fa698d04222877d10d1c547b6c2c01
Author: Steven Perron <stevenperron at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll
R llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
Log Message:
-----------
[SPIRV] Add reads from image buffer for shaders. (#115178)
This commit adds an intrinsic that will read from an image buffer. We
chose to match the name of the DXIL intrinsic for simplicity in clang.
We cannot reuse the existing openCL readimage function because that is
not a reserved name in HLSL.
I considered trying to refactor generateReadImageInst, so that we could
share code between the two implementations. However, most of the code in
generateReadImageInst is concerned with trying to figure out which type
of image read is being done. Once we factor out the code that will be
common, then we end up with just a single call to the MIRBuilder being
common.
Commit: e458434ebe87f890db0d4a03bbc3de30f3d052b9
https://github.com/llvm/llvm-project/commit/e458434ebe87f890db0d4a03bbc3de30f3d052b9
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
A mlir/test/Dialect/Vector/emulate-narrow-type-unsupported.mlir
M mlir/test/lib/Dialect/MemRef/TestEmulateNarrowType.cpp
Log Message:
-----------
[mlir][vector] Restrict narrow-type-emulation patterns (#115612)
All patterns in populateVectorNarrowTypeEmulationPatterns currently
assume a 1-D vector load/store rather than an n-D vector load/store.
This assumption is evident in ConvertVectorTransferRead, for example,
here (extracted from `ConvertVectorTransferRead`):
```cpp
auto newRead = rewriter.create<vector::TransferReadOp>(
loc, VectorType::get(numElements, newElementType), adaptor.getSource(),
getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices),
newPadding);
auto bitCast = rewriter.create<vector::BitCastOp>(
loc, VectorType::get(numElements * scale, oldElementType), newRead);
```
Both invocations of `VectorType::get()` here generate a 1-D vector.
Attempts to use these patterns with more generic cases, such as 2-D
vectors, fail. For example, trying to cast the following 2-D case to
`i32`:
```mlir
func.func @vector_maskedload_2d_i8_negative(
%idx1: index,
%idx2: index,
%num_elems: index,
%passthru: vector<2x4xi8>) -> vector<2x4xi8> {
%0 = memref.alloc() : memref<3x4xi8>
%mask = vector.create_mask %num_elems, %num_elems : vector<2x4xi1>
%1 = vector.maskedload %0[%idx1, %idx2], %mask, %passthru :
memref<3x4xi8>, vector<2x4xi1>, vector<2x4xi8> into vector<2x4xi8>
return %1 : vector<2x4xi8>
}
```
For example, casting to i32 produces:
```bash
error: 'vector.bitcast' op failed to verify that all of {source, result} have same rank
%1 = vector.maskedload %0[%idx1, %idx2], %mask, %passthru :
^
```
Instead of reworking these patterns (that's going to require much more
effort), I’ve marked them as 1-D only and extended
"TestEmulateNarrowTypePass" with an option to disable the Memref type
converter - that's to be able to add negative tests (otherwise, the type
converter throws an error we can't really test for). While not ideal,
this workaround should suit a test pass.
Commit: 7ebfbf9c87941315d7c9ca84d1b22acf2a5bd14d
https://github.com/llvm/llvm-project/commit/7ebfbf9c87941315d7c9ca84d1b22acf2a5bd14d
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir
M mlir/test/Dialect/Linalg/generalize-tensor-pack.mlir
Log Message:
-----------
[mlir][tensor] Update `GeneralizeOuterUnitDimsPackOpPattern` (#115312)
Avoid generating spurious tensor.extract_slice, follow-on for #114315.
This is best to demonstrate with an example. Here's input for
`GeneralizeOuterUnitDimsPackOpPattern`:
```mlir
%pack = tensor.pack %input
padding_value(%pad : f32)
inner_dims_pos = [1, 0]
inner_tiles = [2, %tile_dim_1]
into %output : tensor<5x1xf32> -> tensor<1x1x2x?xf32>
```
Output _before_:
```mlir
%padded = tensor.pad %arg0 low[0, 0] high[%0, 1] {
^bb0(%arg4: index, %arg5: index):
tensor.yield %arg2 : f32
} : tensor<5x1xf32> to tensor<?x2xf32>
// NOTE: skipped in the output _after_
%extracted_slice = tensor.extract_slice
%padded[0, 0] [%arg3, 2] [1, 1] :
tensor<?x2xf32> to tensor<?x2xf32>
%empty = tensor.empty(%arg3) : tensor<2x?xf32>
%transposed = linalg.transpose
ins(%extracted_slice : tensor<?x2xf32>)
outs(%empty : tensor<2x?xf32>)
permutation = [1, 0]
%inserted_slice = tensor.insert_slice %transposed=
into %arg1[0, 0, 0, 0] [1, 1, 2, %arg3] [1, 1, 1, 1] :
tensor<2x?xf32> into tensor<1x1x2x?xf32>
```
Output _after_:
```mlir
%padded = tensor.pad %arg0 low[0, 0] high[%0, 1] {
^bb0(%arg4: index, %arg5: index):
tensor.yield %arg2 : f32
} : tensor<5x1xf32> to tensor<?x2xf32>
%empty = tensor.empty(%arg3) : tensor<2x?xf32>
%transposed = linalg.transpose
ins(%padded : tensor<?x2xf32>)
outs(%empty : tensor<2x?xf32>) permutation = [1, 0]
%inserted_slice = tensor.insert_slice %transposed
into %arg1[0, 0, 0, 0] [1, 1, 2, %arg3] [1, 1, 1, 1] :
tensor<2x?xf32> into tensor<1x1x2x?xf32>
```
This PR also adds a check to verify that only the last N trailing
dimensions are tiled (for some value of N). Based on the PR
discussion, this restriction seems reasonable - especially as there
are no in-tree tests requiring otherwise. For now, it also simplifies
the computation of permutations for linalg.transpose. This
restriction can be relaxed in the future if needed.
Commit: f6795e6b4f619cbecc59a92f7e5fad7ca90ece54
https://github.com/llvm/llvm-project/commit/f6795e6b4f619cbecc59a92f7e5fad7ca90ece54
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
Log Message:
-----------
[CodeExtractor] Refactor extractCodeRegion, fix alloca emission. (#114419)
Reorganize the code into phases:
* Analyze/normalize
* Create extracted function prototype
* Generate the new function's implementation
* Generate call to new function
* Connect call to original function's CFG
The motivation is #114669 to optionally clone the selected code region
into the new function instead of moving it. The current structure made
it difficult to add such functionality since there was no obvious place
to do so, not made easier by some functions doing more than their name
suggests. For instance, constructFunction modifies code outside the
constructed function, but also function properties such as
setPersonalityFn are derived somewhere else. Another example is
emitCallAndSwitchStatement, which despite its name also inserts stores
for output parameters.
Many operations also implicitly depend on the order they are applied
which this patch tries to reduce. For instance, ExtractedFuncRetVals
becomes the list exit blocks which also defines the return value when
leaving via that block. It is computed early such that the new
function's return instructions and the switch can be generated
independently. Also, ExtractedFuncRetVals is combining the lists
ExitBlocks and OldTargets which were not always kept consistent with
each other or NumExitBlocks. The method recomputeExitBlocks() will
update it when necessary.
The coding style partially contradict the current coding standard. For
instance some local variable start with lower case letters. I updated
some, but not all occurrences to make the diff match at least some lines
as unchanged.
The patch [D96854](https://reviews.llvm.org/D96854) introduced some
confusion of function argument indexes this is fixed here as well, hence
the patch is not NFC anymore. Tested in modified CodeExtractorTest.cpp.
Patch [D121061](https://reviews.llvm.org/D121061) introduced
AllocationBlock, but not all allocas were inserted there.
Efectively includes the following fixes:
1. https://github.com/llvm/llvm-project/commit/ce73b1672a6053d5974dc2342881aac02efe2dbb
2. https://github.com/llvm/llvm-project/commit/4aaa92578686176243a294eeb2ca5697a99edcaa
3. Missing allocas, still unfixed
Originally submitted as https://reviews.llvm.org/D115218
Commit: 30753afc2a3171e962e261622781852a01fbec72
https://github.com/llvm/llvm-project/commit/30753afc2a3171e962e261622781852a01fbec72
Author: PikachuHy <pikachuhy at linux.alibaba.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
M mlir/test/Dialect/LLVMIR/sroa-intrinsics.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][llvm] Add support for memset.inline (#115711)
support `llvm.intr.memset.inline` in llvm-project repo before we add
support for `__builtin_memset_inline` in clangir
cc @bcardosolopes
Commit: 3ab5927b971c2cf758c68d36200ef8ec97916034
https://github.com/llvm/llvm-project/commit/3ab5927b971c2cf758c68d36200ef8ec97916034
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/CommentCommands.td
M clang/test/AST/ast-dump-comment.cpp
Log Message:
-----------
[Clang][Comments] Make @relates an inline comment command (#115040)
According to the Doxygen documentation,
the `relates`, `related`, `relatesalso`, and `relatedalso` commands all
have a single argument. This patch changes their classification from
`VerbatimLineCommand` to `InlineCommand` so the argument is correctly
parsed.
Commit: be89e794f782cb252183446967447239f80c8f9d
https://github.com/llvm/llvm-project/commit/be89e794f782cb252183446967447239f80c8f9d
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/veneer-lld-abs.s
Log Message:
-----------
[BOLT][AArch64] Add support for long absolute LLD thunks/veneers (#113408)
Absolute thunks generated by LLD reference function addresses recorded
as data in code. Since they are generated by the linker, they don't have
relocations associated with them and thus the addresses are left
undetected. Use pattern matching to detect such thunks and handle them
in VeneerElimination pass.
Commit: d922045381347a9d5c7301bf870ee0482bfdf0d4
https://github.com/llvm/llvm-project/commit/d922045381347a9d5c7301bf870ee0482bfdf0d4
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M bolt/lib/Core/Exceptions.cpp
Log Message:
-----------
[BOLT] Use AsmInfo for address size. NFCI (#115932)
Use AsmInfo instead of DWARFObj interface for extracting address size
and format.
Commit: 70d6789c7a95c87bbe24b61a3fca8272060b290e
https://github.com/llvm/llvm-project/commit/70d6789c7a95c87bbe24b61a3fca8272060b290e
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
[bazel] Port for 7302c8dbe71b7c03b73a35a21fa4b415fa1f4505
Commit: 5cd6e21bddb882150068ea1c94e7b35c11f515be
https://github.com/llvm/llvm-project/commit/5cd6e21bddb882150068ea1c94e7b35c11f515be
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/LTO.cpp
M lld/COFF/Options.td
M lld/docs/ReleaseNotes.rst
A lld/test/COFF/savetemps-colon.ll
Log Message:
-----------
[LLD][COFF] allow saving intermediate files with /lldsavetemps (#115131)
* Parity with the `-save-temps=` flag in the `ELF` `lld` driver.
Commit: 014455a58762331b8eb7962c60bd64168c49f3b4
https://github.com/llvm/llvm-project/commit/014455a58762331b8eb7962c60bd64168c49f3b4
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
A llvm/test/CodeGen/X86/sincos-stack-args.ll
Log Message:
-----------
[SDAG] Limit sincos/frexp stack slot folding to stores chained to entry (#115906)
When the chain is not the entry node there is a risk the stores are
within a (CALLSEQ_START, CALLSEQ_END), which when the node is expanded
will lead to nested call sequences.
It should be possible to check for this and allow more cases, but for
now, let's limit this to cases where it's definitely safe.
Fixes #115323
Commit: 6aa74038588ed47e3fc0d829c1e7538cc110ba39
https://github.com/llvm/llvm-project/commit/6aa74038588ed47e3fc0d829c1e7538cc110ba39
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/test/src/__support/FPUtil/fpbits_test.cpp
Log Message:
-----------
[libc] Fix fpbits test running 80bit ld everywhere (#115937)
After #115084 the 80 bit long double tests error if sizeof(long double)
isn't 96 or 128 bits. This caused failures in long double is double
systems (since long double is 64 bits) so I've disabled the 80 bit long
double tests on systems that don't use them.
Commit: 4bd6e15a4580d9514819b80af7e5875ae696759c
https://github.com/llvm/llvm-project/commit/4bd6e15a4580d9514819b80af7e5875ae696759c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
Log Message:
-----------
[RISCV][GISel] Sync MaxIterations/ObserverLvl/EnableFullDCE for PreLegalizer combiners with AArch64.
Commit: 5b67372aeca9cac3bad81dd7eac173f163c7c77c
https://github.com/llvm/llvm-project/commit/5b67372aeca9cac3bad81dd7eac173f163c7c77c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libcxx/include/__algorithm/find_end.h
Log Message:
-----------
[libc++] Remove a few unused includes from <__algorithm/find_end.h>
Commit: e5ba11727437456fbab7ce733c07843bf682fa0c
https://github.com/llvm/llvm-project/commit/e5ba11727437456fbab7ce733c07843bf682fa0c
Author: John Harrison <harjohn at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/LLDBUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Remove `g_dap` references from lldb-dap/LLDBUtils. (#115933)
This refactor removes g_dap references from lldb-dap/LLDBUtils.{h,cpp}
to allow us to create more than one g_dap instance in the future.
Commit: f5396748c7da3d9f278fcd42e2a10a3214920d82
https://github.com/llvm/llvm-project/commit/f5396748c7da3d9f278fcd42e2a10a3214920d82
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
A clang/test/Driver/time.c
A flang/test/Driver/time.f90
Log Message:
-----------
[clang][flang] Support -time in both clang and flang
The -time option prints timing information for the subcommands
(compiler, linker) in a format similar to that used by gcc/gfortran.
This partially addresses requests from #89888
Commit: 5c2a133b1342881dc4f42a896e7e5f4b85d20508
https://github.com/llvm/llvm-project/commit/5c2a133b1342881dc4f42a896e7e5f4b85d20508
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/X86/math-builtins.c
M clang/test/CodeGen/constrained-math-builtins.c
M clang/test/CodeGen/libcalls.c
M clang/test/CodeGen/math-libcalls.c
M clang/test/CodeGenCXX/builtin-calling-conv.cpp
M clang/test/CodeGenOpenCL/builtins-f16.cl
M llvm/docs/LangRef.rst
M llvm/test/CodeGen/ARM/fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll
M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
Log Message:
-----------
Emit constrained atan2 intrinsic for clang builtin (#113636)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
- `Builtins.td` - Add f16 support for libm atan2 builtin
- `CGBuiltin.cpp` - Emit constraint atan2 intrinsic for clang builtin
- `clang/test/CodeGenCXX/builtin-calling-conv.cpp` - Use erff instead of
atan2 for clang builtin to lib call calling convention check, now that
atan2 maps to an intrinsic.
- add atan2 cases to llvm.experimental.constrained tests for more
backends: ARM, PowerPC, RISCV, SystemZ.
- LangRef.rst: add llvm.experimental.constrained.atan2, revise
llvm.atan2 description.
Last part of Implement the atan2 HLSL Function. Fixes #70096.
Commit: d2db9bd708f1f1d4368e0b2d3870dd8c307c9895
https://github.com/llvm/llvm-project/commit/d2db9bd708f1f1d4368e0b2d3870dd8c307c9895
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/include/clang/APINotes/Types.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesTypes.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.h
M clang/test/APINotes/swift-import-as.cpp
Log Message:
-----------
[clang][APINotes] Add support for the SwiftEscapable attribute (#115866)
This is similar to SwiftCopyable. Also fix missing SwiftCopyable dump
for TagInfo.
Commit: fe83a7282e05b6aba7c87fa293ec84ef926a7991
https://github.com/llvm/llvm-project/commit/fe83a7282e05b6aba7c87fa293ec84ef926a7991
Author: Peng Sun <peng.sun at arm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
Log Message:
-----------
[TOSA] Introduce Tosa_ElementwiseUnaryOp with Type and Shape Enforcement (#115784)
* Enforce that Tosa_ElementwiseUnaryOp requires output tensors to match
the input tensor's type and shape.
* Update the following ops to conform to Tosa_ElementwiseUnaryOp: clamp,
erf, sigmoid, tanh, cos, sin, abs, bitwise_not, ceil, clz, exp, floor,
log, logical_not, negate, reciprocal, rsqrt.
* Add invalid tests for each operator to ensure compliance with TOSA
v1.0 Specification.
Signed-off-by: Peng Sun <peng.sun at arm.com>
Commit: 49f90e798fe5667ac5e71a796aa897af3185137d
https://github.com/llvm/llvm-project/commit/49f90e798fe5667ac5e71a796aa897af3185137d
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[mlir][affine] Cancel exactly-matching delinearize/linearize pairs (#115758)
If we linearize values (with an assertion tha they are disjoint) and
then delinearize that linear index with th exact same basis, we know
that these operations are exact inverses of each other and can be
replaced with the original inputs to the linearization.
Similarly, if we take a linear index, delinearize it with some bases,
and then re-linearize it with that same basis (noting that the outputs
of the delinearization are guaranteed to by `disjoint`, even if this is
not asserted on the linearize_index operation), the re-linearization is
the inverse of the delinearization, so those two operations can also be
canceled out.
This commit adds canonicalization patterns for these simple
cancelations.
Commit: 36fa8bdfa0130b6233a4ef2b8619702533a9f4df
https://github.com/llvm/llvm-project/commit/36fa8bdfa0130b6233a4ef2b8619702533a9f4df
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libcxx/include/__split_buffer
Log Message:
-----------
[libc++][NFC] Remove unused functions from <__split_buffer> (#115735)
Commit: 24a8092be7c1700e9bcdb15c114e9a738f0a2a6b
https://github.com/llvm/llvm-project/commit/24a8092be7c1700e9bcdb15c114e9a738f0a2a6b
Author: lialan <me at alanli.org>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[MLIR] Avoid `vector.extract_strided_slice` when not needed (#115941)
In `staticallyExtractSubvector`, When the extracting slice is the same
as source vector, do not need to emit `vector.extract_strided_slice`.
This fixes the lit test case `@vector_store_i4` in
`mlir\test\Dialect\Vector\vector-emulate-narrow-type.mlir`, where
converting from `vector<8xi4>` to `vector<4xi8>` does not need slice
extraction.
The issue was introduced in #113411 and #115070, CI failure link:
https://buildkite.com/llvm-project/github-pull-requests/builds/118845
This PR does not include a lit test case because it is a fix and the
above mentioned `@vector_store_i4` test actually tests the mechanism.
Signed-off-by: Alan Li <me at alanli.org>
Commit: 8da61a3434411850a0829f2d47f916f9bf29a4d8
https://github.com/llvm/llvm-project/commit/8da61a3434411850a0829f2d47f916f9bf29a4d8
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[llvm][docs] Expand HowToAddABuilder with guidance on testing locally (#115024)
With <https://github.com/llvm/llvm-zorg/pull/289> and <https://github.com/llvm/llvm-zorg/pull/293> landed, it's now reasonable to ask people to test their builder configurations locally. This patch adds documentation on how to do so.
Commit: a2042521a0387d7d7b80b2987f4b21f5a50bc7bb
https://github.com/llvm/llvm-project/commit/a2042521a0387d7d7b80b2987f4b21f5a50bc7bb
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libcxx/include/__algorithm/copy.h
M libcxx/include/__algorithm/copy_move_common.h
M libcxx/include/__algorithm/ranges_copy.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/ranges_set_difference.h
M libcxx/include/__algorithm/ranges_set_symmetric_difference.h
M libcxx/include/__algorithm/ranges_set_union.h
M libcxx/include/__algorithm/set_difference.h
M libcxx/include/__algorithm/set_symmetric_difference.h
M libcxx/include/__algorithm/set_union.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
Log Message:
-----------
[libc++] Remove _AlgPolicy from std::copy and algorithms using std::copy (#115887)
`std::copy` doesn't use the `_AlgPolicy` for anything other than calling
itself with it, so we can just remove the argument. This also removes
the need in a few other algorithms which had an `_AlgPolicy` argument
only to call `copy`.
Commit: 9d85ba5724f22d73c95858246691e0b389bdb28d
https://github.com/llvm/llvm-project/commit/9d85ba5724f22d73c95858246691e0b389bdb28d
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR] Preserve the order of switch cases after revert. (#115577)
Preserving the case order is not strictly necessary to preserve
semantics (for example, operations like SwitchInst::removeCase will
happily swap cases around). However, I'm planning to introduce an
optional verification step for SandboxIR that will use StructuralHash to
compare IR after a revert to the original IR to help catch tracker bugs,
and the order difference triggers a difference there.
Commit: 0e97b4d05a0b09513a4c130ec85a36c808d0074b
https://github.com/llvm/llvm-project/commit/0e97b4d05a0b09513a4c130ec85a36c808d0074b
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
A llvm/lib/CodeGen/GlobalISel/CombinerHelperArtifacts.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[GlobalISel] Combine G_MERGE_VALUES of x and undef (#113616)
into anyext x
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32),
[[DEF]](s32)
Please continue padding merge values.
// %bits_8_15:_(s8) = G_IMPLICIT_DEF
// %0:_(s16) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8)
%bits_8_15 is defined by undef. Its value is undefined and we can pick
an arbitrary value. For optimization, we pick anyext, which plays well
with the undefinedness.
// %0:_(s16) = G_ANYEXT %bits_0_7:(s8)
The upper bits of %0 are undefined and the lower bits come from
%bits_0_7.
Commit: 5a5122cac6eca445062e36ed7c69b6b749497143
https://github.com/llvm/llvm-project/commit/5a5122cac6eca445062e36ed7c69b6b749497143
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/GlobalISel/BUILD.gn
Log Message:
-----------
[gn build] Port 0e97b4d05a0b
Commit: 13317502da8ee3885854f67700140586c0edafee
https://github.com/llvm/llvm-project/commit/13317502da8ee3885854f67700140586c0edafee
Author: Shlomi Regev <shlmregev at users.noreply.github.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
Log Message:
-----------
[mlir] Add a null pointer check in symbol lookup (#115165)
Dead code analysis crashed because a symbol that is called/used didn't appear in the symbol
table.
This patch fixes this by adding a nullptr check after symbol table lookup.
Commit: 7b5e285d16090c2ddf4ee539c410d24bde52cbea
https://github.com/llvm/llvm-project/commit/7b5e285d16090c2ddf4ee539c410d24bde52cbea
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[NFC][Clang] Use range for loops in ClangDiagnosticsEmitter (#115573)
Use range based for loops in Clang diagnostics emitter.
Commit: 84e95beae980466ffcc555297e0e34d23fca8a76
https://github.com/llvm/llvm-project/commit/84e95beae980466ffcc555297e0e34d23fca8a76
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
Log Message:
-----------
[RISCV] Update SiFive P600's scheduling model on RVV instructions (#115243)
The biggest change is assigning vector crypto instructions to the
correct processor resource.
The majority of these changes are guided by our RVV-capable
llvm-exegesis.
Commit: d6219e65996a485adb3883c8cf3335ece68c66cf
https://github.com/llvm/llvm-project/commit/d6219e65996a485adb3883c8cf3335ece68c66cf
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
Log Message:
-----------
[libc] Make fstatvfs test less flakey (#115949)
Commit: b0a4e958e85784cff46303c92b6a3a14b20fa1d8
https://github.com/llvm/llvm-project/commit/b0a4e958e85784cff46303c92b6a3a14b20fa1d8
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.h
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Add support for non-unique `func.return` (#114017)
Multiple `func.return` ops inside of a `func.func` op are now supported
during bufferization. This PR extends the code base in 3 places:
- When inferring function return types, `memref.cast` ops are folded
away only if all `func.return` ops have matching buffer types. (E.g., we
don't fold if two `return` ops have operands with different layout
maps.)
- The alias sets of all `func.return` ops are merged. That's because
aliasing is a "may be" property.
- The equivalence sets of all `func.return` ops are taken only if they
match. If different `func.return` ops have different equivalence sets
for their operands, the equivalence information is dropped. That's
because equivalence is a "must be" property.
This commit is in preparation of removing the deprecated
`func-bufferize` pass. That pass can bufferize functions with multiple
`return` ops.
Commit: 7ba864b592b7ba1c70e958b9387b462931053a12
https://github.com/llvm/llvm-project/commit/7ba864b592b7ba1c70e958b9387b462931053a12
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SeedCollectorTest.cpp
Log Message:
-----------
[SandboxVectorizer] Register erase callback for seed collection (#115951)
Commit: 01d233ff403823389f8480897e41aea84ecbb3d3
https://github.com/llvm/llvm-project/commit/01d233ff403823389f8480897e41aea84ecbb3d3
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/Compilation.cpp
M clang/lib/Driver/Driver.cpp
R clang/test/Driver/time.c
R flang/test/Driver/time.f90
Log Message:
-----------
Revert "[clang][flang] Support -time in both clang and flang"
Reverts llvm/llvm-project#109165
This created a buildbot failure on
[Fuchsia](https://lab.llvm.org/buildbot/#/builders/11/builds/8080).
Commit: 37143fe27e082b478d333ca28f6f1af5210b7c6b
https://github.com/llvm/llvm-project/commit/37143fe27e082b478d333ca28f6f1af5210b7c6b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/test/Parser/cuf-sanity-common
Log Message:
-----------
[flang][cuda] Make launch configuration optional for cuf kernel (#115947)
Commit: e887f8290df419ffd4e018b6f8afbaeb1912cf0e
https://github.com/llvm/llvm-project/commit/e887f8290df419ffd4e018b6f8afbaeb1912cf0e
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir][LLVM] Add !invariant.group metadata to llvm.load and llvm.store (#115723)
This patch adds support for the `!invariant.group` metadata to the
`llvm.load` and the `llvm.store` operation.
Commit: 5fa47d8c52fa7449cc9f68cf314681f755df34bc
https://github.com/llvm/llvm-project/commit/5fa47d8c52fa7449cc9f68cf314681f755df34bc
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/CMakeLists.txt
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[libc] Support multilib with runtimes build (#115357)
This adds minimal support for multilibs akin to libc++.
Commit: 274feef7dd25585030af81c285d8ab1bbc8c4f28
https://github.com/llvm/llvm-project/commit/274feef7dd25585030af81c285d8ab1bbc8c4f28
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
Log Message:
-----------
Reland "[NVPTX] Emit prmt selection value in hex" (#115952)
Initially landed in 3ed4b0b0efca7a9467ce83fc62de9413da38006d.
Reverted in 375d1925dbd0c051fe2d4a86fe98ed08f4a502c5 because the
[`load-store.ll`](https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/NVPTX/load-store.ll)
test was not updated after 5e75880165553e9afb721239689a9c79ec84a108.
5e75880165553e9afb721239689a9c79ec84a108 is now updated in
7a99f2322c324972f2c5091dddd7752fa21d5a78.
Commit: 5a5502b9e1ca04626f7fd03c581b6deb5cd39c13
https://github.com/llvm/llvm-project/commit/5a5502b9e1ca04626f7fd03c581b6deb5cd39c13
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC. Use Value instead of template. (#115440)
Commit: de0fd64bedd23660f557833cc0108c3fb2be3918
https://github.com/llvm/llvm-project/commit/de0fd64bedd23660f557833cc0108c3fb2be3918
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Cuda.h
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9-4-generic-err.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
A llvm/test/MC/AMDGPU/gfx9_4_generic_unsupported.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AMDGPU] Introduce a new generic target `gfx9-4-generic` (#115190)
This patch introduces a new generic target, `gfx9-4-generic`. Since it doesn’t support FP8 and XF32-related instructions, the patch includes several code reorganizations to accommodate these changes.
Commit: 4714215efb0486682feaa3a99162e80a934be8f9
https://github.com/llvm/llvm-project/commit/4714215efb0486682feaa3a99162e80a934be8f9
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/Language.h
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.h
M lldb/source/Plugins/Language/ObjCPlusPlus/ObjCPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/ObjCPlusPlus/ObjCPlusPlusLanguage.h
M lldb/source/Target/Language.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/functionalities/data-formatter/setvaluefromcstring/main.m
M lldb/test/API/python_api/value/change_values/TestChangeValueAPI.py
M lldb/test/API/python_api/value/change_values/main.c
Log Message:
-----------
[lldb] Support true/false in ValueObject::SetValueFromCString (#115780)
Support "true" and "false" (and "YES" and "NO" in Objective-C) in
ValueObject::SetValueFromCString.
Fixes #112597
Commit: 2583071fb4773348e9ef89ddff1f00f1db8abb84
https://github.com/llvm/llvm-project/commit/2583071fb4773348e9ef89ddff1f00f1db8abb84
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
Log Message:
-----------
[flang][cuda] Compute size of derived type arrays (#115914)
Commit: 2baead09b2eea3b7b76afa193e35b93a236d948d
https://github.com/llvm/llvm-project/commit/2baead09b2eea3b7b76afa193e35b93a236d948d
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/docs/HowToAddABuilder.rst
Log Message:
-----------
[docs] Add blank line before bulletpoint list to fix HowToAddABuilder
The bulletpoint list wasn't rendering properly due to a missing blank
line.
Commit: 5911fbb39d615b39f1bf6fd732503ab433de5f27
https://github.com/llvm/llvm-project/commit/5911fbb39d615b39f1bf6fd732503ab433de5f27
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
Log Message:
-----------
AMDGPU: Do not fold copy to physreg from operation on frame index (#115977)
Commit: 95554cbd7717e7d1925f475540a70603bcb3a224
https://github.com/llvm/llvm-project/commit/95554cbd7717e7d1925f475540a70603bcb3a224
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Teach extractCallsFromIR to recognize heap allocation functions (#115938)
This patch teaches extractCallsFromIR to recognize heap allocation
functions. Specifically, when we encounter a callee that is known to
be a heap allocation function like "new", we set the callee GUID to 0.
Note that I am planning to do the same for the caller-callee pairs
extracted from the profile. That is, when I encounter a frame that
does not have a callee, we assume that the frame is calling some heap
allocation function with GUID 0.
Technically, I'm not recognizing enough functions in this patch.
TCMalloc is known to drop certain frames in the call stack immediately
above new. This patch is meant to lay the groundwork, setting up
GetTLI, plumbing it to extractCallsFromIR, and adjusting the unit
tests. I'll address remaining issues in subsequent patches.
Commit: 9991ea28fcd308d5bd357358710e5344e26b46e1
https://github.com/llvm/llvm-project/commit/9991ea28fcd308d5bd357358710e5344e26b46e1
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/AArch64/extract_float.ll
Log Message:
-----------
[CostModel][AArch64] Make extractelement, with fmul user, free whenev… (#111479)
…er possible
In case of Neon, if there exists extractelement from lane != 0 such that
1. extractelement does not necessitate a move from vector_reg -> GPR
2. extractelement result feeds into fmul
3. Other operand of fmul is a scalar or extractelement from lane 0 or
lane equivalent to 0
then the extractelement can be merged with fmul in the backend and it
incurs no cost.
e.g.
```
define double @foo(<2 x double> %a) {
%1 = extractelement <2 x double> %a, i32 0
%2 = extractelement <2 x double> %a, i32 1
%res = fmul double %1, %2
ret double %res
}
```
`%2` and `%res` can be merged in the backend to generate:
`fmul d0, d0, v0.d[1]`
The change was tested with SPEC FP(C/C++) on Neoverse-v2.
**Compile time impact**: None
**Performance impact**: Observing 1.3-1.7% uplift on lbm benchmark with -flto depending upon the config.
Commit: 804d3c4ce192391ef7ba8724c6b9eff456b5c4b2
https://github.com/llvm/llvm-project/commit/804d3c4ce192391ef7ba8724c6b9eff456b5c4b2
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Block.h
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/IR/Block.cpp
Log Message:
-----------
[mlir][IR] Add `Block::isReachable` helper function (#114928)
Add a new helper function `isReachable` to `Block`. This function
traverses all successors of a block to determine if another block is
reachable from the current block.
This functionality has been reimplemented in multiple places in MLIR.
Possibly additional copies in downstream projects. Therefore, moving it
to a common place.
Commit: 1824e45cd799a19fb9b5f9a84f9a0197157af8c8
https://github.com/llvm/llvm-project/commit/1824e45cd799a19fb9b5f9a84f9a0197157af8c8
Author: Kasper Nielsen <kasper0406 at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/test/python/ir/array_attributes.py
Log Message:
-----------
[MLIR,Python] Support converting boolean numpy arrays to and from mlir attributes (unrevert) (#115481)
This PR re-introduces the functionality of
https://github.com/llvm/llvm-project/pull/113064, which was reverted in
https://github.com/llvm/llvm-project/commit/0a68171b3c67503f7143856580f1b22a93ef566e
due to memory lifetime issues.
Notice that I was not able to re-produce the ASan results myself, so I
have not been able to verify that this PR really fixes the issue.
---
Currently it is unsupported to:
1. Convert a MlirAttribute with type i1 to a numpy array
2. Convert a boolean numpy array to a MlirAttribute
Currently the entire Python application violently crashes with a quite
poor error message https://github.com/pybind/pybind11/issues/3336
The complication handling these conversions, is that MlirAttribute
represent booleans as a bit-packed i1 type, whereas numpy represents
booleans as a byte array with 8 bit used per boolean.
This PR proposes the following approach:
1. When converting a i1 typed MlirAttribute to a numpy array, we can not
directly use the underlying raw data backing the MlirAttribute as a
buffer to Python, as done for other types. Instead, a copy of the data
is generated using numpy's unpackbits function, and the result is send
back to Python.
2. When constructing a MlirAttribute from a numpy array, first the
python data is read as a uint8_t to get it converted to the endianess
used internally in mlir. Then the booleans are bitpacked using numpy's
bitpack function, and the bitpacked array is saved as the MlirAttribute
representation.
Commit: 1294ddabbc3112559e5e652db226b2b6c099abb5
https://github.com/llvm/llvm-project/commit/1294ddabbc3112559e5e652db226b2b6c099abb5
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost model tests for vp.{s,u}{min,max}. NFC
Commit: edfa75de33433de29f438fbea4145ec6ae20e020
https://github.com/llvm/llvm-project/commit/edfa75de33433de29f438fbea4145ec6ae20e020
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
Log Message:
-----------
[clang] [NFC] Split checkAttributesAfterMerging() to multiple functions (#115464)
Commit: 9a365bc9a0dc92f25c0f1fdc25925b442dfe1455
https://github.com/llvm/llvm-project/commit/9a365bc9a0dc92f25c0f1fdc25925b442dfe1455
Author: Boaz Brickner <brickner at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/docs/InternalsManual.rst
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/lib/Basic/Diagnostic.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[Clang] [NFC] Add "human" diagnostic argument format (#115835)
This allows formatting large integers in a human friendly way. Example:
"5321584" -> "5.32M".
Use it where such human numbers are generated manually today.
Commit: a6f8af676a36bd43dd0c7f6229e6c91161a56819
https://github.com/llvm/llvm-project/commit/a6f8af676a36bd43dd0c7f6229e6c91161a56819
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
Log Message:
-----------
[RISCV] Improve vmsge and vmsgeu selection (#115435)
Select vmsge(u) vs, C to vmsgt(u) vs, C-1 if C is not in the imm range
and not the minimum value.
Fix https://github.com/llvm/llvm-project/issues/114505.
Commit: 735ab61ac828bd61398e6847d60e308fdf2b54ec
https://github.com/llvm/llvm-project/commit/735ab61ac828bd61398e6847d60e308fdf2b54ec
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/DwarfEHPrepare.cpp
M llvm/lib/CodeGen/ExpandLargeDivRem.cpp
M llvm/lib/CodeGen/ExpandLargeFpConvert.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GCEmptyBasicBlocks.cpp
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/CodeGen/HardwareLoops.cpp
M llvm/lib/CodeGen/IfConversion.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/InterferenceCache.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
M llvm/lib/CodeGen/KCFI.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveIntervalCalc.cpp
M llvm/lib/CodeGen/LiveRangeCalc.cpp
M llvm/lib/CodeGen/LiveStacks.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineStableHash.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
M llvm/lib/CodeGen/RegAllocScore.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/RegisterScavenging.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
Log Message:
-----------
[CodeGen] Remove unused includes (NFC) (#115996)
Identified with misc-include-cleaner.
Commit: 9571cc2b28d74c20f1abb3280adaa42d6e5b88dc
https://github.com/llvm/llvm-project/commit/9571cc2b28d74c20f1abb3280adaa42d6e5b88dc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
M llvm/lib/Target/ARM/ARMParallelDSP.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
Log Message:
-----------
[ARM] Remove unused includes (NFC) (#115995)
Identified with misc-include-cleaner.
Commit: fcacda899fcd812251a44a5b01548d7bb74d0481
https://github.com/llvm/llvm-project/commit/fcacda899fcd812251a44a5b01548d7bb74d0481
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
Log Message:
-----------
[RISCV] Remove constant_fold_cast_op from RISCVPostLegalizerCombiner.
This is no longer tested after other recent changes. AArch64 does
have this in their PostLegalizerCombiner.
Commit: 202ad47fe1bd652ee5cc7612e696a2479398c44f
https://github.com/llvm/llvm-project/commit/202ad47fe1bd652ee5cc7612e696a2479398c44f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Source.cpp
M clang/lib/AST/ByteCode/Source.h
M clang/test/SemaCXX/lambda-expressions.cpp
Log Message:
-----------
[clang][bytecode] SourceInfo::Source might be null (#115905)
This broke in 23fbaff9a3fd2b26418e0c2f10b701049399251f, but the old
.dyn_cast<> handled null.
Commit: 9aa4f50ae489507a780fb43367da9652ebfd6ffc
https://github.com/llvm/llvm-project/commit/9aa4f50ae489507a780fb43367da9652ebfd6ffc
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
Log Message:
-----------
[RISCV][TTI] Add vp.fneg intrinsic cost with functionalOP (#114378)
Commit: a4f3a10c0effa165071ad43cf8690e1762897533
https://github.com/llvm/llvm-project/commit/a4f3a10c0effa165071ad43cf8690e1762897533
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libc/config/baremetal/arm/headers.txt
M libc/config/baremetal/riscv/headers.txt
Log Message:
-----------
[libc] Include features.h in baremetal targets (#109444)
This is used by other libraries like libc++.
Commit: ae7b5af904850db71308915836f32a8d79553dd8
https://github.com/llvm/llvm-project/commit/ae7b5af904850db71308915836f32a8d79553dd8
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lldb/include/lldb/Host/posix/ConnectionFileDescriptorPosix.h
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
Log Message:
-----------
[lldb] Remove ConnectionFileDescriptor::child_process_inherit (#115861)
It's never set to true. Inheritable FDs are also dangerous as they can
end up processes which know nothing about them. It's better to
explicitly pass a specific FD to a specific subprocess, which we already
mostly can do using the ProcessLaunchInfo FileActions.
Commit: 91e134ad7d162c9affe37c67afb9dec34a215b7a
https://github.com/llvm/llvm-project/commit/91e134ad7d162c9affe37c67afb9dec34a215b7a
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/unittests/Analysis/PhiValuesTest.cpp
Log Message:
-----------
[llvm] Replace `UndefValue::get` with `PoisonValue::get` in a unit test [NFC] (#115985)
Since these `UndefValue::get` are acted as placeholders, I think it's
safe to replace them with poison values.
There are a lot of `UndefValue::get` in LLVM, I'll start fixing the ones
in `unittests` while fixing the regression tests.
Commit: d56f5171af96501d26723c4daed4d4a3b7c1f94b
https://github.com/llvm/llvm-project/commit/d56f5171af96501d26723c4daed4d4a3b7c1f94b
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add support for invariant group related intrinsics (#115877)
This PR adds support for the following LLVM intrinsics:
- `llvm.launder.invariant.group`
- `llvm.strip.invariant.group`
Commit: 20b442a25d86c35556cfc1bba4356f8ee75987bd
https://github.com/llvm/llvm-project/commit/20b442a25d86c35556cfc1bba4356f8ee75987bd
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/test/Fir/target-rewrite-complex16.fir
Log Message:
-----------
[Flang][LoongArch] Add support for complex16 params/returns. (#114732)
In LoongArch64, the passing and returning of type `complex16` is similar
to that of structure type like `struct {fp128, fp128}`, meaning they are
passed and returned by reference. This behavior is similar to clang, so
it can implement conveniently `iso_c_binding`.
Additionally, this patch fixes the failure in flang test
Integration/debug-complex-1.f90:
```
llvm-project/flang/lib/Optimizer/codeGen/Target.cpp:56:
not yet implemented: complex for this precision for return type
Commit: 5a12881514f9f70b24ad402f440f598bcad53cfb
https://github.com/llvm/llvm-project/commit/5a12881514f9f70b24ad402f440f598bcad53cfb
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[RISCV][Test] Add test for vp float arithmetic ops. NFC (#114516)
Commit: 7a1fdbb9c0f3becdbe539f0518d182f56a9f99f8
https://github.com/llvm/llvm-project/commit/7a1fdbb9c0f3becdbe539f0518d182f56a9f99f8
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/include/clang/AST/ASTImporter.h
M clang/include/clang/AST/ASTStructuralEquivalence.h
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/unittests/AST/StructuralEquivalenceTest.cpp
Log Message:
-----------
[clang][AST] Add 'IgnoreTemplateParmDepth' to structural equivalence cache (#115518)
Structural equivalence check uses a cache to store already found
non-equivalent values. This cache can be reused for calls (ASTImporter
does this). Value of "IgnoreTemplateParmDepth" can have an effect on the
structural equivalence therefore it is wrong to reuse the same cache for
checks with different values of 'IgnoreTemplateParmDepth'. The current
change adds the 'IgnoreTemplateParmDepth' to the cache key to fix the
problem.
Commit: c63e83f49575c024cf89fce9bc95d64988f3177b
https://github.com/llvm/llvm-project/commit/c63e83f49575c024cf89fce9bc95d64988f3177b
Author: Rakshit Patel <rakshit.patel at sony.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
A llvm/utils/lit/tests/xunit-output-report-failures-only.py
Log Message:
-----------
[lit] Add --report-failures-only option for lit test reports (#115439)
- Add option (--report-failures-only) to generate a reduced report for
lit tests that only includes failing tests
- This is a continuation of proposed patches by @gregbedwell here:
- https://reviews.llvm.org/D143516
- https://reviews.llvm.org/D143519
---------
Co-authored-by: Greg Bedwell <greg.bedwell at sony.com>
Co-authored-by: James Henderson <James.Henderson at sony.com>
Commit: 6ff41e860fdb69bb9e234e003255aae9accff79a
https://github.com/llvm/llvm-project/commit/6ff41e860fdb69bb9e234e003255aae9accff79a
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/test/Driver/target-cpu-features.f90
Log Message:
-----------
[Flang][LoongArch] Emit target features for Loongarch64. (#114735)
Commit: 12dcaa2e1e6c46d8a1b440d8a836d6b81ab92efb
https://github.com/llvm/llvm-project/commit/12dcaa2e1e6c46d8a1b440d8a836d6b81ab92efb
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
[clang] Add steakhal to the Clang Static Analyzer maintainers (#114991)
I've been contributing to the Clang Static Analyzer for a while now. I
think from 2019, or something like that.
I've ensured the quality of the Static Analyzer releases for the last
~4-6 releases now, with testing, fixing and backporting patches; also
writing comprehensive release notes for each release.
I have a strong sense of ownership of the code I contribute.
I follow the issue tracker, and also try to follow and participate in
RFCs on Discourse if I'm not overloaded.
I also check Discord time-to-time, but I rarely see anything there.
You can find the maintainer section of the LLVM DeveloperPolicy
[here](https://llvm.org/docs/DeveloperPolicy.html#maintainers) to read
more about the responsibilities.
Commit: 39b2979a434e70a4ce76d4adf91572dcfc9662ff
https://github.com/llvm/llvm-project/commit/39b2979a434e70a4ce76d4adf91572dcfc9662ff
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lldb/include/lldb/Symbol/Function.h
M lldb/source/Breakpoint/BreakpointResolverFileLine.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/test/API/source-manager/TestSourceManager.py
R lldb/test/API/source-manager/artificial_location.c
A lldb/test/API/source-manager/artificial_location.cpp
A lldb/test/API/source-manager/artificial_location.h
Log Message:
-----------
[lldb] Fix source display for artificial locations (#115876)
When retrieving the location of the function declaration, we were
dropping the file component on the floor, which resulted in an amusingly
confusing situation were we displayed the file containing the
implementation of the function, but used the line number of the
declaration. This patch fixes that.
It required a small refactor Function::GetStartLineSourceLineInfo to
return a SupportFile (instead of just the file spec), which in turn
necessitated changes in a couple of other places as well.
Commit: 2c980310f67c13dd89c8702d40abeab47a4a2b4b
https://github.com/llvm/llvm-project/commit/2c980310f67c13dd89c8702d40abeab47a4a2b4b
Author: Sylvestre Ledru <sylvestre at debian.org>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
Revert "[libclc] Create aliases with custom_command (#115885)"
for causing: https://github.com/llvm/llvm-project/issues/115942
This reverts commit 584d1a632f3af0daca4db02f7f3b2c7f48ab0ddf.
Commit: 133f8fa233abf40508ea9e42c4c31f5f0c13485f
https://github.com/llvm/llvm-project/commit/133f8fa233abf40508ea9e42c4c31f5f0c13485f
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
A clang/test/Driver/Inputs/cpunative/cortex-a57
A clang/test/Driver/Inputs/cpunative/cortex-a72
A clang/test/Driver/Inputs/cpunative/cortex-a76
A clang/test/Driver/Inputs/cpunative/neoverse-n1
A clang/test/Driver/Inputs/cpunative/neoverse-v2
A clang/test/Driver/aarch64-mcpu-native.c
M clang/test/lit.cfg.py
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
Reland [clang][AArch64] Add getHostCPUFeatures to query for enabled f… (#115467)
…eatures in cpu info
Relands #97749. Fixed test by adding additional checks for system linux
and target == host.
Commit: d7263d6d6d120a833fb45a17924117aad7412a99
https://github.com/llvm/llvm-project/commit/d7263d6d6d120a833fb45a17924117aad7412a99
Author: David Green <david.green at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir
Log Message:
-----------
[AArch64] Use second reg class in genSubAdd2SubSub machine combine.
In case the first operand is a physical register with no register class, use
the second operand of the sub as the register class for the new virtual
register in genSubAdd2SubSub machine combine.
Commit: 42da81582ea5a0e5bb0e18af74e6c101f0307f36
https://github.com/llvm/llvm-project/commit/42da81582ea5a0e5bb0e18af74e6c101f0307f36
Author: David Green <david.green at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-vector-splat.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
Log Message:
-----------
[AArch64][GlobalISel] Add a number of ptr shufflevector tests. NFC
Commit: 5845688e91d85d46c0f47daaf4edfdfc772853cf
https://github.com/llvm/llvm-project/commit/5845688e91d85d46c0f47daaf4edfdfc772853cf
Author: Kadir Cetinkaya <kadircet at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
A clang/docs/WarningSuppressionMappings.rst
M clang/docs/index.rst
M clang/include/clang/Basic/Diagnostic.h
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticOptions.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Basic/Diagnostic.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Interpreter/CodeCompletion.cpp
M clang/lib/Serialization/ASTReader.cpp
A clang/test/Misc/Inputs/suppression-mapping.txt
A clang/test/Misc/warning-suppression-mappings-pragmas.cpp
A clang/test/Misc/warning-suppression-mappings.cpp
M clang/tools/driver/cc1gen_reproducer_main.cpp
M clang/tools/driver/driver.cpp
M clang/unittests/Basic/DiagnosticTest.cpp
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M llvm/include/llvm/Support/SpecialCaseList.h
Log Message:
-----------
Reapply "[clang] Introduce diagnostics suppression mappings (#112517)"
This reverts commit 5f140ba54794fe6ca379362b133eb27780e363d7.
Commit: 2a1586dfb5a304830301cfcce8bd7d520b9d5a49
https://github.com/llvm/llvm-project/commit/2a1586dfb5a304830301cfcce8bd7d520b9d5a49
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/windows.inc
M compiler-rt/lib/builtins/cpu_model/cpu_model.h
Log Message:
-----------
[compiler-rt] Add cpu model init for Windows. (#111961)
Commit: 3e20bae827c0a314142fea74aa3d7ead039fab3d
https://github.com/llvm/llvm-project/commit/3e20bae827c0a314142fea74aa3d7ead039fab3d
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/AST/attr-lifetime-capture-by.cpp
A clang/test/SemaCXX/attr-lifetime-capture-by.cpp
Log Message:
-----------
Reapply "[clang] Introduce [[clang::lifetime_capture_by(X)]] (#115823)
Fix compile time regression and memory leak
In the previous change, we saw:
- Memory leak: https://lab.llvm.org/buildbot/#/builders/169/builds/5193
- 0.5% Compile time regression
[link](https://llvm-compile-time-tracker.com/compare.php?from=4a68e4cbd2423dcacada8162ab7c4bb8d7f7e2cf&to=8c4331c1abeb33eabf3cdbefa7f2b6e0540e7f4f&stat=instructions:u)
For compile time regression, we make the Param->Idx `StringMap` for
**all** functions. This `StringMap` is expensive and should not be
computed when none of the params are annotated with
`[[clang::lifetime_capture_by(X)]]`.
For the memory leak, the small vectors used in Attribute are not
destroyed because the attributes are allocated through ASTContext's
allocator. We therefore need a raw array in this case.
Commit: c7df10643bda4acdc9a02406a2eee8aa4ced747f
https://github.com/llvm/llvm-project/commit/c7df10643bda4acdc9a02406a2eee8aa4ced747f
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libcxx/include/__split_buffer
M libcxx/include/__vector/vector.h
M libcxx/include/deque
M lldb/examples/synthetic/libcxx.py
Log Message:
-----------
Unify naming of internal pointer members in std::vector and std::__split_buffer (#115517)
Related to PR #114423, this PR proposes to unify the naming of the
internal pointer members in `std::vector` and `std::__split_buffer` for
consistency and clarity.
Both `std::vector` and `std::__split_buffer` originally used a
`__compressed_pair<pointer, allocator_type>` member named `__end_cap_`
to store an internal capacity pointer and an allocator. However,
inconsistent naming changes have been made in both classes:
- `std::vector` now uses `__cap_` and `__alloc_` for its internal
pointer and allocator members.
- In contrast, `std::__split_buffer` retains the name `__end_cap_` for
the capacity pointer, along with `__alloc_`.
This inconsistency between the names `__cap_` and `__end_cap_` has
caused confusions (especially to myself when I was working on both
classes). I suggest unifying these names by renaming `__end_cap_` to
`__cap_` in `std::__split_buffer`.
Commit: 889b3c9487d114b9d082e9552599c8a8a8ccc660
https://github.com/llvm/llvm-project/commit/889b3c9487d114b9d082e9552599c8a8a8ccc660
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
A .ci/generate_test_report.py
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
A .ci/requirements.txt
Log Message:
-----------
Reland "[ci] New script to generate test reports as Buildkite Annotations (#113447)"
This reverts commit 8a1ca6cad9cd0e972c322910cdfbbe9552c6c7ca.
I have fixed 2 things:
* The report is now sent by stdin so we do not hit the limit on the size
of command line arguments.
* The report is limited to 1MB in size and if we exceed that we fall back
to listing only the totals with a note telling you to check the full log.
Commit: b69ddbc62838f23ace237c206676b1ed1c882638
https://github.com/llvm/llvm-project/commit/b69ddbc62838f23ace237c206676b1ed1c882638
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libcxx/include/__random/discard_block_engine.h
M libcxx/include/__random/linear_congruential_engine.h
M libcxx/include/__random/mersenne_twister_engine.h
M libcxx/include/__random/shuffle_order_engine.h
M libcxx/include/__random/subtract_with_carry_engine.h
M libcxx/include/__type_traits/integral_constant.h
M libcxx/include/any
M libcxx/include/limits
M libcxx/include/ratio
M libcxx/src/chrono.cpp
M libcxx/src/filesystem/filesystem_clock.cpp
M libcxx/src/filesystem/path.cpp
M libcxxabi/src/cxa_demangle.cpp
M runtimes/cmake/Modules/WarningFlags.cmake
Log Message:
-----------
[libc++] Make variables in templates inline (#115785)
The variables are all `constexpr`, which implies `inline`. Since they
aren't `constexpr` in C++03 they're also not `inline` there. Because of
that we define them out-of-line currently. Instead we can use the C++17
extension of `inline` variables, which results in the same weak
definitions of the variables but without having all the boilerplate.
Commit: 67b81e2120697b90f7c6595b73eb5fc94f437320
https://github.com/llvm/llvm-project/commit/67b81e2120697b90f7c6595b73eb5fc94f437320
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__locale
A libcxx/include/__memory/shared_count.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__mutex/once_flag.h
M libcxx/include/future
M libcxx/include/module.modulemap
M libcxx/include/mutex
Log Message:
-----------
[libc++] Split __shared_count out of <__memory/shared_ptr.h> (#115943)
`__shared_count` is used in a few places where `shared_ptr` isn't. This
avoids a bunch of transitive includes needed for the implementation of
`shared_ptr` in these places.
Commit: d942f5e13dd03e902ae77602c5a1781d04ac18a3
https://github.com/llvm/llvm-project/commit/d942f5e13dd03e902ae77602c5a1781d04ac18a3
Author: hanbeom <kese111 at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
M llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
M llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/load.ll
Log Message:
-----------
[VectorCombine] Combine extract/insert from vector into a shuffle (#115213)
insert (DstVec, (extract SrcVec, ExtIdx), InsIdx) --> shuffle (DstVec, SrcVec, Mask)
This commit combines extract/insert on a vector into Shuffle with vector.
Commit: 4c9cb974898c6a6fe3a4d3b1e2eb61c29dd1af28
https://github.com/llvm/llvm-project/commit/4c9cb974898c6a6fe3a4d3b1e2eb61c29dd1af28
Author: Andrey Timonin <timonina1909 at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
Log Message:
-----------
[NFC][mlir][emitc] fix misspelling in description of emitc.global (#115548)
Missing `!` before `emitc.global` was added in the `EmitC.td`.
Commit: e5d5ee4ea76faabab890c45538a464abb70b8793
https://github.com/llvm/llvm-project/commit/e5d5ee4ea76faabab890c45538a464abb70b8793
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 67b81e212069
Commit: 76befc86dea9cad6be870c04732379f7ecf596dd
https://github.com/llvm/llvm-project/commit/76befc86dea9cad6be870c04732379f7ecf596dd
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
Reland "[libclc] Create aliases with custom_command (#115885)" (#116025)
This relands commit 2c980310f67c13dd89c8702d40abeab47a4a2b4b after
fixing an issue.
Commit: 856c47b884ada7dadb1081244821e0acc199cc72
https://github.com/llvm/llvm-project/commit/856c47b884ada7dadb1081244821e0acc199cc72
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
ConstraintElim: assert on invalid union field (NFC) (#115898)
getContextInst currently returns an invalid union field, when it is
called with a ConditionFact, although existing callers don't do this. In
order to error out early and serve as documentation for future callers,
add an assert forbidding the behavior.
Commit: aba55809e9af5e0d981f10c7f9b44a1f57b423c2
https://github.com/llvm/llvm-project/commit/aba55809e9af5e0d981f10c7f9b44a1f57b423c2
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_mve.td
M clang/test/CodeGen/arm-mve-intrinsics/ternary.c
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
M llvm/test/CodeGen/Thumb2/mve-qrintr.ll
Log Message:
-----------
[ARM] Fix operand order for MVE predicated VFMAS (#115908)
For most MVE predicated FMA instructions, disabled lanes will contain
the value in the addend operand. However, The VFMAS instruction takes
the addend in a GPR, and the output register is shared with the first
multiply operand, so disabled lanes will get that value instead. This
means that we can't use the same intrinsic as for the other VFMA
instructions. Instead, we can codegen the vfmas intrinsic to a regular
FMA and select in clang, which the backend already has the patterns to
select VFMAS from.
Commit: 1878b94568e77e51f0bc316ba5a8a6b8994b8daf
https://github.com/llvm/llvm-project/commit/1878b94568e77e51f0bc316ba5a8a6b8994b8daf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll
M llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
Log Message:
-----------
[VectorCombine] isExtractExtractCheap - specify the extract/insert shuffle mask to improve shuffle costs (#114780)
This shuffle mask is so focused, the cost model is very likely to be able to determine a specific (lower) cost
Commit: 8ae2a18736c15e0d0d9d0893b21bce4f3bf581c9
https://github.com/llvm/llvm-project/commit/8ae2a18736c15e0d0d9d0893b21bce4f3bf581c9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/test/CodeGen/X86/lwp-intrinsics.ll
M llvm/test/CodeGen/X86/rotate_vec.ll
Log Message:
-----------
[X86] Use proxy scheduler models for bdver3/bdver4 cpus (#114873)
We don't have specific models for bdver3/bdver4 cpus but we can use the
bdver2/znver1 models as proxy standins - these days the models are more
useful for analysis than for perfect instruction scheduling so these
should be fine.
While they don't accurately represent the bdver3/bdver4 architecture
(specifically the different fp-pipe layout), they give more accurate
latency/throughputs (vs Agner) than the default SandyBridge model, and
enable PostRA scheduling which all recent AMD models have benefitted
from.
I had to use the znver1 model for bdver4 so that we have AVX2
instruction coverage (none of the TBM/XOP/LWP/FMA4 instructions have
explicit schedules so this shouldn't be a problem) - they both
double-pump 256-bit instructions so this works pretty well.
This patch is based off a discussion at the devmtg regarding how easily
we can provide an actual scheduler model (or at least approximation) to
more of the X86 cpu targets - we can then add specific models if the
(unlikely) need arises.
Commit: 97298853b4de70dbce9c0a140ac38e3ac179e02e
https://github.com/llvm/llvm-project/commit/97298853b4de70dbce9c0a140ac38e3ac179e02e
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/IR/ConstantFold.cpp
M llvm/lib/IR/Constants.cpp
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/div.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/or.ll
M llvm/test/Transforms/InstCombine/rotate.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/xor-ashr.ll
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
Log Message:
-----------
[LLVM][IR] Teach constant integer binop folds about vector ConstantInts. (#115739)
The existing logic mostly works with the main changes being:
* Use getScalarSizeInBits instead of IntegerType::getBitWidth
* Use ConstantInt::get(Type* instead of ConstantInt::get(LLVMContext
Commit: deb057adb7334734482452daf20ccdd8cece1aa8
https://github.com/llvm/llvm-project/commit/deb057adb7334734482452daf20ccdd8cece1aa8
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree-visitor.h
Log Message:
-----------
[flang] Enclose Walk overloads into class for lookup purposes (#115926)
The parse-tree-visitor consists of a range of `Walk` functions where
each overload is specialized for a particular case. These overloads do
call one another, and due to the usual name lookup rules, an earlier
overload can't call an overload defined later unless the latter was
declared ahead of time.
To avoid listing a number of declarations at the beginning of the header
enclose them in a class as static members, with a couple of simple
forwarding calls. This takes advantage of the class member name lookup,
which uses the entire class definition for lookup.
Commit: ec4dab173cf8055b640aa5dbbd27ec8be11974f3
https://github.com/llvm/llvm-project/commit/ec4dab173cf8055b640aa5dbbd27ec8be11974f3
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
Log Message:
-----------
[NFC] Remove a mistakenly committed binary file
`llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o`
Commit: b385c6358c8782742dd6a79ad23953d3b6765446
https://github.com/llvm/llvm-project/commit/b385c6358c8782742dd6a79ad23953d3b6765446
Author: lntue <lntue at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libc/test/src/math/smoke/CanonicalizeTest.h
Log Message:
-----------
[libc] Fix canonicalize[f|l] tests for targets with long-double-is-double. (#115998)
Commit: a33ae1b7df82d7d714156ad050c0b99545fad497
https://github.com/llvm/llvm-project/commit/a33ae1b7df82d7d714156ad050c0b99545fad497
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/LiveRangeCalc.cpp
Log Message:
-----------
[LiveRangeCalc] Fix isJointlyDominated (#116020)
Check that every path from the entry block to the use block passes
through at least one def block. Previously we only checked that at least
one path passed through a def block.
Commit: b63b0101ca47b8ba1589283cd34cc80cdb68b902
https://github.com/llvm/llvm-project/commit/b63b0101ca47b8ba1589283cd34cc80cdb68b902
Author: Oleksandr T. <oleksandr.tarasiuk at outlook.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaCast.cpp
M clang/test/AST/ByteCode/builtin-bit-cast.cpp
M clang/test/SemaCXX/builtin-bit-cast.cpp
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
Log Message:
-----------
[Clang] enhance diagnostic message for __builtin_bit_cast size mismatch (#115940)
Fixes #115870
Commit: b6bd7477a91ed47ecc1baae0a961224511679b59
https://github.com/llvm/llvm-project/commit/b6bd7477a91ed47ecc1baae0a961224511679b59
Author: aurel32 <aurelien at aurel32.net>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M offload/CMakeLists.txt
M offload/plugins-nextgen/common/src/Utils/ELF.cpp
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/plugins-nextgen/host/dynamic_ffi/ffi.h
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[Offload] Add support for riscv64 to host plugin (#115773)
This adds support for the riscv64 architecture to the offload host
plugin. The check to define FFI_DEFAULT_ABI is intentionally not guarded
by __riscv_xlen as the value is the same for riscv32 and riscv64
(support for OpenMP on riscv32 is still under review).
Commit: 256050520380b271ff0ac1f01fa56d6665e9af03
https://github.com/llvm/llvm-project/commit/256050520380b271ff0ac1f01fa56d6665e9af03
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
[AMDGPU] Reorder GCNPassConfig::addOptimizedRegAlloc. NFC. (#115873)
This just makes it so that the added passes are mentioned in this
function in the same order that they will appear in the final pass
pipeline.
Commit: 1884ffc41c20b1e08b30eef4e8ebbcc54543a139
https://github.com/llvm/llvm-project/commit/1884ffc41c20b1e08b30eef4e8ebbcc54543a139
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/utils/TableGen/MveEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115994)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 8cc616bc71dfe0648de3843a006ac8827c5fe59d
https://github.com/llvm/llvm-project/commit/8cc616bc71dfe0648de3843a006ac8827c5fe59d
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir] Clamp UnPackOp tiling sizes from operand tile (#112429)
The `getIterationDomainTileFromOperandTile` implementation for
tensor.unpack did not clamp sizes when the unpack op had extract_slice
semantics. This PR fixes the bug.
The PR also makes a minor change to `tileAndFuseConsumerOfSlice`. When
replacing DPS inits, the iteration domain is needed, and it is computed
from the tiled version of the operation after the initial tiling
transformation. This can result in some extra indexing computation, so
the PR changes it to use the original full sized cloned consumer op.
---------
Signed-off-by: Max Dawkins <max.dawkins at gmail.com>
Commit: a86d00cf24008929bf32393415bf532c59cec4c4
https://github.com/llvm/llvm-project/commit/a86d00cf24008929bf32393415bf532c59cec4c4
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/SemaOpenACC/combined-construct-auto_seq_independent-ast.cpp
A clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct.cpp
Log Message:
-----------
[OpenACC] Implement combined constr 'seq'/'independent'/'auto' clauses
These three are identical to the version on compute constructs, so this
patch implements the tests for it, and ensures that we properly validate
it against all the other clauses we're supposed to. The test is mostly
a mock-up at the moment, since most other clauses aren't implemented
yet for 'loop'.
Commit: 716a095a80030de3ffdccd52b8e7e0909ee7b8d0
https://github.com/llvm/llvm-project/commit/716a095a80030de3ffdccd52b8e7e0909ee7b8d0
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for 8cc616bc71dfe0648de3843a006ac8827c5fe59d
Commit: 46b275716ac03f6f28b945b0c7b2b05592d7207f
https://github.com/llvm/llvm-project/commit/46b275716ac03f6f28b945b0c7b2b05592d7207f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangSACheckersEmitter.cpp
M clang/utils/TableGen/ClangSyntaxEmitter.cpp
Log Message:
-----------
[NFC][Clang] Use StringRef and range for loops in SA/Syntax Emitters (#115972)
Use StringRef and range for loops in Clang SACheckers and Syntax
emitters.
Commit: 4f1fe6d5f1607133883d116ef0c14582fbde7ada
https://github.com/llvm/llvm-project/commit/4f1fe6d5f1607133883d116ef0c14582fbde7ada
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[NFC][lang][TableGen] Simplify `EmitClangDiagsIndexName` (#115962)
Simplify `EmitClangDiagsIndexName` to directly sort records instead of
creating an array of `RecordIndexElement` containing record name and
sorting it.
---------
Co-authored-by: Kazu Hirata <kazu at google.com>
Commit: 3169a38ddf75277030471a996ebd981f9dd51aa3
https://github.com/llvm/llvm-project/commit/3169a38ddf75277030471a996ebd981f9dd51aa3
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
A clang/test/AST/ast-print-openacc-combined-construct.cpp
Log Message:
-----------
[OpenACC] Add ast-print test for combined constructs
Commit: 9c928d0308eb75f52e570d61330975a67e0be71c
https://github.com/llvm/llvm-project/commit/9c928d0308eb75f52e570d61330975a67e0be71c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/and-fcmp.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
Log Message:
-----------
[InstCombine] Add tests for reassoc of and/or of fcmps (NFC)
Commit: 1e5bfac933ea90ec4361446398551dd6b967c67f
https://github.com/llvm/llvm-project/commit/1e5bfac933ea90ec4361446398551dd6b967c67f
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/SystemZ/zvector2.c
Log Message:
-----------
[clang][SystemZ][NFC] Autogenerate some test case
Autogenerate the clang/test/CodeGen/SystemZ/zvector{,2}.c
test cases to make it easier to update them in the future.
Commit: cd88bfcb5906049e1387b856fc7256e5fae22e5f
https://github.com/llvm/llvm-project/commit/cd88bfcb5906049e1387b856fc7256e5fae22e5f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
A llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll
Log Message:
-----------
ConstantFolding: Do not fold fcmp of denormal without known mode (#115407)
Fixes #114947
Commit: 8e6630391699116641cf390a10476295b7d4b95c
https://github.com/llvm/llvm-project/commit/8e6630391699116641cf390a10476295b7d4b95c
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorInsertExtractStridedSliceRewritePatterns.cpp
M mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-lowering.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir
Log Message:
-----------
[mlir][Vector] Remove trivial uses of vector.extractelement/vector.insertelement (1/N) (#116053)
This patch removes trivial usages of
vector.extractelement/vector.insertelement. These operations can be
fully represented by vector.extract/vector.insert. See
https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops/71116
for more information.
Further patches will remove more usages of these ops.
Commit: 9174b5400c57efefc09f8f6c7afdb7012834b4f4
https://github.com/llvm/llvm-project/commit/9174b5400c57efefc09f8f6c7afdb7012834b4f4
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir
Log Message:
-----------
[TailDup] Add test case for pred/succ limit without phi nodes.
Commit: 69879ffaec8789dd4ce5f6fa26f1b5e8140190ff
https://github.com/llvm/llvm-project/commit/69879ffaec8789dd4ce5f6fa26f1b5e8140190ff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
Log Message:
-----------
AMDGPU: Fix using illegal VOP3 literal in frame index elimination (#115747)
Commit: 4a0c3077b0075f64471b306356ec5b3b98a0fa94
https://github.com/llvm/llvm-project/commit/4a0c3077b0075f64471b306356ec5b3b98a0fa94
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV][NFCI] Reorder RISCVRegsiterInfo.td
Also adds some headers so different sections are easier to identify.
Commit: fd8d4333fc3abbf8a54b5f10e4cb16b3b7bfc663
https://github.com/llvm/llvm-project/commit/fd8d4333fc3abbf8a54b5f10e4cb16b3b7bfc663
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
Log Message:
-----------
[RISCV][GISel] Promote s32 G_SEXTLOAD/ZEXTLOAD on RV64.
Commit: 0baa6a7272970257fd6f527e95eb7cb18ba3361c
https://github.com/llvm/llvm-project/commit/0baa6a7272970257fd6f527e95eb7cb18ba3361c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Log Message:
-----------
[VectorCombine] foldShuffleOfShuffles - relax one-use of inner shuffles (#116062)
Allow multi-use of either of the inner shuffles and account for that in the cost comparison.
Commit: 4df5310ffc82c0382f508d969e19521200ab357b
https://github.com/llvm/llvm-project/commit/4df5310ffc82c0382f508d969e19521200ab357b
Author: Yadong Chen <cyd.matt at qq.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
M mlir/lib/Dialect/SPIRV/IR/GroupOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Conversion/ConvertToSPIRV/argmax-kernel.mlir
M mlir/test/Conversion/ConvertToSPIRV/gpu.mlir
M mlir/test/Conversion/GPUToSPIRV/reductions.mlir
M mlir/test/Dialect/SPIRV/IR/group-ops.mlir
M mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/group-ops.mlir
M mlir/test/Target/SPIRV/non-uniform-ops.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define groupNonUniform op assembly (#115662)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out CPP interfaces.
Changes:
* updates the Ops defined in `SPIRVNonUniformOps.td and
SPIRVGroupOps.td` to use assemblyFormat.
* Removes print/parse from `GroupOps.cpp` which is now generated by
assemblyFormat
* Updates tests to updated format (largely using <operand> in place of
"operand" and complementing type information)
Issue: #73359
Commit: c342d11375e2befaf6ee15d491d5cbd5458ca6b1
https://github.com/llvm/llvm-project/commit/c342d11375e2befaf6ee15d491d5cbd5458ca6b1
Author: lntue <lntue at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libc/docs/talks.rst
Log Message:
-----------
[libc][doc] Add links to slides and video from Siva's CppNow 2023 talk. (#116038)
Commit: 2ca25ab11d01ceacf359643b09aed7d53d0ff8dc
https://github.com/llvm/llvm-project/commit/2ca25ab11d01ceacf359643b09aed7d53d0ff8dc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Add extra tests for FoldOpIntoSelect (NFC)
Commit: 7a31f3c7612995ac32b4529039a1773e260b00c9
https://github.com/llvm/llvm-project/commit/7a31f3c7612995ac32b4529039a1773e260b00c9
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[mlir][vector][nfc] Improve comments in `getCompressedMaskOp` (#115663)
Commit: 21f7c626270d5b39c40f7d8f978ee91937d11dbb
https://github.com/llvm/llvm-project/commit/21f7c626270d5b39c40f7d8f978ee91937d11dbb
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
A llvm/lib/Target/ARM/ARMLatencyMutations.cpp
A llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/CMakeLists.txt
Log Message:
-----------
[LLVM][ARM] Latency mutations for cortex m55,m7 and m85 (#115153)
This patch adds latency mutations as a scheduling related speedup for
the above mentioned cores. When benchmarking this pass on selected
benchmarks we see a performance improvement of 1% on most benchmarks
with some improving by up to 6%.
Author: David Penry <david.penry at arm.com>
Co-authored-by: Nashe Mncube <nashe.mncube at arm.com
Commit: 67c434523b1bca96f49458eef835fd8838b67c54
https://github.com/llvm/llvm-project/commit/67c434523b1bca96f49458eef835fd8838b67c54
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps5-linker.c
Log Message:
-----------
[PS5][Driver] Allow `-T` to override `--default-script` (#116074)
If a linker script is explicitly supplied, there's no benefit to
supplying a default script.
SIE tracker: TOOLCHAIN-17524
Commit: 2d95ad05311e91037e60ce4d0e724c13e6f009ec
https://github.com/llvm/llvm-project/commit/2d95ad05311e91037e60ce4d0e724c13e6f009ec
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Log Message:
-----------
[RISCV][GISel] Use boolean predicated legalization action method to simplify code. NFC
Commit: 51e9609706df288ba52ea48512ab69543a58a64d
https://github.com/llvm/llvm-project/commit/51e9609706df288ba52ea48512ab69543a58a64d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
Log Message:
-----------
[gn build] Port 21f7c626270d
Commit: 39a8046b731ff4968835e8786ad2331aab7f9de2
https://github.com/llvm/llvm-project/commit/39a8046b731ff4968835e8786ad2331aab7f9de2
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/utils/TableGen/AsmWriterEmitter.cpp
Log Message:
-----------
[NFC][TableGen] Use formatv automatic index in AsmWriterEmitter (#115966)
Use formatv automatic index assignment in AsmWriterEmitter.
Commit: bf51a9e744fe2acdbd709e10f6aec3b5aa2f3ab3
https://github.com/llvm/llvm-project/commit/bf51a9e744fe2acdbd709e10f6aec3b5aa2f3ab3
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/test/Conversion/SPIRVToLLVM/non-uniform-ops-to-llvm.mlir
Log Message:
-----------
[mlir][spirv] Upgrade spirv group op syntax in tests
Fixing forward a missed test from
https://github.com/llvm/llvm-project/pull/115662.
Commit: 0afdac41ceb9567c2f953092d0e8b6220c15acea
https://github.com/llvm/llvm-project/commit/0afdac41ceb9567c2f953092d0e8b6220c15acea
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
Log Message:
-----------
[lldb][test] Fix inline_sites_live.cpp Shell when run on Windows remotely from Linux (#115722)
This test fails on
https://lab.llvm.org/staging/#/builders/197/builds/76/steps/18/logs/FAIL__lldb-shell__inline_sites_live_cpp
because of a little difference in the lldb output.
```
# .---command stderr------------
# | C:\buildbot\as-builder-10\lldb-x-aarch64\llvm-project\lldb\test\Shell\SymbolFile\NativePDB\inline_sites_live.cpp:25:11: error: CHECK: expected string not found in input
# | // CHECK: * thread #1, stop reason = breakpoint 1
# | ^
# | <stdin>:1:1: note: scanning from here
# | (lldb) platform select remote-linux
# | ^
# | <stdin>:28:27: note: possible intended match here
# | * thread #1, name = 'inline_sites_li', stop reason = breakpoint 1.3
# | ^
# |
```
Commit: 2bd6af8cbc75ba67c20382757e03b85829d77a32
https://github.com/llvm/llvm-project/commit/2bd6af8cbc75ba67c20382757e03b85829d77a32
Author: Ronan Keryell <ronan.keryell at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/CMakeLists.txt
Log Message:
-----------
[MLIR][NFC] Fix SYCL spelling (#113060)
See https://www.khronos.org/sycl/ for the official spelling of the
Khronos Group standard.
Also fix MLIR spelling in the neighborhood.
Commit: 67fb2686fba9abd6e607ff9a09b7018b2b8ae31b
https://github.com/llvm/llvm-project/commit/67fb2686fba9abd6e607ff9a09b7018b2b8ae31b
Author: Augusto Noronha <anoronha at apple.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/test/Assembler/debug-info.ll
A llvm/test/DebugInfo/AArch64/specification.ll
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
Log Message:
-----------
[DebugInfo] Add a specification attribute to LLVM DebugInfo (#115362)
Add a specification attribute to LLVM DebugInfo, which is analogous
to DWARF's DW_AT_specification. According to the DWARF spec:
"A debugging information entry that represents a declaration that
completes another (earlier) non-defining declaration may have a
DW_AT_specification attribute whose value is a reference to the
debugging information entry representing the non-defining declaration."
This patch allows types to be specifications of other types. This is
used by Swift to represent generic types. For example, given this Swift
program:
```
struct MyStruct<T> {
let t: T
}
let variable = MyStruct<Int>(t: 43)
```
The Swift compiler emits (roughly) an unsubtituted type for MyStruct<T>:
```
DW_TAG_structure_type
DW_AT_name ("MyStruct")
// "$s1w8MyStructVyxGD" is a Swift mangled name roughly equivalent to
// MyStruct<T>
DW_AT_linkage_name ("$s1w8MyStructVyxGD")
// other attributes here
```
And a specification for MyStruct<Int>:
```
DW_TAG_structure_type
DW_AT_specification (<link to "MyStruct">)
// "$s1w8MyStructVySiGD" is a Swift mangled name equivalent to
// MyStruct<Int>
DW_AT_linkage_name ("$s1w8MyStructVySiGD")
DW_AT_byte_size (0x08)
// other attributes here
```
Commit: 6b2de10c687dedb8e460699d2b68f0b0eafc2b4e
https://github.com/llvm/llvm-project/commit/6b2de10c687dedb8e460699d2b68f0b0eafc2b4e
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-device_type-ast.cpp
A clang/test/SemaOpenACC/combined-construct-device_type-clause.c
A clang/test/SemaOpenACC/combined-construct-device_type-clause.cpp
M clang/test/SemaOpenACC/combined-construct.cpp
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.cpp
M clang/test/SemaOpenACC/loop-construct.cpp
Log Message:
-----------
[OpenACC] implement 'device_type' for combined constructs
This clause is pretty small/doesn't do much semantic-analysis-wise, , other than
have two spellings and disallow certain clauses after it. However, as
most of those aren't implemented yet, the diagnostic is left as a TODO.
Commit: 1b8e0cf090a08b2c517eb2a3e101332d692063c2
https://github.com/llvm/llvm-project/commit/1b8e0cf090a08b2c517eb2a3e101332d692063c2
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M bolt/include/bolt/Core/Exceptions.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Never emit "large" functions (#115974)
"Large" functions are functions that are too big to fit into their
original slots after code modifications. CheckLargeFunctions pass is
designed to prevent such functions from emission. Extend this pass to
work with functions with constant islands.
Now that CheckLargeFunctions covers all functions, it guarantees that we
will never see such functions after code emission on all platforms
(previously it was guaranteed on x86 only). Hence, we can get rid of
RewriteInstance extensions that were meant to support "large" functions.
Commit: 92604cf3788e5603482e7adde20949eddbc4c939
https://github.com/llvm/llvm-project/commit/92604cf3788e5603482e7adde20949eddbc4c939
Author: vdonaldson <37090318+vdonaldson at users.noreply.github.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/module/ieee_arithmetic.f90
M flang/runtime/Float128Math/CMakeLists.txt
M flang/runtime/Float128Math/math-entries.h
A flang/runtime/Float128Math/remainder.cpp
A flang/test/Lower/Intrinsics/ieee_rem.f90
Log Message:
-----------
[flang] IEEE_REM (#115936)
Implement the IEEE 60559:2020 remainder function.
Commit: 57cf199be2f1496e242f6dcd32456b3ed816d46d
https://github.com/llvm/llvm-project/commit/57cf199be2f1496e242f6dcd32456b3ed816d46d
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMSubtarget.cpp
Log Message:
-----------
[llvm][ARM] Missing switch statement handles (#116086)
PR #115153 added enums which needed to be handled in a switch statement.
This trips up buildbot.
Commit: 95b680e4c353d479fbfb96adb39696042c005e99
https://github.com/llvm/llvm-project/commit/95b680e4c353d479fbfb96adb39696042c005e99
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libc/src/__support/CMakeLists.txt
M libc/src/__support/HashTable/generic/bitmask_impl.inc
R libc/src/__support/endian.h
A libc/src/__support/endian_internal.h
M libc/src/network/htonl.cpp
M libc/src/network/htons.cpp
M libc/src/network/ntohl.cpp
M libc/src/network/ntohs.cpp
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/utils.h
M libc/test/src/__support/CMakeLists.txt
A libc/test/src/__support/endian_internal_test.cpp
R libc/test/src/__support/endian_test.cpp
M libc/test/src/network/htonl_test.cpp
M libc/test/src/network/htons_test.cpp
M libc/test/src/network/ntohl_test.cpp
M libc/test/src/network/ntohs_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel
Log Message:
-----------
[libc] Rename libc/src/__support/endian.h to endian_internal.h (#115950)
This prevents a conflict with the Linux system endian.h when built in
overlay mode for CPP files in __support.
This issue appeared in PR #106259.
Commit: 461a0d6c56ff2e6beb458bd410bfcf605cd63753
https://github.com/llvm/llvm-project/commit/461a0d6c56ff2e6beb458bd410bfcf605cd63753
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/test/CodeGen/AArch64/fmv-dependencies.c
M clang/test/CodeGen/AArch64/fmv-streaming.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
Log Message:
-----------
[FMV] Add "+fmv" to the target-features of versioned functions. (#116028)
This essentially propagates the information that a function is versioned
from source code to IR.
Commit: 0f44d72e0ee74970cf696ff4c791f63e0c3fa9b4
https://github.com/llvm/llvm-project/commit/0f44d72e0ee74970cf696ff4c791f63e0c3fa9b4
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/phi.ll
Log Message:
-----------
[InstCombine] Precommit test for PR115901 (NFC)
Commit: 929cbe7f596733f85cd274485acc19442dd34a80
https://github.com/llvm/llvm-project/commit/929cbe7f596733f85cd274485acc19442dd34a80
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/phi.ll
Log Message:
-----------
[InstCombine] Intersect nowrap flags between geps while folding into phi
A miscompilation issue has been addressed with refined checking.
Fixes: https://github.com/llvm/llvm-project/issues/115149.
Commit: 71ae021359b6f0fbf241021d2246e7acb66f4837
https://github.com/llvm/llvm-project/commit/71ae021359b6f0fbf241021d2246e7acb66f4837
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang] Few minor formatting changes, NFC
This makes these files be invariant with respect to clang-format.
Commit: cb9481dbf902adc349757eca12a0a09396dc4a23
https://github.com/llvm/llvm-project/commit/cb9481dbf902adc349757eca12a0a09396dc4a23
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[mlir][affine] Add folders for delinearize_index and linearize_index (#115766)
This commit adds implementations of fold() for delinearize_index and
linearize_index to constant-fold them away when they have a fully
constant basis and constant argument(s).
This commit also adds a canonicalization pattern to linearize_index that
causes it to drop leading-zero inputs.
Commit: e4578616476426595737c73c9ac357467ee19123
https://github.com/llvm/llvm-project/commit/e4578616476426595737c73c9ac357467ee19123
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
Log Message:
-----------
[flang][cuda] Support shape shift in data transfer op. (#115929)
When an array is declared with a non default lower bound, the declare op
`getShape` will return a `ShapeShiftOp`. This result is used in data
transfer operation to compute the number of bytes to transfer. Update
the op to support `ShapeShiftOp`.
Commit: c658d07c4f8210555473c5721e1302f00f9fd25b
https://github.com/llvm/llvm-project/commit/c658d07c4f8210555473c5721e1302f00f9fd25b
Author: John Harrison <harjohn at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/evaluate/main.cpp
Log Message:
-----------
[lldb-dap] Adjust the evaluate test to use a different lldb command. (#116045)
Previously this used `var` as both an lldb command and variable in the
source to validate the behavior of the 'auto' repl mode. However, `var`
seems to occasionally fail in the CI test when attempting to print some
c++ types. Instead switch the command and variable name to `list` which
should not run the dynamic variable formatting code for c++ objects.
This should fix #116041.
Commit: a6d299ddb9398e4641b23ce5c549ca5285dd2ef2
https://github.com/llvm/llvm-project/commit/a6d299ddb9398e4641b23ce5c549ca5285dd2ef2
Author: John Harrison <harjohn at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactor lldb-dap/DAP.{h,cpp} to use its own instance instead of the global instance. (#115948)
The refactor will unblock us for creating multiple DAP instances.
Commit: 48e09fea01d1c0196d22e99ddae5677ef050304e
https://github.com/llvm/llvm-project/commit/48e09fea01d1c0196d22e99ddae5677ef050304e
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
Add new "llvm:SandboxIR" label to .github/new-prs-labeler.yml (#115965)
As requested in
https://github.com/llvm/llvm-project/pull/115577#issuecomment-2466300749
Commit: 00f2989f98520c401f0ab544a3dc766ed83785c0
https://github.com/llvm/llvm-project/commit/00f2989f98520c401f0ab544a3dc766ed83785c0
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/hip-device-libs.hip
Log Message:
-----------
[HIP] Default to COV5 for HIP compilations (#116077)
Summary:
This was done a long time ago for OpenMP, but it seems HIP was never
updated. This patch rectifies that. The default for the LLVM backend is
5 so this is probably required for some stuff.
Commit: 8ac6af2c7f5caec824ebc9a0a527e2040f2b03f6
https://github.com/llvm/llvm-project/commit/8ac6af2c7f5caec824ebc9a0a527e2040f2b03f6
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM][Maintainers] Update NVPTX maintainers (#115973)
This PR requires approval from:
- @jholewinski to attest that @Artem-B, @AlexMaclean, and
@justinfargnoli can perform the [responsibilities of a
maintainer](https://llvm.org/docs/DeveloperPolicy.html#maintainers).
- @Artem-B and @AlexMaclean to ensure they'd like to volunteer for the
role.
Commit: 47cc9db797b1e1da94af91cf3d0f2999d11c1cbc
https://github.com/llvm/llvm-project/commit/47cc9db797b1e1da94af91cf3d0f2999d11c1cbc
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/test/Transforms/WholeProgramDevirt/devirt_single_after_filtering_unreachable_function.ll
Log Message:
-----------
[WPD]Regard unreachable function as a possible devirtualizable target (#115668)
https://reviews.llvm.org/D115492 skips unreachable functions and
potentially allows more static de-virtualizations. The motivation is to
ignore virtual deleting destructor of abstract class (e.g.,
`Base::~Base()` in https://gcc.godbolt.org/z/dWMsdT9Kz).
* Note WPD already handles most pure virtual functions (like `Base::x()`
in the godbolt example above), which becomes a `__cxa_pure_virtual` in
the vtable slot.
This PR proposes to undo the change, because it turns out there are
other unreachable functions that a general program wants to run and fail
intentionally, with `LOG(FATAL)` or `CHECK` [1] for example. While many
real-world applications are encouraged to check-fail sparingly, they are
allowed to do so on critical errors (e.g., misconfiguration or bug is
detected during server startup).
* Implementation-wise, this PR keeps the one-bit 'unreachable' state in
bitcode and updates WPD analysis.
https://gcc.godbolt.org/z/T1aMhczYr is a minimum reproducible example
extracted from unit test. `Base::func` is a one-liner of `LOG(FATAL) <<
"message"`, and lowered to one basic block ending with `unreachable`. A
real-world program is _allowed_ to invoke Base::func to terminate the
program as a way to report errors (in server initialization stage for
example), even if errors on the serving path should be handled more
gracefully.
[1] https://abseil.io/docs/cpp/guides/logging#CHECK and
https://abseil.io/docs/cpp/guides/logging#configuration-and-flags
Commit: 62441b9f30a65b2708697f06333cb8bc777cebe9
https://github.com/llvm/llvm-project/commit/62441b9f30a65b2708697f06333cb8bc777cebe9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
Log Message:
-----------
[RISCV][GISel] Add instruction selection mir test for f32/f64 fp load/store. NFC
We had a regbank-select test but not an instruction selection test.
Commit: e25e8867348953c17fa0d0b79f43bde758ad8b37
https://github.com/llvm/llvm-project/commit/e25e8867348953c17fa0d0b79f43bde758ad8b37
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M libc/src/__support/high_precision_decimal.h
Log Message:
-----------
[libc][z/OS] Remove ASCII trick to fix EBDIC std::from_char (#116078)
This PR will fix the following lit in all EBCDIC variations on z/OS:
`std/utilities/charconv/charconv.from.chars/floating_point.pass.cpp`
The trick to test for `e` and `E` is working only in ASCII.
The fix is to simply test for both lower and upper case exponent letter
`e` and `E` respectfully.
Commit: d492001bdcd7bfcd19ada7459a6b0eaf81ba3ba2
https://github.com/llvm/llvm-project/commit/d492001bdcd7bfcd19ada7459a6b0eaf81ba3ba2
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[Fuchsia][CMake] Enable new libc header gen (#102371)
All issues blocking this were resolved.
Commit: b904166aa0cf9a00440076911056ed81d01dfe59
https://github.com/llvm/llvm-project/commit/b904166aa0cf9a00440076911056ed81d01dfe59
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
Log Message:
-----------
[RISCV][GISel] Remove -disable-gisel-legality-check from scalar tests. NFC
Adjust a couple tests so they can pass the check.
Commit: 4e330faac2b9a9172f4f16842196200989d6fbf3
https://github.com/llvm/llvm-project/commit/4e330faac2b9a9172f4f16842196200989d6fbf3
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
Log Message:
-----------
[OpenACC] Implement combined construct allowed-after device-type rule
This patch implements the 'only X is allowed after' rule for combined
constructs on a device-type clause. This was left as a set of 'TODO' in
the previous patch, plus more issues were found with the TODO list,
which are fixed here.
Commit: fa20b5d30d38f4bb090acac7c205fbb54a5ca990
https://github.com/llvm/llvm-project/commit/fa20b5d30d38f4bb090acac7c205fbb54a5ca990
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-if-ast.cpp
A clang/test/SemaOpenACC/combined-construct-if-clause.c
A clang/test/SemaOpenACC/combined-construct-if-clause.cpp
A clang/test/SemaOpenACC/combined-construct-self-ast.cpp
A clang/test/SemaOpenACC/combined-construct-self-clause.c
A clang/test/SemaOpenACC/combined-construct-self-clause.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
Log Message:
-----------
[OpenACC] 'if' and 'self' clause implementation for Combined Constructs
These two are identical to how they work for compute constructs, so this
patch enables them and ensures there is sufficient testing.
Commit: 04d450fd8d4e8fcf0b0c5019d9233a5c7d7fe751
https://github.com/llvm/llvm-project/commit/04d450fd8d4e8fcf0b0c5019d9233a5c7d7fe751
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
Log Message:
-----------
AtomicExpand: Preserve metadata when bitcasting fp atomicrmw xchg (#115240)
Commit: dc4185fe2f9635791c6bab04ace29e090949a18e
https://github.com/llvm/llvm-project/commit/dc4185fe2f9635791c6bab04ace29e090949a18e
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
Log Message:
-----------
[TLI] Add support for reallocarray (#114818)
reallocarray is available in glibc since 2.29 under _DEFAULT_SOURCE and
under _GNU_SOURCE before, let's model it appropriately.
Commit: 6684eb4d6c9ac2b1ec35cf7d0df1344bfe81ade1
https://github.com/llvm/llvm-project/commit/6684eb4d6c9ac2b1ec35cf7d0df1344bfe81ade1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove IR section from a couple MIR tests. NFC
Commit: 17c6ec6db1430e7e00c0e2a2ad6d26fa94fe8cf1
https://github.com/llvm/llvm-project/commit/17c6ec6db1430e7e00c0e2a2ad6d26fa94fe8cf1
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[NFC][Clang] Use StringRef instead of string in ClangDiagnosticEmitter (#115959)
Use StringRef instead of std::string in ClangDiagnosticEmitter.
Commit: 95fa5f39a0506948bd3c81842c7828d7892023cd
https://github.com/llvm/llvm-project/commit/95fa5f39a0506948bd3c81842c7828d7892023cd
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/test/AST/ast-print-openacc-combined-construct.cpp
Log Message:
-----------
[OpenACC] Fix ast-print test that failed due to copy/paste error
Commit: 98c4f4fce84bb7b0943be92d06765ed4dff28710
https://github.com/llvm/llvm-project/commit/98c4f4fce84bb7b0943be92d06765ed4dff28710
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove IVEndValues, use resume value directly from fixed phi.(NFC)
Use the IV resume/end values from the phis in the scalar header,
instead of collecting them in a map. This removes some complexity
from the code dealing with induction resume values.
Analogous to 1edd22030 which did the same for reduction resume values.
Commit: 0dcb0acf8265e1486f4f3715cef01987af1391cd
https://github.com/llvm/llvm-project/commit/0dcb0acf8265e1486f4f3715cef01987af1391cd
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Fix false positives in warning againt 2-parameter std::span constructor (#115797)
Do not warn when two parameter constructor receives pointer address from
a std::addressof method and the span size is set to 1.
(rdar://139298119)
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 7a8fe0f83c4ba03d07aef9243596d67af74a3b87
https://github.com/llvm/llvm-project/commit/7a8fe0f83c4ba03d07aef9243596d67af74a3b87
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[SelectionDAG] Fixup type usage of CondCodeAction table (#116082)
Ensure that all uses of CondCodeAction table are checking the compared
types, not the produced type. This is a prerequisite to landing #115035
Commit: d50fbe43c9887e776cdfe95deaf312fb9cecfeaf
https://github.com/llvm/llvm-project/commit/d50fbe43c9887e776cdfe95deaf312fb9cecfeaf
Author: Amy Wang <kai.ting.wang at huawei.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/IR/CommonAttrConstraints.td
M mlir/python/mlir/dialects/affine.py
M mlir/test/python/dialects/affine.py
Log Message:
-----------
[MLIR][Python] Python binding support for AffineIfOp (#108323)
Fix the AffineIfOp's default builder such that it takes in an
IntegerSetAttr. AffineIfOp has skipDefaultBuilders=1 which effectively
skips the creation of the default AffineIfOp::builder on the C++ side.
(AffineIfOp has two custom OpBuilder defined in the
extraClassDeclaration.) However, on the python side, _affine_ops_gen.py
shows that the default builder is being created, but it does not accept
IntegerSet and thus is useless. This fix at line 411 makes the default
python AffineIfOp builder take in an IntegerSet input and does not
impact the C++ side of things.
Commit: de6d48d05d7aa233248d2f725654931cb1e2f6fd
https://github.com/llvm/llvm-project/commit/de6d48d05d7aa233248d2f725654931cb1e2f6fd
Author: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/Transforms/ConcatOpPatterns.cpp
M mlir/test/Dialect/Tensor/decompose-concat.mlir
Log Message:
-----------
[mlir][Tensor] Move concat operation decomposition as a method of the concat operation. (#116004)
Currently the implementation is within a pattern that cannot be used
without a pattern rewriter. Move the decomposition as a method of the
operation to make it usable outside of pattern rewrites.
Signed-off-by: MaheshRavishankar <mahesh.ravishankar at gmail.com>
Commit: 5ac624c8234fe0a62cbf0447dbf7035ea29d062e
https://github.com/llvm/llvm-project/commit/5ac624c8234fe0a62cbf0447dbf7035ea29d062e
Author: Farzon Lotfi <1802579+farzonl at users.noreply.github.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
A llvm/lib/Target/DirectX/DXILFlattenArrays.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
A llvm/test/CodeGen/DirectX/flatten-array.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
A llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-data.ll
M llvm/test/CodeGen/DirectX/scalar-load.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
Log Message:
-----------
[DirectX] Flatten arrays (#114332)
- Relevant piece is `DXILFlattenArrays.cpp`
- Loads and Store Instruction visits are just for finding
GetElementPtrConstantExpr and splitting them.
- Allocas needed to be replaced with flattened allocas.
- Global arrays were similar to allocas. Only interesting piece here is
around initializers.
- Most of the work went into building correct GEP chains. The approach
here was a recursive strategy via `recursivelyCollectGEPs`.
- All intermediary GEPs get marked for deletion and only the leaf GEPs
get updated with the new index.
fixes [89646](https://github.com/llvm/llvm-project/issues/89646)
Commit: be95e16d38724a78b6845868a06eb03db87e0a53
https://github.com/llvm/llvm-project/commit/be95e16d38724a78b6845868a06eb03db87e0a53
Author: AdityaK <hiraditya at msn.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
Log Message:
-----------
[NFC] Fix typos in LoopVersioningLICM.cpp (#116099)
Commit: 569c36e29c6563f97594994744abb3c0bf03da6c
https://github.com/llvm/llvm-project/commit/569c36e29c6563f97594994744abb3c0bf03da6c
Author: Chris B <chris.bieneman at me.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[DirectX] Add @bogner as DX backend maintainer (#114872)
@bogner has a long history with the LLVM community as a contributor and
maintainer of a wide array of project areas. He is providing a lot of
the leadership and direction for the contributors working on the DirectX
backend, and should be recognized as its maintainer.
Commit: 9778fc76e3342cc5d6ac36feef63631eb065c57f
https://github.com/llvm/llvm-project/commit/9778fc76e3342cc5d6ac36feef63631eb065c57f
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
Revert "AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)" (#116091)
Based on the suggestion from
https://github.com/llvm/llvm-project/pull/115543, we should not do the
pattern matching from x << (32-y) >> (32-y) to "bfe x, 0, y" at all.
This reverts commits a2bacf8ab58af4c1a0247026ea131443d6066602 and
https://github.com/llvm/llvm-project/commit/bdf8e308b7ea430f619ca3aa1199a76eb6b4e2d4.
Commit: e8c07f7458285c6fb2eddff5b7914519de10474d
https://github.com/llvm/llvm-project/commit/e8c07f7458285c6fb2eddff5b7914519de10474d
Author: Ethan Luis McDonough <ethanluismcdonough at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/test/MC/AMDGPU/reloc-directive.s
Log Message:
-----------
[MC][AMDGPU] Support .reloc BFD_RELOC_{NONE,32,64} (#114617)
Emitting BFD_RELOC_* reloc directives can cause internal errors on
AMDGPU.
Commit: fd2e4004cd01cd1cdf65cf643ca9c178c91741dc
https://github.com/llvm/llvm-project/commit/fd2e4004cd01cd1cdf65cf643ca9c178c91741dc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Add XLenVT casts in isel patterns that output 2 GPR instructions.
See #81192 for why we need to do this.
Commit: ec066d30e29fce388b1722971970d73ec65f14fb
https://github.com/llvm/llvm-project/commit/ec066d30e29fce388b1722971970d73ec65f14fb
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] cuf.alloc in device context should be converted to fir.alloc (#116110)
Update `inDeviceContext` to account for the gpu.func operation.
Commit: fa0cf3d39e03c3c63478f30a4c8c17d119b54b7f
https://github.com/llvm/llvm-project/commit/fa0cf3d39e03c3c63478f30a4c8c17d119b54b7f
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangle.h
M llvm/include/llvm/IR/Mangler.h
M llvm/lib/Demangle/MicrosoftDemangle.cpp
M llvm/lib/IR/Mangler.cpp
M llvm/unittests/IR/ManglerTest.cpp
Log Message:
-----------
[llvm][aarch64] Fix Arm64EC name mangling algorithm (#115567)
Arm64EC uses a special name mangling mode that adds `$$h` between the
symbol name and its type. In MSVC's name mangling `@` is used to
separate the name and type BUT it is also used for other purposes, such
as the separator between paths in a fully qualified name.
The original algorithm was quite fragile and made assumptions that
didn't hold true for all MSVC mangled symbols, so instead of trying to
improve this algorithm we are now using the demangler to indicate where
the insertion point should be (i.e., to parse the fully-qualified name
and return the current string offset).
Also fixed `isArm64ECMangledFunctionName` to search for `@$$h` since the
`$$h` must always be after a `@`.
Fixes #115231
Commit: adfa6b762dc53bc53377785d824264a3311e829d
https://github.com/llvm/llvm-project/commit/adfa6b762dc53bc53377785d824264a3311e829d
Author: Richard Smith <richard at metafoo.co.uk>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Document that the lifetime of the caller-side `trivial_abi` parameter ends before the call. (#116100)
Fixes #116096.
Commit: 6c9256dc5cda9184e295bc8d00be35e61b3be892
https://github.com/llvm/llvm-project/commit/6c9256dc5cda9184e295bc8d00be35e61b3be892
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M compiler-rt/lib/asan/asan_descriptions.cpp
Log Message:
-----------
[ASAN] fix a nullptr dereference error. (#116011)
`parent_context` is used without checking for nullptr and we can see in
LINE 50 that it could totally be nullptr. This patch addresses this
issue.
Commit: 73b577cc8c8a8ceeac87de5953a2c643e125d43e
https://github.com/llvm/llvm-project/commit/73b577cc8c8a8ceeac87de5953a2c643e125d43e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
Log Message:
-----------
[WebKit checkers] Treat ref() and incrementCheckedPtrCount() as trivial (#115695)
Treat member function calls to ref() and incrementCheckedPtrCount() as
trivial so that a function which returns RefPtr/Ref out of a raw
reference / pointer is also considered trivial.
Commit: b4d23cf6853a1e3971f27eae3b58609f77829252
https://github.com/llvm/llvm-project/commit/b4d23cf6853a1e3971f27eae3b58609f77829252
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/remarks-reduction-inloop.ll
Log Message:
-----------
[LV] Fix missing precomptueCosts() in emitInvalidCostRemarks(). (#114918)
We should always update the `SkipComputation` which is set in
`VPCostContext` before VPlan compute costs.
This patch prevent the assertion of in-loop reduction in the
`VPReductionRecipe::computeCost()` and other potential assertions of
partially implemented VPlan-based cost model.
Commit: c03b6e89434c11c936dc2fa8b01f1deb95b1923a
https://github.com/llvm/llvm-project/commit/c03b6e89434c11c936dc2fa8b01f1deb95b1923a
Author: Greg Roth <grroth at microsoft.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
Log Message:
-----------
[SPIRV] Mark maybe unused extractSubvector variable (#116117)
Change #115178 introduced a variable that is only used in an assert,
which could result in an unused variable warning in builds without
asserts enabled. This just addes the maybe_unused attribute to silence
the warning.
Commit: 1f0e0da3af783fd2bb5e23bc2b97141abac68926
https://github.com/llvm/llvm-project/commit/1f0e0da3af783fd2bb5e23bc2b97141abac68926
Author: Greg Roth <grroth at microsoft.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] update Apple undefined symbol link flag from suppress (#116113)
the -undefined suppress option for Apple's linker is deprecated and was
producing multiple warnings. This updates it to dynamic_lookup, which
has much the same effect, but avoids these deprecation warnings.
Commit: e5092c301959b599ffd51b7942a8bed5c4be54de
https://github.com/llvm/llvm-project/commit/e5092c301959b599ffd51b7942a8bed5c4be54de
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/convert-to-llvm.fir
Log Message:
-----------
[flang][cuda] Support malloc and free conversion in gpu module (#116112)
Commit: aed4356252df2a4ab2e430d77a29bdb3dfd874fc
https://github.com/llvm/llvm-project/commit/aed4356252df2a4ab2e430d77a29bdb3dfd874fc
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect Conversion: Add `replaceOpWithMultiple` (#115816)
This commit adds a new function
`ConversionPatternRewriter::replaceOpWithMultiple`. This function is
similar to `replaceOp`, but it accepts multiple `ValueRange`
replacements, one per op result.
Note: This function is not an overload of `replaceOp` because of
ambiguous overload resolution that would make the API difficult to use.
This commit aligns "block signature conversions" with "op replacements":
both support 1:N replacements now. Due to incomplete 1:N support in the
dialect conversion driver, an argument materialization is inserted when
an SSA value is replaced with multiple values; same as block signature
conversions already work around the problem. These argument
materializations are going to be removed in a subsequent commit that
adds full 1:N support. The purpose of this PR is to add missing features
gradually in small increments.
This commit also updates two MLIR transformations that have their custom
workarounds around missing 1:N support. These can already start using
`replaceOpWithMultiple`.
Co-authored-by: Markus Böck <markus.boeck02 at gmail.com>
Commit: 6e614e11df6a152082b51a1b18332cb8730a4032
https://github.com/llvm/llvm-project/commit/6e614e11df6a152082b51a1b18332cb8730a4032
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
[clang][docs] Revise documentation for `__builtin_reduce_(max|min)`. (#114637)
The function operation described in the document did not match its
actual semantic meaning, this patch resolved the problem.
Commit: d23c5c2d6566fce4380cfa31d438422db19fbce9
https://github.com/llvm/llvm-project/commit/d23c5c2d6566fce4380cfa31d438422db19fbce9
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/include/llvm/CGData/StableFunctionMap.h
M llvm/include/llvm/CGData/StableFunctionMapRecord.h
A llvm/include/llvm/CodeGen/GlobalMergeFunctions.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
A llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-read.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-two-rounds.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-write.ll
M llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-double.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-single.test
M llvm/tools/llvm-cgdata/Opts.td
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
M llvm/unittests/CGData/StableFunctionMapTest.cpp
Log Message:
-----------
[CGData] Global Merge Functions (#112671)
This implements a global function merging pass. Unlike traditional
function merging passes that use IR comparators, this pass employs a
structurally stable hash to identify similar functions while ignoring
certain constant operands. These ignored constants are tracked and
encoded into a stable function summary. When merging, instead of
explicitly folding similar functions and their call sites, we form a
merging instance by supplying different parameters via thunks. The
actual size reduction occurs when identically created merging instances
are folded by the linker.
Currently, this pass is wired to a pre-codegen pass, enabled by the
`-enable-global-merge-func` flag.
In a local merging mode, the analysis and merging steps occur
sequentially within a module:
- `analyze`: Collects stable function hashes and tracks locations of
ignored constant operands.
- `finalize`: Identifies merge candidates with matching hashes and
computes the set of parameters that point to different constants.
- `merge`: Uses the stable function map to optimistically create a
merged function.
We can enable a global merging mode similar to the global function
outliner
(https://discourse.llvm.org/t/rfc-enhanced-machine-outliner-part-2-thinlto-nolto/78753/),
which will perform the above steps separately.
- `-codegen-data-generate`: During the first round of code generation,
we analyze local merging instances and publish their summaries.
- Offline using `llvm-cgdata` or at link-time, we can finalize all these
merging summaries that are combined to determine parameters.
- `-codegen-data-use`: During the second round of code generation, we
optimistically create merging instances within each module, and finally,
the linker folds identically created merging instances.
Depends on #112664
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: 474ed453f7a9ef1c4bcd9ba60f2ef20e0199d872
https://github.com/llvm/llvm-project/commit/474ed453f7a9ef1c4bcd9ba60f2ef20e0199d872
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port d23c5c2d6566
Commit: 287a34311e342d5573200fbc2c651fa665ccc062
https://github.com/llvm/llvm-project/commit/287a34311e342d5573200fbc2c651fa665ccc062
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/unittests/Support/YAMLIOTest.cpp
Log Message:
-----------
Reformat
Commit: 941f704f0892317701fd263603a729e0ef86dda6
https://github.com/llvm/llvm-project/commit/941f704f0892317701fd263603a729e0ef86dda6
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/unittests/Support/YAMLIOTest.cpp
Log Message:
-----------
[YAML] Make `std::array` available (#116059)
`std::array` will be handled like `MutableArrayRef`;
- Extending elements is not acceptable.
- For applying fewer sequence, trailing elements will be initialized by
default.
Not like;
- `std::array` is not the reference but holds values. Supposing to hold
small count of elements.
Commit: e9aee4fd80874f80556456f64c303ffb957bd614
https://github.com/llvm/llvm-project/commit/e9aee4fd80874f80556456f64c303ffb957bd614
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/unittests/Support/YAMLIOTest.cpp
Log Message:
-----------
Revert "[YAML] Make `std::array` available (#116059)"
Compilation failed on gcc hosts.
This reverts commit 941f704f0892317701fd263603a729e0ef86dda6.
(llvmorg-20-init-12117-g941f704f0892)
Commit: f407dff50cdcbcfee9dd92397d3792627c3ac708
https://github.com/llvm/llvm-project/commit/f407dff50cdcbcfee9dd92397d3792627c3ac708
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/MC/MCStreamer.cpp
A llvm/test/DebugInfo/X86/DW_AT_LLVM_stmt_seq_sec_offset.ll
Log Message:
-----------
[DebugInfo][DWARF] Emit Per-Function Line Table Offsets and End Sequences (#110192)
**Summary**
This patch introduces a new compiler option `-mllvm
-emit-func-debug-line-table-offsets` that enables the emission of
per-function line table offsets and end sequences in DWARF debug
information. This enhancement allows tools and debuggers to accurately
attribute line number information to their corresponding functions, even
in scenarios where functions are merged or share the same address space
due to optimizations like Identical Code Folding (ICF) in the linker.
**Background**
RFC: [New DWARF Attribute for Symbolication of Merged
Functions](https://discourse.llvm.org/t/rfc-new-dwarf-attribute-for-symbolication-of-merged-functions/79434)
Previous similar PR:
[#93137](https://github.com/llvm/llvm-project/pull/93137) – This PR was
very similar to the current one but at the time, the assembler had no
support for emitting labels within the line table. That support was
added in PR [#99710](https://github.com/llvm/llvm-project/pull/99710) -
and in this PR we use some of the support added in the assembler PR.
In the current implementation, Clang generates line information in the
`debug_line` section without directly associating line entries with
their originating `DW_TAG_subprogram` DIEs. This can lead to issues when
post-compilation optimizations merge functions, resulting in overlapping
address ranges and ambiguous line information.
For example, when functions are merged by ICF in LLD, multiple functions
may end up sharing the same address range. Without explicit linkage
between functions and their line entries, tools cannot accurately
attribute line information to the correct function, adversely affecting
debugging and call stack resolution.
**Implementation Details**
To address the above issue, the patch makes the following key changes:
**`DW_AT_LLVM_stmt_sequence` Attribute**: Introduces a new LLVM-specific
attribute `DW_AT_LLVM_stmt_sequence` to each `DW_TAG_subprogram` DIE.
This attribute holds a label pointing to the offset in the line table
where the function's line entries begin.
**End-of-Sequence Markers**: Emits an explicit DW_LNE_end_sequence after
each function's line entries in the line table. This marks the end of
the line information for that function, ensuring that line entries are
correctly delimited.
**Assembler and Streamer Modifications**: Modifies the MCStreamer and
related classes to support emitting the necessary labels and tracking
the current function's line entries. A new flag
GenerateFuncLineTableOffsets is added to control this behavior.
**Compiler Option**: Introduces the `-mllvm
-emit-func-debug-line-table-offsets` option to enable this
functionality, allowing users to opt-in as needed.
Commit: 48cc43510931625ea23cd4ba621e5c0ddb12a452
https://github.com/llvm/llvm-project/commit/48cc43510931625ea23cd4ba621e5c0ddb12a452
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M lld/test/ELF/ppc64-local-exec-tls.s
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrFormats.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrSPE.td
M llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
M llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)
Commit 93589057830b2c3c35500ee8cac25c717a1e98f9 was reverted because it
caused a failure with test `lld :: ELF/ppc64-local-exec-tls.s`. This
relands the commit with a fix for the test.
Commit: 2283d50447369fc576eced8aca1cf0f54bdc235b
https://github.com/llvm/llvm-project/commit/2283d50447369fc576eced8aca1cf0f54bdc235b
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[LoongArch] add la v1.1 features for sys::getHostCPUFeatures (#115832)
Two features (i.e. `frecipe` and `lam-bh`) are added to
`sys.getHostCPUFeatures`. More features will be added in future.
In addition, this patch adds the features returned by
`sys.getHostCPUFeature` when `-march=native`.
Commit: be187369a03bf2df8bdbc76ecd381377b3bb6074
https://github.com/llvm/llvm-project/commit/be187369a03bf2df8bdbc76ecd381377b3bb6074
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp
M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
Log Message:
-----------
[AMDGPU] Remove unused includes (NFC) (#116154)
Identified with misc-include-cleaner.
Commit: d3da78863c7021fa2447a168dc03ad791db69dc6
https://github.com/llvm/llvm-project/commit/d3da78863c7021fa2447a168dc03ad791db69dc6
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
Log Message:
-----------
[CGData] Refactor Global Merge Functions (#115750)
This is a follow-up PR to refactor the initial global merge function
pass implemented in #112671.
It first collects stable functions relevant to the current module and
iterates over those only, instead of iterating through all stable
functions in the stable function map.
This is a patch for
https://discourse.llvm.org/t/rfc-global-function-merging/82608.
Commit: 0b54e33fd5ab362dfa5eacb61d7cbdb9cc3a89ac
https://github.com/llvm/llvm-project/commit/0b54e33fd5ab362dfa5eacb61d7cbdb9cc3a89ac
Author: s-watanabe314 <watanabe.shu-06 at fujitsu.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/lib/Lower/CallInterface.cpp
M flang/test/Lower/HLFIR/select-rank.f90
M flang/test/Lower/attributes.f90
Log Message:
-----------
[flang] Add FIR attributes and apply them to dummy arguments (#115686)
To determine if a function's dummy argument is nocapture, add the
asynchronous attribute to the FIR attribute. The volatile attribute will
also be used to determine nocapture assignment, but this will remain a
TODO until other processing using volatile is implemented.
I will post another patch to apply nocapture. See also the discussion in
the following discourse post.
https://discourse.llvm.org/t/applying-the-nocapture-attribute-to-reference-passed-arguments-in-fortran-subroutines/81401
Commit: 0341da561cd964b4f3341abfaebc0b5cf97c088b
https://github.com/llvm/llvm-project/commit/0341da561cd964b4f3341abfaebc0b5cf97c088b
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h
Log Message:
-----------
[NFC] Reformat comment (#116003)
Commit: 40edb0a1af3041d289fcdec3dd4c9368f2686429
https://github.com/llvm/llvm-project/commit/40edb0a1af3041d289fcdec3dd4c9368f2686429
Author: sstipano <146831748+sstipano at users.noreply.github.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
Log Message:
-----------
[AMDGPU] llvm.amdgcn.raw.buffer.load.format intrinsic supports v4i32 as return type. (#116067)
Commit: 5a2888ddbd7a601c8ad6bf7b5f13bf77318e4a4d
https://github.com/llvm/llvm-project/commit/5a2888ddbd7a601c8ad6bf7b5f13bf77318e4a4d
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalMergeFunctions.cpp
Log Message:
-----------
Revert "[CGData] Refactor Global Merge Functions (#115750)"
This reverts commit d3da78863c7021fa2447a168dc03ad791db69dc6.
Commit: 813f7c3820d00349fe23bfc6ba26159764541540
https://github.com/llvm/llvm-project/commit/813f7c3820d00349fe23bfc6ba26159764541540
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxbf16transposeintrin.h
A clang/lib/Headers/amxcomplextransposeintrin.h
M clang/lib/Headers/amxfp16intrin.h
A clang/lib/Headers/amxfp16transposeintrin.h
M clang/lib/Headers/amxintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
M clang/test/CodeGen/X86/amx_transpose.c
M clang/test/CodeGen/X86/amx_transpose_api.c
M clang/test/CodeGen/X86/amx_transpose_errors.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
M llvm/test/MC/X86/amx-transpose-att.s
M llvm/test/MC/X86/amx-transpose-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-TRANSPOSE, part 2 (#115660)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: e5ca3ede0697e8a9cccafa08f641ee33eaefe320
https://github.com/llvm/llvm-project/commit/e5ca3ede0697e8a9cccafa08f641ee33eaefe320
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 813f7c3820d0
Commit: 5be43db9b17e7cfc9e987f257221b0926551eb6e
https://github.com/llvm/llvm-project/commit/5be43db9b17e7cfc9e987f257221b0926551eb6e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.cpp
M llvm/lib/Target/ARM/ARMLatencyMutations.cpp
M llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
M llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
Log Message:
-----------
[ARM] Remove unused includes (NFC) (#116155)
Identified with misc-include-cleaner.
Commit: 3d3b0bc239cd9c6e8c65ae26bdcf1534515c4beb
https://github.com/llvm/llvm-project/commit/3d3b0bc239cd9c6e8c65ae26bdcf1534515c4beb
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M lldb/test/Shell/Minidump/Windows/find-module.test
Log Message:
-----------
[lldb] Disable find-module.test in case of a remote target (#94165)
The target arch is `i386-pc-windows` after loading the dump. It updates
to `i386-pc-windows-msvc` or `i386-pc-windows-gnu` in
lldb\source\Plugins\Process\minidump\ProcessMinidump.cpp, line 218
```
GetTarget().MergeArchitecture(module->GetArchitecture());
```
But in case of the remote target (`remote-linux`) and the `Windows host`
lldb executed the following commands at the beginning
```
platform select remote-linux
platform connect connect://<ip>:<port>
```
and then the target arch is `i386-pc-windows-msvc` immediately after
loading the dump.
GetTarget().MergeArchitecture(module->GetArchitecture()) does not update
it to `i386-pc-windows-gnu` when the module arch is
`i386-pc-windows-gnu`.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: 627b8f87e2c499c62df2e9bd6048f795fd085545
https://github.com/llvm/llvm-project/commit/627b8f87e2c499c62df2e9bd6048f795fd085545
Author: Petr Hosek <phosek at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[Fuchsia][CMake] Enable new libc header gen" (#116174)
Reverts llvm/llvm-project#102371
Commit: 9a730d878e96e2a992f337acc94f897d47c920e3
https://github.com/llvm/llvm-project/commit/9a730d878e96e2a992f337acc94f897d47c920e3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-13 (Wed, 13 Nov 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[memprof] Add IndexedMemProfReader::getMemProfCallerCalleePairs (#115807)
Undrifting the MemProf profile requires two sets of information:
- caller-callee pairs from the profile
- callee-callee pairs from the IR
This patch adds a function to do the former. The latter has been
addressed by extractCallsFromIR.
Unfortunately, the current MemProf format does not directly give us
the caller-callee pairs from the profile. "struct Frame" just tells
us where the call site is -- Caller GUID and line/column numbers; it
doesn't tell us what function a given Frame is calling. To extract
caller-callee pairs, we need to scan each call stack, look at two
adjacent Frames, and extract a caller-callee pair.
Conceptually, we would extract caller-callee pairs with:
for each MemProfRecord in the profile:
for each call stack in AllocSites:
extract caller-callee pairs from adjacent pairs of Frames
However, this is highly inefficient. Obtaining MemProfRecord involves
looking up the OnDiskHashTable, allocating several vectors on the
heap, and populating fields that are irrelevant to us, such as MIB and
CallSites.
This patch adds an efficient way of doing the above. Specifically, we
- go though all IndexedMemProfRecords,
- look at each linear call stack ID
- extract caller-callee pairs from each call stack
The extraction is done by a new class CallerCalleePairExtractor,
modified from LinearCallStackIdConverter, which reconstructs a call
stack from the radix tree array. For our purposes, we skip the
reconstruction and immediately populates the data structure for
caller-callee pairs.
The resulting caller-callee-pairs is of the type:
DenseMap<uint64_t, SmallVector<CallEdgeTy, 0>> CallerCalleePairs;
which can be passed directly to longestCommonSequence just like the
result of extractCallsFromIR.
Further performance optimizations are possible for the new functions
in this patch. I'll address those in follow-up patches.
Commit: 9e77f59005917e32f09136fa43018f471267f5bd
https://github.com/llvm/llvm-project/commit/9e77f59005917e32f09136fa43018f471267f5bd
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
Log Message:
-----------
[LV] Account for vp_merge in out of loop EVL reductions in legacy cost model (#115903)
In #101641, support for out of loop reductions with EVL tail folding was
added by transforming selects to vp_merges in
transformRecipestoEVLRecipes.
Whilst the select was previously free, the vp_merge wasn't and incurs a
cost on RISC-V with the VPlan cost model. But this diverged from the
legacy cost model and caused the "VPlan cost model and legacy cost model
disagreed" assertion to trigger when building 502.gcc_r from SPEC CPU
2017.
Neither the select nor vp_merge recipes from the VPlan exist in the
underlying instructions, so I thought it would make the most sense to
fix this by adding the cost to the underlying phi instruction in
getInstructionCost.
It's worth noting that on RISC-V this vp_merge won't actually generate
any instructions because the mask is all true, and will be folded away.
So we should update the cost model at some point to reflect that.
Commit: 050e2d325a09a27418898e45fd064d3f62e825e7
https://github.com/llvm/llvm-project/commit/050e2d325a09a27418898e45fd064d3f62e825e7
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
Log Message:
-----------
[LV] Remove assertions in IV overflow check (#115705)
In #111310 an assert was added that for the IV overflow check used with
tail folding, the overflow check is never known.
However when applying the loop guards, it looks like it's possible that
we might actually know the IV won't overflow: this occurs in
500.perlbench_r from SPEC CPU 2017 and triggers the assertion:
Assertion failed: (!isIndvarOverflowCheckKnownFalse(Cost, VF * UF) &&
!SE.isKnownPredicate(CmpInst::getInversePredicate(ICmpInst::ICMP_ULT),
TC2OverflowSCEV, SE.getSCEV(Step)) && "unexpectedly proved overflow
check to be known"), function emitIterationCountCheck, file
LoopVectorize.cpp, line 2501.
There is a discrepancy between `isIndvarOverflowCheckKnownFalse` and the
ICMP_ULT check, because the former uses `getSmallConstantMaxTripCount`
which only takes into trip counts that fit into 32 bits. There doesn't
seem to be an easy way to make the assertion aware of this, so this PR
just removes it for now.
There are two potential follow up things from this PR:
1. We miss calculating the max trip count in `@trip_count_max_1024`, it
looks like we might need to apply loop guards somewhere in
`ScalarEvolution::computeExitLimitFromICmp`
2. In `@overflow_at_0`, if `%tc == 0` then we the overflow check will
always return false, even though it will overflow
Fixes https://github.com/llvm/llvm-project/issues/115755
Commit: 5cfa8baef33636827e5aa8dd76888c724433b53e
https://github.com/llvm/llvm-project/commit/5cfa8baef33636827e5aa8dd76888c724433b53e
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
Log Message:
-----------
[LoongArch] Fix a typo in LoongArchCCAssignFn. NFC (#116178)
Commit: 2e6deb1dd3a4422807633ba08773e8d786e43d4c
https://github.com/llvm/llvm-project/commit/2e6deb1dd3a4422807633ba08773e8d786e43d4c
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
A llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
Log Message:
-----------
[LoopInterchange] Fix overflow in cost calculation (#111807)
If the iteration count is really large, e.g. UINT_MAX, then the cost
calculation can overflows and trigger an assert. So saturate the cost to
INT_MAX if this is the case by using InstructionCost as a type which
already supports this kind of overflow handling.
This fixes #104761
Commit: d119d43e92333966125755353f4e6227dd2c70da
https://github.com/llvm/llvm-project/commit/d119d43e92333966125755353f4e6227dd2c70da
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
Log Message:
-----------
[LV] Add missing REQUIRES: asserts to test
Commit: debfd7b0b44d8eb0bfe9f69933251a67f752f0b5
https://github.com/llvm/llvm-project/commit/debfd7b0b44d8eb0bfe9f69933251a67f752f0b5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
Log Message:
-----------
[msan] Remove unnecacary zero increment (#116185)
Commit: e52238b59f250aef5dc0925866d0308305a19dbf
https://github.com/llvm/llvm-project/commit/e52238b59f250aef5dc0925866d0308305a19dbf
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
A llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
Log Message:
-----------
[AArch64] Add @llvm.experimental.vector.match (#101974)
This patch introduces an experimental intrinsic for matching the
elements of one vector against the elements of another.
For AArch64 targets that support SVE2, the intrinsic lowers to a MATCH
instruction for supported fixed and scalar vector types.
Commit: c1c68baf7e0fcaef1f4ee86b527210f1391b55f6
https://github.com/llvm/llvm-project/commit/c1c68baf7e0fcaef1f4ee86b527210f1391b55f6
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)
This is a step towards enabling subreg liveness tracking for AArch64,
which requires that registers are fully covered by their subregisters,
as covered here #109797.
There are several changes in this patch:
* AArch64RegisterInfo.td and tests: Define the high bits like B0_HI,
H0_HI, S0_HI, D0_HI, Q0_HI. Because the bits must be defined by some
register class, this added a register class which meant that we had to
update 'magic numbers' in several tests.
The use of ComposedSubRegIndex helped 'compress' the number of bits
required for the lanemask. The correctness of the masks is tested by an
explicit unit tests.
* LoadStoreOptimizer: previously 'HasDisjunctSubRegs' was only true for
register tuples, but with this change to describe the high bits, a
register like 'D0' will also have 'HasDisjunctSubRegs' set to true
(because it's fullly covered by S0 and S0_HI). The fix here is to
explicitly test if the register class is one of the known D/Q/Z tuples.
Commit: 2aa6cedfa81dafa0cd909bab64979310f9ec5e3d
https://github.com/llvm/llvm-project/commit/2aa6cedfa81dafa0cd909bab64979310f9ec5e3d
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU] Clarify amdgpu.cs.chain + init whole wave. NFC (#115452)
Add some docs clarifying how inactive lanes are handled in the
amdgpu_cs_chain calling convention when the llvm.amdgcn.init.whole.wave
intrinsic is used.
Commit: cb64c3c573d7239036d46addb3ea09f954ca3a55
https://github.com/llvm/llvm-project/commit/cb64c3c573d7239036d46addb3ea09f954ca3a55
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
A llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
Log Message:
-----------
[LoopInterchange] Precommit tests for scalar dependencies. NFC. (#115900)
We are miscompiling and incorrectly interchanging loops with scalar
dependencies that are live-out and conditionally set. This precommits
some tests demonstrating this. This is based on the tests in
https://reviews.llvm.org/D87879 by `mdchen`.
Commit: 78f7ca0980f3369da19e3cbb01890fe718307ac2
https://github.com/llvm/llvm-project/commit/78f7ca0980f3369da19e3cbb01890fe718307ac2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
Log Message:
-----------
[InstCombine] Use KnownBits predicate helpers (#115874)
Inside foldICmpUsingKnownBits(), instead of rolling our own logic based
on min/max values, make use of ICmpInst::compare() working on KnownBits.
This gives better results for the equality predicates. In practice, the
improvement is only for pointers, because isKnownNonEqual() handles the
non-pointer case.
I've adjusted some tests to prevent the new fold from triggering, to
retain their original intent of testing constant expressions.
Commit: d97f17a95982bab49ecdfb9b45ef3c7d7e3d143e
https://github.com/llvm/llvm-project/commit/d97f17a95982bab49ecdfb9b45ef3c7d7e3d143e
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
A llvm/test/MC/ARM/lower-upper-errors-2.s
A llvm/test/MC/ARM/lower-upper-errors.s
Log Message:
-----------
[MC][ARM] Fix crash when assembling Thumb 'movs r0,#foo'. (#115026)
If the assembler sees this instruction, understanding `foo` to be an
external symbol, there's no relocation it can write that will put the
whole value of `foo` into the 8-bit immediate field of the 16-bit Thumb
add instruction. So it should report an error message pointing at the
source line, and in LLVM 18, it did exactly that. But now the error is
not reported, due to an indexing error in the operand list in
`validateInstruction`, and instead the code continues to attempt
assembly, ending up aborting at the `llvm_unreachable` at the end of
`getHiLoImmOpValue`.
In this commit I've fixed the index in the `ARM::tMOVi8` case of
`validateInstruction`, and also the one for `tADDi8` which must cope
with either the 2- or 3-operand form in the input assembly source. But
also, while writing the test, I found that if you assemble for Armv7-M
instead of Armv6-M, the instruction has opcode `t2ADDri` when it goes
through `validateInstruction`, and only turns into `tMOVi8` later in
`processInstruction`. Then it's too late for `validateInstruction` to
report that error. So I've adjusted `processInstruction` to spot that
case and inhibit the conversion.
Commit: b18bb240a8ea4d698deaf95a47df838d1352c504
https://github.com/llvm/llvm-project/commit/b18bb240a8ea4d698deaf95a47df838d1352c504
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port c1c68baf7e0f
Commit: caa9a827978536ea0047c75b32a8fedd6a1dcacf
https://github.com/llvm/llvm-project/commit/caa9a827978536ea0047c75b32a8fedd6a1dcacf
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/debugloc-optimize-vfuf-term.ll
Log Message:
-----------
[DebugInfo][LoopVectorizer] Avoid dropping !dbg in optimizeForVFAndUF (#114243)
Prior to this patch, optimizeForVFAndUF may optimize the conditional
branch for a VPBasicblock to have a constant condition, but
unnecessarily drops the DILocation attachment when it does so; this
patch changes it to preserve the DILocation.
Commit: ec1e0c5ecd53e415b23d5bd40b8e44e3ef4b4d92
https://github.com/llvm/llvm-project/commit/ec1e0c5ecd53e415b23d5bd40b8e44e3ef4b4d92
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/unparse-with-symbols.cpp
A flang/test/Lower/OpenMP/Todo/omp-declare-mapper.f90
A flang/test/Parser/OpenMP/declare-mapper-unparse.f90
A flang/test/Semantics/OpenMP/declare-mapper-symbols.f90
A flang/test/Semantics/OpenMP/declare-mapper01.f90
A flang/test/Semantics/OpenMP/declare-mapper02.f90
A flang/test/Semantics/OpenMP/declare-mapper03.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[Flang][OMP]Add support for DECLARE MAPPER parsing and semantics (#115160)
Will hit a TODO in the lowering, which there are tests added to check
for this happening.
Commit: d9e2fb70d0b72b398fef3106bab0605b5b3e6761
https://github.com/llvm/llvm-project/commit/d9e2fb70d0b72b398fef3106bab0605b5b3e6761
Author: k-kashapov <52855633+k-kashapov at users.noreply.github.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/mmx-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/msan_i386_bts_asm.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/msan_i386intrinsics.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/msan_x86_bts_asm.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/msan_x86intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse41-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse41-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg-too-large.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_call.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
Log Message:
-----------
[msan] Add 32-bit platforms support (#109284)
References https://github.com/llvm/llvm-project/issues/103057
Added `VAArgHelper` functions for platforms: ARM32, i386, RISC-V,
PowerPC32, MIPS32.
ARM, RISCV and MIPS share similar conventions regarding va args.
Therefore `VAArgGenericHelper` was introduced to avoid code duplication.
---------
Co-authored-by: Kamil Kashapov <kashapov at ispras.ru>
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 1ef4d3b6bf9879a21b15e62e7d4323973914feb0
https://github.com/llvm/llvm-project/commit/1ef4d3b6bf9879a21b15e62e7d4323973914feb0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] canonicalizeBitSelect/combineLogicBlendIntoPBLENDV - avoid SDLoc duplication. NFC.
Reuse caller's equivalent SDLoc
Commit: d686e5cdafab7c6d8fb9d27ec428cf3b9d145c56
https://github.com/llvm/llvm-project/commit/d686e5cdafab7c6d8fb9d27ec428cf3b9d145c56
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
A llvm/test/Transforms/InstCombine/debugloc-bswap.ll
Log Message:
-----------
[DebugInfo][InstCombine] When replacing bswap idiom, add DebugLoc to new insts (#114231)
Currently when InstCombineAndOrXor recognizes a bswap idiom and replaces
it with an intrinsic and other instructions, only the last instruction
gets the DebugLoc of the replaced instruction set to it. This patch
applies the DebugLoc to all the generated instructions, to maintain some
degree of attribution.
Commit: 6721bcfd1b6494e9643a04a13144f282979544ad
https://github.com/llvm/llvm-project/commit/6721bcfd1b6494e9643a04a13144f282979544ad
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M libcxx/include/__memory/uninitialized_algorithms.h
Log Message:
-----------
[libc++] Accept iterators instead of raw pointers in __uninitialized_allocator_relocate (#114552)
This generalizes the algorithm a bit. Unfortunately, we can't make
the call sites cleaner inside std::vector because the arguments being
passed can all be fancy pointers, which may not be contiguous iterators.
Commit: b468ed494acde4d1cc496a436ab9109660db5b80
https://github.com/llvm/llvm-project/commit/b468ed494acde4d1cc496a436ab9109660db5b80
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/test/CodeGen/X86/no-non-zero-debug-loc-prologue.ll
M llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
A llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
A llvm/test/DebugInfo/X86/dbg-prolog-end-backup-loc.ll
M llvm/test/DebugInfo/X86/dbg-prolog-end.ll
M llvm/test/DebugInfo/X86/empty-line-info.ll
M llvm/test/DebugInfo/X86/loop-align-debug.ll
Log Message:
-----------
Reapply ccddb6ffad1, "Emit a worst-case prologue_end"
In 39b2979a4 Pavel has kindly refined the implementation of a test in such
a way that it doesn't trip up over this patch -- the test wishes to
stimulate LLDBs presentation of line0 locations, rather than wanting to
always step on line-zero on entry to artificial_location.c. As that's what
was tripping up this change, reapply.
Original commit message follows.
[DWARF] Emit a worst-case prologue_end flag for pathological inputs (#107849)
prologue_end usually indicates where the end of the function-initialization
lies, and is where debuggers usually choose to put the initial breakpoint
for a function. Our current algorithm piggy-backs it on the first available
source-location: which doesn't necessarily have anything to do with the
start of the function.
To avoid this in heavily-optimised code that lacks many useful source
locations, pick a worst-case "if all else fails" prologue_end location, of
the first instruction that appears to do meaningful computation. It'll be
given the function-scope line number, which should run-on from the start of
the function anyway. This means if your code is completely inverted by the
optimiser, you can at least put a breakpoint at the _start_ like you
expect, even if it's difficult to then step through.
This patch also attempts to preserve some good behaviour we have without
optimisations -- at O0, if the prologue immediately falls into a loop body
without any computation happening, then prologue_end lands at the start of
that loop. This is desirable; but does mean we need to do more work to
detect and support those situations.
Commit: 9b6b9d39030f92ea20d8f38ef37305e99cfc6d60
https://github.com/llvm/llvm-project/commit/9b6b9d39030f92ea20d8f38ef37305e99cfc6d60
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
Log Message:
-----------
Default initialize a pointer in CodeExtractor.
This fixes msan failure after f6795e6b4f619cbecc59a92f7e5fad7ca90ece54
Commit: dd9f1a572b7c98b6761281bfa2d6bb351cbedb61
https://github.com/llvm/llvm-project/commit/dd9f1a572b7c98b6761281bfa2d6bb351cbedb61
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/cmp-alloca-offsets.ll
Log Message:
-----------
[InstSimplify] Correctly handle comparison with zero-size allocs (#115728)
InstSimplify currently folds alloc1 == alloc2 to false, even if one of
them is a zero-size allocation. A zero-size allocation may have the same
address as another allocation.
This also disables the fold for the case where we're comparing a
zero-size alloc with the middle of another allocation. It's possible
that this case is legal to fold depending on our precise zero-size
allocation semantics, but LangRef currently doesn't specify this either
way, so we shouldn't make assumptions here.
Commit: 905256ad2ff136ec15e4c1a822412c87881876b8
https://github.com/llvm/llvm-project/commit/905256ad2ff136ec15e4c1a822412c87881876b8
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M lldb/test/Shell/Minidump/Windows/find-module.test
Log Message:
-----------
[lldb] Fixed find-module.test in case of a remote target (#116198)
Changing from UNSUPPOERTED to XFAIL in #94165 break x86 linux host /
Aarch64 linux target build
https://lab.llvm.org/buildbot/#/builders/195/builds/1047
Commit: 748b028540de67000345dfb3454ccd011ace4bb5
https://github.com/llvm/llvm-project/commit/748b028540de67000345dfb3454ccd011ace4bb5
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/AArch64/fmv-dependencies.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sme-features.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Make +sve2-aes an alias of +sve2+sve-aes (#116026)
This patch essentially re-lands
https://github.com/llvm/llvm-project/pull/114293 with the following
fixups
- `nosve2-aes` should disable the backend feature `FeatureSVEAES` such
that the set of existing instructions that this removes is unchanged.
- FMV dependencies now use the autogenerated `ExtensionDepencies`
structure (since https://github.com/llvm/llvm-project/pull/113281) so we
do not require the change to `AArch64FMV.td`.
Commit: 980316ec85381f65c369cb650f25881e470857b7
https://github.com/llvm/llvm-project/commit/980316ec85381f65c369cb650f25881e470857b7
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/unittests/Support/YAMLIOTest.cpp
Log Message:
-----------
[YAML] Recommit "Make `std::array` available (#116059)" with a fix.
`std::array` will be handled like `MutableArrayRef`;
- Extending elements is not acceptable.
- For applying fewer sequence, trailing elements will be initialized by
default.
Not like;
- `std::array` is not the reference but holds values. Supposing to hold
small count of elements.
Changes since llvmorg-20-init-12117-g941f704f0892:
- Use `size_t` for `N`, instead of `unsigned`.
- include <array>
Commit: 33a9c2642390dfe32cab82e0571712b5b2410c35
https://github.com/llvm/llvm-project/commit/33a9c2642390dfe32cab82e0571712b5b2410c35
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
A mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
Log Message:
-----------
[mlir][tensor] Add e2e test for tensor.pack with dynamic tile sizes (#115698)
Adds an end-to-end test for `tensor.pack` with dynamic inner tile sizes.
While relatively simple (e.g., no vectorization), this example required
a few non-trivial fixes in handling `tensor.pack`:
* #114315, #114559, #113108.
The end goal for this test is to incrementally increase its complexity
and to work towards scalable tile sizes.
Commit: 8ff2da782d676edddc19d856a853c1ebab999fc2
https://github.com/llvm/llvm-project/commit/8ff2da782d676edddc19d856a853c1ebab999fc2
Author: Abdul Raheem <55028856+abdulraheembeigh at users.noreply.github.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
Log Message:
-----------
[MLIR][NFC] Fix comment formatting and use 3 slashes (#116201)
NFC making a consistent indentation.
Corrected comment syntax. Changed // to ///
and nit grammatical change.
Commit: 576865a50e6ccb74196c9491fa79575d6d7f0b0b
https://github.com/llvm/llvm-project/commit/576865a50e6ccb74196c9491fa79575d6d7f0b0b
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
Fix up MCPlusBuilder.cpp to account for W0_HI on AArch64
Landing #114827 broke these tests, because they did not account
for the new artificial registers.
Commit: e58949632e91477af58d983f3b66369e6a2c8233
https://github.com/llvm/llvm-project/commit/e58949632e91477af58d983f3b66369e6a2c8233
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/utils/libcxx/test/format.py
Log Message:
-----------
[libc++] Define all CMake configuration features in the same location (#115361)
This moves the configuration of the CMake features to turn off RTTI,
exceptions and friends to the beginning of the CMake file, where we
configure other optional parts of the library.
This fixes an important bug where we would disable the benchmarks
because these options were not defined yet, leading to the build
thinking they were defined to OFF.
Commit: 8fde648aad1affa4e8680a9fd14a0816d73e5774
https://github.com/llvm/llvm-project/commit/8fde648aad1affa4e8680a9fd14a0816d73e5774
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M libcxx/include/forward_list
M libcxx/include/list
Log Message:
-----------
[libc++] Remove obsolete accessors in std::list and std::forward_list (#115748)
We don't need these accessors anymore now that we stopped using
compressed-pair.
Commit: 862f42eedf21cc28f4bc692ab846c87b28b5960b
https://github.com/llvm/llvm-project/commit/862f42eedf21cc28f4bc692ab846c87b28b5960b
Author: Sam Elliott <quic_aelliott at quicinc.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/ls64-inline-asm.ll
Log Message:
-----------
[TargetLowering] Use Correct VT for Multi-out Asm (#116024)
This was overlooked in 7d940432c46be83b8fcb5dbefee439585fa820cd - when
inline assembly has multiple outputs, they are returned as members of a
struct, and the `getAsmOperandType` needs to be called for each member
of struct. The difference between this and the single-output case is
that in the latter, there isn't a struct wrapping the outputs.
I noticed this when trying to use the same mechanism in the RISC-V
backend.
Committing two tests:
- One that shows a crash before this change, which is fixed by this
change.
- One (commented out) that shows a different crash with tied
inputs/outputs. This is commented as it is not fixed by this change and
needs more work in target-independent inline asm handling code.
Commit: 402efa733c64bd20b54dbc5b7057868cbb938d07
https://github.com/llvm/llvm-project/commit/402efa733c64bd20b54dbc5b7057868cbb938d07
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[mlir][LLVM] Remove redundant `custom<LLVMOpAttrs>` (#116207)
This custom printer was previously used to avoid printing fast math
flags if they have default values.
This is redundant however, as `attr-dict` will already elide attributes
whose default values are set, making it a noop nowadays.
Commit: 5c3befb91cd774161e5d700cf2c351d42d29927c
https://github.com/llvm/llvm-project/commit/5c3befb91cd774161e5d700cf2c351d42d29927c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M libcxx/include/__memory/uninitialized_algorithms.h
Log Message:
-----------
[libc++] Add forgotten call to std::__to_address in __uninitialized_allocator_relocate
Commit: 965f3a95b94a6787736f739018ce3a98e3880e84
https://github.com/llvm/llvm-project/commit/965f3a95b94a6787736f739018ce3a98e3880e84
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.pass.cpp
Log Message:
-----------
[libc++][NFC] Run clang-format on vector::erase test
Since I am about to make significant changes to this test, run clang-format
on it before to avoid obscuring the review.
Commit: 43bef75fd65083349ec888fadfb99987f7804d18
https://github.com/llvm/llvm-project/commit/43bef75fd65083349ec888fadfb99987f7804d18
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
Log Message:
-----------
[NFC][CodeGen] Clang format MachineSink.cpp (#114027)
Preparing to port this pass to new pass manager.
Commit: b96c24b8613036749e7ba28f0c7a837115ae9f91
https://github.com/llvm/llvm-project/commit/b96c24b8613036749e7ba28f0c7a837115ae9f91
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
Log Message:
-----------
[analyzer] Allow copying empty structs (1/4) (#115916)
We represent copies of structs by LazyCompoundVals, that is basically a
snapshot of the Store and Region that your copy would refer to.
This snapshot is actually not taken for empty structs (structs that have
no non-static data members), because the users won't be able to access
any fields anyways, so why bother.
However, when it comes to taint propagation, it would be nice if
instances of empty structs would behave similar to non-empty structs.
For this, we need an identity for which taint can bind, so Unknown -
that was used in the past wouldn't work.
Consequently, copying the value of an empty struct should behave the
same way as a non-empty struct, thus be represented by a
LazyCompoundVal.
Split from #114835
Commit: 251958f3570730f58d1337ac6d00f03ee6a839fe
https://github.com/llvm/llvm-project/commit/251958f3570730f58d1337ac6d00f03ee6a839fe
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Log Message:
-----------
[DebugInfo] Don't pick prologue_end if there are no instructions
Add a filter to avoid picking prologue_end when a function is empty (it may
have blocks but no instructions). This saves us from pushing more
validity-checking into findPrologueEndLoc.
Commit: 9f06129e55a09ea6442b50a541a5ac55577c6a22
https://github.com/llvm/llvm-project/commit/9f06129e55a09ea6442b50a541a5ac55577c6a22
Author: Malay Sanghi <malay.sanghi at intel.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
A .icslock
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/immintrin.h
A clang/lib/Headers/movrsintrin.h
A clang/test/CodeGen/X86/movrs-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
A llvm/test/CodeGen/X86/movrs-builtins.ll
A llvm/test/CodeGen/X86/movrs-prefetch-builtins.ll
A llvm/test/MC/Disassembler/X86/movrs.txt
A llvm/test/MC/Disassembler/X86/prefetchrst2-32.txt
A llvm/test/MC/Disassembler/X86/prefetchrst2-64.txt
A llvm/test/MC/X86/movrs-att-64.s
A llvm/test/MC/X86/movrs-intel-64.s
A llvm/test/MC/X86/prefetchrst2-att-32.s
A llvm/test/MC/X86/prefetchrst2-att-64.s
A llvm/test/MC/X86/prefetchrst2-intel-32.s
A llvm/test/MC/X86/prefetchrst2-intel-64.s
Log Message:
-----------
[X86][MOVRS] Support MOVRS (#116181)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: 3f40ad7ba83ecf6f374039191ae7ceeb1f5fe831
https://github.com/llvm/llvm-project/commit/3f40ad7ba83ecf6f374039191ae7ceeb1f5fe831
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/TargetInfo.h
M clang/test/CodeGen/attr-ifunc.c
A clang/test/CodeGen/ifunc-win.c
M clang/test/CodeGen/ifunc.c
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
Log Message:
-----------
Add ifunc support for Windows on AArch64. (#111962)
On Windows there is no platform support for ifunc but we could lower
them to global function pointers.
This also enables FMV for Windows with Clang and Compiler-rt.
Depends on #111961
Commit: 8781a4320c9b0ef00d1907341cf347759b9a822d
https://github.com/llvm/llvm-project/commit/8781a4320c9b0ef00d1907341cf347759b9a822d
Author: David Truby <david.truby at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/iterator_range.h
Log Message:
-----------
[NFC] Check for defined(__GNUC__) before use (#116076)
This silences some spurious warnings on Windows builds with clang-cl
that `__GNUC__` is not defined if `-Wundef` is passed, which is the default
in MLIR.
These warnings make Windows builds of LLVM very noisy when MLIR is
included.
Commit: 9685681aa47561c9941bb70aa84a09c55c7db824
https://github.com/llvm/llvm-project/commit/9685681aa47561c9941bb70aa84a09c55c7db824
Author: Edd Dawson <edd.dawson at sony.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps5-linker.c
Log Message:
-----------
[PS5][Driver] Supply libraries and CRT objects to the linker (#115497)
Until now, these have been hardcoded as a downstream patches in lld. Add
them to the driver so that the private patches can be removed.
PS5 only. On PS4, the equivalent hardcoded configuration will remain in
the proprietary linker.
SIE tracker: TOOLCHAIN-16704
Commit: 9e1faa834173f57344a12b1a0a2f90b8e903c7bd
https://github.com/llvm/llvm-project/commit/9e1faa834173f57344a12b1a0a2f90b8e903c7bd
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
R .icslock
Log Message:
-----------
[NFC] Delete stray file introduced by #116181 (#116235)
Commit: 0192ae5ce047424caf4ff51c8ce813a8cdf298ed
https://github.com/llvm/llvm-project/commit/0192ae5ce047424caf4ff51c8ce813a8cdf298ed
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 9f06129e55a0
Commit: 562d235cbc0dfc2e54d268df5db118c461b10d97
https://github.com/llvm/llvm-project/commit/562d235cbc0dfc2e54d268df5db118c461b10d97
Author: Joe Nash <joseph.nash at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
Log Message:
-----------
[AMDGPU][True16][MC] Copy True16Predicate from pseudo to real in VOP1 (#116098)
This is a necessary change for consistency and an upcoming patch.
Cleanup an affected extra whitespace and wrong CHECK prefix in
v_swap_b16.
Commit: 8ac46d6b4f8dff07730c4c0dff20d969efcf14f2
https://github.com/llvm/llvm-project/commit/8ac46d6b4f8dff07730c4c0dff20d969efcf14f2
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll
M llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
A llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-vs-calllowering-unwrapped.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-vs-calllowering.ll
Log Message:
-----------
[SPIR-V] Implement builtins for OpIAddCarry/OpISubBorrow and improve/fix type inference (#115192)
This PR is to solve several intertwined issues with type inference while
adding support for builtins for OpIAddCarry and OpISubBorrow:
* OpIAddCarry and OpISubBorrow generation in a way of supporting SPIR-V
friendly builtins `__spirv_...` -- introduces a new element to account
for, namely, `ptr sret (%struct) %0` argument that is a place to put a
result of the instruction;
* fix early definition of SPIR-V types during call lowering -- namely,
the goal of the PR is to ensure that correct types are applied to
virtual registers which were used as arguments in call lowering and so
caused early definition of SPIR-V types; reproducers are attached as a
new test cases;
* improve parsing of builtin names (e.g., understand a name of a kind
`"anon<int, int> __spirv_IAddCarry<int, int>(int, int)"` that was
incorrectly parsed as `anon` before the PR);
* improve type inference and fix access to erased from parent after
visit instructions -- before the PR visiting of instructions in
emitintrinsics pass replaced old alloca's, bitcast's, etc. instructions
with a newly generated internal SPIR-V intrinsics and after erasing old
instructions there were still references to them in a postprocessing
working list, while records for newly deduced pointee types were lost;
this PR fixes the issue by adding as consistent wrt. internal data
structures action `SPIRVEmitIntrinsics::replaceAllUsesWith()` that fixes
above mentioned problems;
* LLVM IR add/sub instructions result in logical SPIR-V instructions
when applied to bool type;
* fix validation of pointer types for frexp and lgamma_r,
* fix hardcoded reference to AS0 as a Function storage class in
lib/Target/SPIRV/SPIRVBuiltins.cpp -- now it's
`storageClassToAddressSpace(SPIRV::StorageClass::Function)`,
* re-use the same OpTypeStruct for two identical references to struct's
in arithmetic with overflow instructions.
Commit: b7f7e6454877846d2ee4be8cae821b2c32501b1e
https://github.com/llvm/llvm-project/commit/b7f7e6454877846d2ee4be8cae821b2c32501b1e
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-combined-construct.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-default-ast.cpp
A clang/test/SemaOpenACC/combined-construct-default-clause.c
A clang/test/SemaOpenACC/combined-construct-default-clause.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
Log Message:
-----------
[OpenACC] Implement 'default' clause for Combined Constructs
This clause takes one of two fixed values, and can apply to all three of
the combined constructs. Tests/etc are all exactly like the compute
constructs, so committing them all here.
Commit: d84d0caf28902843e0aae7ac435daed9aa04e3e2
https://github.com/llvm/llvm-project/commit/d84d0caf28902843e0aae7ac435daed9aa04e3e2
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90
M flang/test/Transforms/omp-map-info-finalization.fir
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
A offload/test/Inputs/target-use-dev-ptr.c
A offload/test/offloading/fortran/target-use-dev-ptr.f90
Log Message:
-----------
[Flang][OpenMP] Update MapInfoFinalization to use BlockArgs Interface and modify use_device_ptr/addr to be order independent (#113919)
This patch primarily updates the MapInfoFinalization pass to utilise the
BlockArgument interface. It also shuffles newly added arguments the
MapInfoFinalization passes to the end of the BlockArg/Relevant MapInfo
lists, instead of one prior to the owning descriptor type.
During this it was noted that the use_device_ptr/addr handling of target
data was a little bit too order dependent so I've attempted to make it
less so, as we cannot depend on argument ordering to be the same as
Fortran for any future frontends.
Commit: 4cdfa2a2c80d59db10d1a17e4ff0ec9902952759
https://github.com/llvm/llvm-project/commit/4cdfa2a2c80d59db10d1a17e4ff0ec9902952759
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
Log Message:
-----------
[OpenACC] Fix test that didn't actually test the clause it claimed to
Apparently a copy/paste issue, we were testing private instead of
firstprivate for oen of the tests.
Commit: 4610e5c78647983f79d1bd5264afff254774e13e
https://github.com/llvm/llvm-project/commit/4610e5c78647983f79d1bd5264afff254774e13e
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
M clang/test/Analysis/store-dump-orders.cpp
Log Message:
-----------
[analyzer] Don't copy field-by-field conjured LazyCompoundVals (2/4) (#115917)
Split from #114835
Commit: f71cb9dbb739bb58ce7e52e49fe384ff2ff11687
https://github.com/llvm/llvm-project/commit/f71cb9dbb739bb58ce7e52e49fe384ff2ff11687
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
M llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
M llvm/lib/Target/PowerPC/PPCCCState.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoopsVerify.cpp
M llvm/lib/Target/PowerPC/PPCCallingConv.cpp
M llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
M llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/PowerPC/PPCGenScalarMASSEntries.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetObjectFile.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
Log Message:
-----------
[PowerPC] Remove unused includes (NFC) (#116163)
Identified with misc-include-cleaner.
Commit: a8a1e9033a902d961ad050a139b97ac0319b9e25
https://github.com/llvm/llvm-project/commit/a8a1e9033a902d961ad050a139b97ac0319b9e25
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/utils/TableGen/ASTTableGen.cpp
M clang/utils/TableGen/ClangASTPropertiesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
M clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
M clang/utils/TableGen/ClangSACheckersEmitter.cpp
M clang/utils/TableGen/ClangTypeNodesEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
Log Message:
-----------
[TableGen] Remove unused includes (NFC) (#116168)
Identified with misc-include-cleaner.
Commit: 6fb7cdff3d90c565b87a253ff7dbd36319879111
https://github.com/llvm/llvm-project/commit/6fb7cdff3d90c565b87a253ff7dbd36319879111
Author: Daniel Zabawa <daniel.zabawa at intel.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
A llvm/test/CodeGen/X86/pr114265.mir
Log Message:
-----------
[X86] Recognize POP/ADD/SUB modifying rsp in getSPAdjust. (#114265)
This code assumed only PUSHes would appear in call sequences. However,
if calls require frame-pointer/base-pointer spills, only the PUSH
operations inserted by spillFPBP will be recognized, and the adjustments
to frame object offsets in prologepilog will be incorrect.
This change correctly reports the SP adjustment for POP and ADD/SUB to
rsp, and an assertion for unrecognized instructions that modify rsp.
Commit: 76bb9633a77965cbfce9c3a8985d9a59cf420877
https://github.com/llvm/llvm-project/commit/76bb9633a77965cbfce9c3a8985d9a59cf420877
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
M clang/test/Frontend/noderef.cpp
Log Message:
-----------
No longer assert when using noderef on an _Atomic type (#116237)
When filling out the type locations for a declarator, we handled atomic
types and we handled noderef types, but we didn't handle atomic noderef
types.
Fixes #116124
Commit: 44b33f5d3b7ec1f29235acee34938d52bb987619
https://github.com/llvm/llvm-project/commit/44b33f5d3b7ec1f29235acee34938d52bb987619
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/test/CodeGen/ifunc-win.c
Log Message:
-----------
Filter test based on backend support. (#116244)
ifunc support for Windows on AArch64 needs AArch64 support in the
backend so restrict the test to it's availability.
Commit: 03730cdd3d10c5270fe436777a37d50b0838a3bf
https://github.com/llvm/llvm-project/commit/03730cdd3d10c5270fe436777a37d50b0838a3bf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M clang/test/Driver/amdgpu-hip-system-arch.c
M clang/test/Driver/amdgpu-openmp-system-arch-fail.c
M clang/test/Driver/nvptx-cuda-system-arch.c
M clang/test/Driver/openmp-system-arch.c
Log Message:
-----------
clang: Remove requires system-linux from some driver tests (#111976)
Works for me on macos.
Commit: 3a20a5f5108dc43f8a831013ef6a69fd484cf4d4
https://github.com/llvm/llvm-project/commit/3a20a5f5108dc43f8a831013ef6a69fd484cf4d4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M offload/cmake/caches/Offload.cmake
Log Message:
-----------
[Offload] Move compiler-rt to runtimes in cache
Commit: 8ed3b05582e504c545fbadcc384f474220e42d3f
https://github.com/llvm/llvm-project/commit/8ed3b05582e504c545fbadcc384f474220e42d3f
Author: Joe Nash <joseph.nash at amd.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
Log Message:
-----------
[AMDGPU][True16][MC] Implement V_CVT_PK_F32_FP8/BF8 (#116106)
Existing Fake16 versions of these instructions do not support op_sel on
the _e32 encoding, which leaves a hole in the disassembler support.
Implement the true16 version of the instructions in the MC layer.
Commit: 310351d94d7abab5d29e4171aca9dc61a97209cc
https://github.com/llvm/llvm-project/commit/310351d94d7abab5d29e4171aca9dc61a97209cc
Author: cmtice <cmtice at google.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/Target/Target.h
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
Log Message:
-----------
[LLDB] Add framework for Data Inspection Language (DIL) work. (#115666)
Add the framework code for hooking up and calling the Data Inspection
Language (DIL) implementation, as an alternate implementation for the
'frame variable' command. For now, this is an opt-in option, via a
target setting 'target.experimental.use-DIL'. See
https://discourse.llvm.org/t/rfc-data-inspection-language/69893 for more
information about this project.
This PR does not actually call any of the DIL code; instead the piece
that will eventually call the DIL code
(StackFrame::DILEvaluateVariableExpression) calls back into the original
'frame variable' implementation.
Commit: 6203a6781ff8e5977d42dec36136556567c3e014
https://github.com/llvm/llvm-project/commit/6203a6781ff8e5977d42dec36136556567c3e014
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-11-14 (Thu, 14 Nov 2024)
Changed paths:
A .ci/generate_test_report.py
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
A .ci/requirements.txt
M .github/new-prs-labeler.yml
M bolt/include/bolt/Core/Exceptions.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Profile/YAMLProfileWriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/veneer-lld-abs.s
M bolt/unittests/Core/MCPlusBuilder.cpp
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
M clang/Maintainers.rst
M clang/docs/InternalsManual.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
A clang/docs/WarningSuppressionMappings.rst
M clang/docs/index.rst
M clang/include/clang/APINotes/Types.h
M clang/include/clang/AST/ASTImporter.h
M clang/include/clang/AST/ASTStructuralEquivalence.h
M clang/include/clang/AST/CommentCommands.td
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/Cuda.h
M clang/include/clang/Basic/Diagnostic.h
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticOptions.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_mve.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Sema/Sema.h
M clang/lib/APINotes/APINotesFormat.h
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/APINotes/APINotesTypes.cpp
M clang/lib/APINotes/APINotesWriter.cpp
M clang/lib/APINotes/APINotesYAMLCompiler.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/ByteCode/Source.cpp
M clang/lib/AST/ByteCode/Source.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Cuda.cpp
M clang/lib/Basic/Diagnostic.cpp
M clang/lib/Basic/DiagnosticIDs.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxbf16transposeintrin.h
A clang/lib/Headers/amxcomplextransposeintrin.h
M clang/lib/Headers/amxfp16intrin.h
A clang/lib/Headers/amxfp16transposeintrin.h
M clang/lib/Headers/amxintrin.h
M clang/lib/Headers/immintrin.h
A clang/lib/Headers/movrsintrin.h
M clang/lib/Interpreter/CodeCompletion.cpp
M clang/lib/Sema/SemaAPINotes.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes
M clang/test/APINotes/Inputs/Headers/SwiftImportAs.h
M clang/test/APINotes/swift-import-as.cpp
M clang/test/AST/ByteCode/builtin-bit-cast.cpp
M clang/test/AST/ast-dump-comment.cpp
A clang/test/AST/ast-print-openacc-combined-construct.cpp
A clang/test/AST/attr-lifetime-capture-by.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
M clang/test/Analysis/ctor-trivial-copy.cpp
A clang/test/Analysis/store-dump-orders.cpp
M clang/test/CodeGen/AArch64/fmv-dependencies.c
M clang/test/CodeGen/AArch64/fmv-streaming.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/CodeGen/SystemZ/zvector.c
M clang/test/CodeGen/SystemZ/zvector2.c
M clang/test/CodeGen/X86/amx_transpose.c
M clang/test/CodeGen/X86/amx_transpose_api.c
M clang/test/CodeGen/X86/amx_transpose_errors.c
M clang/test/CodeGen/X86/math-builtins.c
A clang/test/CodeGen/X86/movrs-builtins.c
M clang/test/CodeGen/arm-mve-intrinsics/ternary.c
M clang/test/CodeGen/attr-ifunc.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/constrained-math-builtins.c
A clang/test/CodeGen/ifunc-win.c
M clang/test/CodeGen/ifunc.c
M clang/test/CodeGen/libcalls.c
M clang/test/CodeGen/math-libcalls.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/builtin-calling-conv.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
M clang/test/CodeGenOpenCL/amdgpu-features.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9-4-generic-err.cl
M clang/test/CodeGenOpenCL/builtins-f16.cl
A clang/test/Driver/Inputs/cpunative/cortex-a57
A clang/test/Driver/Inputs/cpunative/cortex-a72
A clang/test/Driver/Inputs/cpunative/cortex-a76
A clang/test/Driver/Inputs/cpunative/neoverse-n1
A clang/test/Driver/Inputs/cpunative/neoverse-v2
M clang/test/Driver/aarch64-implied-sme-features.c
M clang/test/Driver/aarch64-implied-sve-features.c
A clang/test/Driver/aarch64-mcpu-native.c
M clang/test/Driver/amdgpu-hip-system-arch.c
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/amdgpu-openmp-system-arch-fail.c
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/nvptx-cuda-system-arch.c
M clang/test/Driver/openmp-system-arch.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Driver/ps5-linker.c
M clang/test/Frontend/noderef.cpp
A clang/test/Misc/Inputs/suppression-mapping.txt
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Misc/warning-suppression-mappings-pragmas.cpp
A clang/test/Misc/warning-suppression-mappings.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
A clang/test/SemaCXX/attr-lifetime-capture-by.cpp
M clang/test/SemaCXX/builtin-bit-cast.cpp
M clang/test/SemaCXX/constexpr-builtin-bit-cast.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp
A clang/test/SemaOpenACC/combined-construct-auto_seq_independent-ast.cpp
A clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
A clang/test/SemaOpenACC/combined-construct-default-ast.cpp
A clang/test/SemaOpenACC/combined-construct-default-clause.c
A clang/test/SemaOpenACC/combined-construct-default-clause.cpp
A clang/test/SemaOpenACC/combined-construct-device_type-ast.cpp
A clang/test/SemaOpenACC/combined-construct-device_type-clause.c
A clang/test/SemaOpenACC/combined-construct-device_type-clause.cpp
A clang/test/SemaOpenACC/combined-construct-if-ast.cpp
A clang/test/SemaOpenACC/combined-construct-if-clause.c
A clang/test/SemaOpenACC/combined-construct-if-clause.cpp
A clang/test/SemaOpenACC/combined-construct-self-ast.cpp
A clang/test/SemaOpenACC/combined-construct-self-clause.c
A clang/test/SemaOpenACC/combined-construct-self-clause.cpp
M clang/test/SemaOpenACC/combined-construct.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-num_gangs-clause.cpp
M clang/test/SemaOpenACC/loop-construct.cpp
M clang/test/lit.cfg.py
M clang/tools/driver/cc1gen_reproducer_main.cpp
M clang/tools/driver/driver.cpp
M clang/unittests/AST/StructuralEquivalenceTest.cpp
M clang/unittests/Basic/DiagnosticTest.cpp
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M clang/utils/TableGen/ASTTableGen.cpp
M clang/utils/TableGen/ClangASTPropertiesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
M clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
M clang/utils/TableGen/ClangOptionDocEmitter.cpp
M clang/utils/TableGen/ClangSACheckersEmitter.cpp
M clang/utils/TableGen/ClangSyntaxEmitter.cpp
M clang/utils/TableGen/ClangTypeNodesEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M compiler-rt/lib/asan/asan_descriptions.cpp
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/windows.inc
M compiler-rt/lib/builtins/cpu_model/cpu_model.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree-visitor.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/CUF/CUFOps.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/executable-parsers.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/unparse-with-symbols.cpp
M flang/module/ieee_arithmetic.f90
M flang/runtime/Float128Math/CMakeLists.txt
M flang/runtime/Float128Math/math-entries.h
A flang/runtime/Float128Math/remainder.cpp
M flang/test/Driver/target-cpu-features.f90
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Fir/CUDA/cuda-data-transfer.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/target-rewrite-complex16.fir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/HLFIR/select-rank.f90
A flang/test/Lower/Intrinsics/ieee_rem.f90
A flang/test/Lower/OpenMP/Todo/omp-declare-mapper.f90
M flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/use-device-ptr-to-use-device-addr.f90
M flang/test/Lower/attributes.f90
A flang/test/Parser/OpenMP/declare-mapper-unparse.f90
M flang/test/Parser/cuf-sanity-common
A flang/test/Semantics/OpenMP/declare-mapper-symbols.f90
A flang/test/Semantics/OpenMP/declare-mapper01.f90
A flang/test/Semantics/OpenMP/declare-mapper02.f90
A flang/test/Semantics/OpenMP/declare-mapper03.f90
M flang/test/Transforms/omp-map-info-finalization.fir
M libc/CMakeLists.txt
M libc/config/baremetal/arm/headers.txt
M libc/config/baremetal/riscv/headers.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/docs/talks.rst
M libc/include/llvm-libc-types/stdfix-types.h
M libc/src/__support/CMakeLists.txt
M libc/src/__support/HashTable/generic/bitmask_impl.inc
R libc/src/__support/endian.h
A libc/src/__support/endian_internal.h
M libc/src/__support/high_precision_decimal.h
M libc/src/network/htonl.cpp
M libc/src/network/htons.cpp
M libc/src/network/ntohl.cpp
M libc/src/network/ntohs.cpp
M libc/src/string/memory_utils/op_generic.h
M libc/src/string/memory_utils/utils.h
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/FPUtil/fpbits_test.cpp
A libc/test/src/__support/endian_internal_test.cpp
R libc/test/src/__support/endian_test.cpp
M libc/test/src/math/smoke/CanonicalizeTest.h
M libc/test/src/network/htonl_test.cpp
M libc/test/src/network/htons_test.cpp
M libc/test/src/network/ntohl_test.cpp
M libc/test/src/network/ntohs_test.cpp
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
M libclc/cmake/modules/AddLibclc.cmake
M libcxx/CMakeLists.txt
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/copy.h
M libcxx/include/__algorithm/copy_move_common.h
M libcxx/include/__algorithm/find_end.h
M libcxx/include/__algorithm/ranges_copy.h
M libcxx/include/__algorithm/ranges_copy_n.h
M libcxx/include/__algorithm/ranges_set_difference.h
M libcxx/include/__algorithm/ranges_set_symmetric_difference.h
M libcxx/include/__algorithm/ranges_set_union.h
M libcxx/include/__algorithm/set_difference.h
M libcxx/include/__algorithm/set_symmetric_difference.h
M libcxx/include/__algorithm/set_union.h
M libcxx/include/__locale
A libcxx/include/__memory/shared_count.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__mutex/once_flag.h
M libcxx/include/__random/discard_block_engine.h
M libcxx/include/__random/linear_congruential_engine.h
M libcxx/include/__random/mersenne_twister_engine.h
M libcxx/include/__random/shuffle_order_engine.h
M libcxx/include/__random/subtract_with_carry_engine.h
M libcxx/include/__split_buffer
M libcxx/include/__type_traits/integral_constant.h
M libcxx/include/__vector/vector.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/any
M libcxx/include/deque
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/limits
M libcxx/include/list
M libcxx/include/module.modulemap
M libcxx/include/mutex
M libcxx/include/ratio
M libcxx/src/chrono.cpp
M libcxx/src/filesystem/filesystem_clock.cpp
M libcxx/src/filesystem/path.cpp
M libcxx/test/std/containers/sequences/vector/vector.modifiers/erase_iter_iter.pass.cpp
M libcxx/utils/libcxx/test/format.py
M libcxxabi/src/cxa_demangle.cpp
M lld/COFF/Config.h
M lld/COFF/Driver.cpp
M lld/COFF/LTO.cpp
M lld/COFF/Options.td
M lld/docs/ReleaseNotes.rst
A lld/test/COFF/savetemps-colon.ll
M lld/test/ELF/ppc64-local-exec-tls.s
M lldb/examples/synthetic/libcxx.py
M lldb/include/lldb/Host/posix/ConnectionFileDescriptorPosix.h
M lldb/include/lldb/Symbol/Function.h
M lldb/include/lldb/Target/Language.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/Target/Target.h
M lldb/source/Breakpoint/BreakpointResolverFileLine.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.h
M lldb/source/Plugins/Language/ObjCPlusPlus/ObjCPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/ObjCPlusPlus/ObjCPlusPlusLanguage.h
M lldb/source/Symbol/Function.cpp
M lldb/source/Target/Language.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/functionalities/data-formatter/setvaluefromcstring/main.m
M lldb/test/API/python_api/value/change_values/TestChangeValueAPI.py
M lldb/test/API/python_api/value/change_values/main.c
M lldb/test/API/source-manager/TestSourceManager.py
R lldb/test/API/source-manager/artificial_location.c
A lldb/test/API/source-manager/artificial_location.cpp
A lldb/test/API/source-manager/artificial_location.h
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/evaluate/main.cpp
M lldb/test/Shell/Minidump/Windows/find-module.test
M lldb/test/Shell/SymbolFile/NativePDB/inline_sites_live.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/LLDBUtils.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M llvm/Maintainers.md
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/HowToAddABuilder.rst
M llvm/docs/LangRef.rst
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/ADT/iterator_range.h
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/include/llvm/CGData/StableFunctionMap.h
M llvm/include/llvm/CGData/StableFunctionMapRecord.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
A llvm/include/llvm/CodeGen/GlobalMergeFunctions.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Demangle/Demangle.h
M llvm/include/llvm/Demangle/MicrosoftDemangle.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsARM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/Mangler.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/TargetParser.h
M llvm/include/llvm/Transforms/Instrumentation/MemProfiler.h
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CGData/StableFunctionMap.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CFIFixup.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/DwarfEHPrepare.cpp
M llvm/lib/CodeGen/ExpandLargeDivRem.cpp
M llvm/lib/CodeGen/ExpandLargeFpConvert.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GCEmptyBasicBlocks.cpp
M llvm/lib/CodeGen/GCMetadata.cpp
M llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
A llvm/lib/CodeGen/GlobalISel/CombinerHelperArtifacts.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
A llvm/lib/CodeGen/GlobalMergeFunctions.cpp
M llvm/lib/CodeGen/HardwareLoops.cpp
M llvm/lib/CodeGen/IfConversion.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/InterferenceCache.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
M llvm/lib/CodeGen/KCFI.cpp
M llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
M llvm/lib/CodeGen/LiveIntervalCalc.cpp
M llvm/lib/CodeGen/LiveRangeCalc.cpp
M llvm/lib/CodeGen/LiveStacks.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineFunctionSplitter.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineStableHash.cpp
M llvm/lib/CodeGen/MachineTraceMetrics.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegAllocPBQP.cpp
M llvm/lib/CodeGen/RegAllocScore.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/RegisterScavenging.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/ShadowStackGCLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/CodeGen/TargetSchedule.cpp
M llvm/lib/Demangle/MicrosoftDemangle.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/ConstantFold.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Mangler.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/DWARFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp
M llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.cpp
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.cpp
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
A llvm/lib/Target/ARM/ARMLatencyMutations.cpp
A llvm/lib/Target/ARM/ARMLatencyMutations.h
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
M llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
M llvm/lib/Target/ARM/ARMParallelDSP.cpp
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/CMakeLists.txt
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
M llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp
M llvm/lib/Target/DirectX/CMakeLists.txt
A llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
A llvm/lib/Target/DirectX/DXILFlattenArrays.h
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXPassRegistry.def
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/CMakeLists.txt
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
M llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
M llvm/lib/Target/PowerPC/PPCCCState.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoopsVerify.cpp
M llvm/lib/Target/PowerPC/PPCCallingConv.cpp
M llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
M llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/PowerPC/PPCGenScalarMASSEntries.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrFormats.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrSPE.td
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
R llvm/lib/Target/PowerPC/PPCMergeStringPool.cpp
M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
M llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetObjectFile.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
M llvm/lib/Target/X86/X86MachineFunctionInfo.h
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/extract_float.ll
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
A llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
M llvm/test/Assembler/debug-info.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
A llvm/test/CodeGen/AArch64/block-placement-optimize-branches.ll
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
A llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
M llvm/test/CodeGen/AArch64/ls64-inline-asm.ll
M llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir
M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
M llvm/test/CodeGen/AArch64/misched-bundle.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-vector-splat.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/preserve.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
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M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
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M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
M llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
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M llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
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M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
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A llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
A llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-data.ll
M llvm/test/CodeGen/DirectX/scalar-load.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
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M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
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M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-used-with-stringpool.ll
M llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll
M llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll
M llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/PowerPC/licm-remat.ll
M llvm/test/CodeGen/PowerPC/merge-private.ll
R llvm/test/CodeGen/PowerPC/merge-string-used-by-metadata.mir
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R llvm/test/CodeGen/PowerPC/mergeable-string-pool-pass-only.mir
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M llvm/test/CodeGen/PowerPC/mergeable-string-pool-tls.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll
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A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-extload-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/minmax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
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M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir
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M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll
R llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll
A llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll
M llvm/test/CodeGen/SPIRV/instructions/scalar-integer-arithmetic.ll
A llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-vs-calllowering-unwrapped.ll
A llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-vs-calllowering.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
M llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll
M llvm/test/CodeGen/Thumb2/mve-qrintr.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/conditional-tailcall.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/lwp-intrinsics.ll
A llvm/test/CodeGen/X86/movrs-builtins.ll
A llvm/test/CodeGen/X86/movrs-prefetch-builtins.ll
M llvm/test/CodeGen/X86/no-non-zero-debug-loc-prologue.ll
A llvm/test/CodeGen/X86/pr114265.mir
M llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll
M llvm/test/CodeGen/X86/rotate_vec.ll
A llvm/test/CodeGen/X86/sincos-stack-args.ll
M llvm/test/CodeGen/X86/sink-blockfreq.ll
M llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir
A llvm/test/DebugInfo/AArch64/specification.ll
A llvm/test/DebugInfo/MIR/X86/dbg-prologue-backup-loc2.mir
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
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A llvm/test/DebugInfo/X86/dbg-prolog-end-backup-loc.ll
M llvm/test/DebugInfo/X86/dbg-prolog-end.ll
M llvm/test/DebugInfo/X86/empty-line-info.ll
M llvm/test/DebugInfo/X86/loop-align-debug.ll
M llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
M llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
M llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
M llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/avx-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/avx2-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/mmx-intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/msan_i386_bts_asm.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/msan_i386intrinsics.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/msan_x86_bts_asm.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/msan_x86intrinsics.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse2-intrinsics-x86.ll
A llvm/test/Instrumentation/MemorySanitizer/i386/sse41-intrinsics-i386.ll
R llvm/test/Instrumentation/MemorySanitizer/i386/sse41-intrinsics-x86.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg-too-large.ll
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M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_call.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg_shadow.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
A llvm/test/MC/AMDGPU/gfx9_4_generic_unsupported.s
M llvm/test/MC/AMDGPU/reloc-directive.s
A llvm/test/MC/ARM/lower-upper-errors-2.s
A llvm/test/MC/ARM/lower-upper-errors.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/X86/amx-transpose-att.txt
A llvm/test/MC/Disassembler/X86/movrs.txt
A llvm/test/MC/Disassembler/X86/prefetchrst2-32.txt
A llvm/test/MC/Disassembler/X86/prefetchrst2-64.txt
M llvm/test/MC/PowerPC/ppc64-errors.s
M llvm/test/MC/X86/amx-transpose-att.s
M llvm/test/MC/X86/amx-transpose-intel.s
A llvm/test/MC/X86/movrs-att-64.s
A llvm/test/MC/X86/movrs-intel-64.s
A llvm/test/MC/X86/prefetchrst2-att-32.s
A llvm/test/MC/X86/prefetchrst2-att-64.s
A llvm/test/MC/X86/prefetchrst2-intel-32.s
A llvm/test/MC/X86/prefetchrst2-intel-64.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
A llvm/test/ThinLTO/AArch64/cgdata-merge-local.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-read.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-two-rounds.ll
A llvm/test/ThinLTO/AArch64/cgdata-merge-write.ll
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/and-fcmp.ll
A llvm/test/Transforms/InstCombine/debugloc-bswap.ll
M llvm/test/Transforms/InstCombine/div.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/or-fcmp.ll
M llvm/test/Transforms/InstCombine/or.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/rotate.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/xor-ashr.ll
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
M llvm/test/Transforms/InstSimplify/cmp-alloca-offsets.ll
A llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll
A llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
A llvm/test/Transforms/LoopVectorize/debugloc-optimize-vfuf-term.ll
A llvm/test/Transforms/LoopVectorize/remarks-reduction-inloop.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll
A llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll
M llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
M llvm/test/Transforms/VectorCombine/X86/extract-cmp.ll
M llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/load.ll
M llvm/test/Transforms/WholeProgramDevirt/devirt_single_after_filtering_unreachable_function.ll
M llvm/test/tools/llvm-cgdata/merge-combined-funcmap-hashtree.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-archive.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-concat.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-double.test
M llvm/test/tools/llvm-cgdata/merge-funcmap-single.test
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/tools/llvm-cgdata/Opts.td
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
M llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/Analysis/PhiValuesTest.cpp
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
M llvm/unittests/CGData/StableFunctionMapTest.cpp
M llvm/unittests/IR/DebugTypeODRUniquingTest.cpp
M llvm/unittests/IR/ManglerTest.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
M llvm/unittests/Support/YAMLIOTest.cpp
A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
M llvm/unittests/Target/AArch64/CMakeLists.txt
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SeedCollectorTest.cpp
M llvm/utils/TableGen/AsmWriterEmitter.cpp
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGen/GlobalISel/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/main.py
A llvm/utils/lit/tests/xunit-output-report-failures-only.py
M mlir/CMakeLists.txt
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/Block.h
M mlir/include/mlir/IR/CommonAttrConstraints.td
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInterfaces.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/IR/GroupOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorDescriptor.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/ConcatOpPatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorInsertExtractStridedSliceRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/IR/Block.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/dialects/affine.py
M mlir/test/Analysis/DataFlow/test-dead-code-analysis.mlir
M mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
M mlir/test/Conversion/ConvertToSPIRV/argmax-kernel.mlir
M mlir/test/Conversion/ConvertToSPIRV/gpu.mlir
M mlir/test/Conversion/GPUToSPIRV/reductions.mlir
M mlir/test/Conversion/SPIRVToLLVM/non-uniform-ops-to-llvm.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/LLVMIR/sroa-intrinsics.mlir
M mlir/test/Dialect/Linalg/generalize-tensor-pack-tile.mlir
M mlir/test/Dialect/Linalg/generalize-tensor-pack.mlir
M mlir/test/Dialect/Linalg/vectorization-scalable.mlir
M mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract-masked.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/SPIRV/IR/group-ops.mlir
M mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/Tensor/decompose-concat.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/ops.mlir
A mlir/test/Dialect/Vector/emulate-narrow-type-unsupported.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-lowering.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir
A mlir/test/Integration/Dialect/Linalg/CPU/pack-dynamic-inner-tile.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
A mlir/test/Target/LLVMIR/omptarget-data-use-dev-ordering.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/group-ops.mlir
M mlir/test/Target/SPIRV/non-uniform-ops.mlir
M mlir/test/lib/Dialect/MemRef/TestEmulateNarrowType.cpp
M mlir/test/python/dialects/affine.py
M mlir/test/python/ir/array_attributes.py
M offload/CMakeLists.txt
M offload/cmake/caches/Offload.cmake
M offload/plugins-nextgen/common/src/Utils/ELF.cpp
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/plugins-nextgen/host/dynamic_ffi/ffi.h
M offload/plugins-nextgen/host/src/rtl.cpp
A offload/test/Inputs/target-use-dev-ptr.c
A offload/test/offloading/fortran/target-use-dev-ptr.f90
M runtimes/cmake/Modules/WarningFlags.cmake
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Use --as-needed when adding libzircon
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/70828dc66256...6203a6781ff8
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