[all-commits] [llvm/llvm-project] 36c639: [RISCV] Add VTs to some multi instruction isel pat...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36c639483f26c2052c21594695d93c75e348f720
      https://github.com/llvm/llvm-project/commit/36c639483f26c2052c21594695d93c75e348f720
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-14 (Thu, 14 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Add VTs to some multi instruction isel patterns to resolve ambiguity.

See also #81192. These were found by disabling tablegen's
ForceArbitraryInstResultType.

For one of the patterns I was able to get a failure if Zfh was enabled,
but Zfbfmin was not. It appears ForceArbitraryInstResultType picks
bf16 over f16.

I think something like #116165 is a better long term fix for these
issues. I will update that to include f16/bf16.



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