[all-commits] [llvm/llvm-project] fb18dc: [𝘀𝗽𝗿] initial version

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-support-__builtin_cpu_is
  Home:   https://github.com/llvm/llvm-project
  Commit: fb18dcb1c00b60ffba2ad08ec1e3a1c87d8aa8f7
      https://github.com/llvm/llvm-project/commit/fb18dcb1c00b60ffba2ad08ec1e3a1c87d8aa8f7
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-11-14 (Thu, 14 Nov 2024)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/CodeGen/CodeGenFunction.h
    M clang/test/CodeGen/builtin-cpu-is.c
    M llvm/include/llvm/TargetParser/RISCVTargetParser.h
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/TargetParser/RISCVTargetParser.cpp
    M llvm/test/TableGen/riscv-target-def.td
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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