[all-commits] [llvm/llvm-project] c1c68b: [AArch64] Define high bits of FPR and GPR register...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c1c68baf7e0fcaef1f4ee86b527210f1391b55f6
      https://github.com/llvm/llvm-project/commit/c1c68baf7e0fcaef1f4ee86b527210f1391b55f6
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-11-14 (Thu, 14 Nov 2024)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
    M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
    M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
    M llvm/test/CodeGen/AArch64/misched-bundle.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
    M llvm/test/CodeGen/AArch64/preserve.ll
    M llvm/test/CodeGen/AArch64/strpre-str-merge.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
    A llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
    M llvm/unittests/Target/AArch64/CMakeLists.txt
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)

This is a step towards enabling subreg liveness tracking for AArch64,
which requires that registers are fully covered by their subregisters,
as covered here #109797.

There are several changes in this patch:

* AArch64RegisterInfo.td and tests: Define the high bits like B0_HI,
H0_HI, S0_HI, D0_HI, Q0_HI. Because the bits must be defined by some
register class, this added a register class which meant that we had to
update 'magic numbers' in several tests.

The use of ComposedSubRegIndex helped 'compress' the number of bits
required for the lanemask. The correctness of the masks is tested by an
explicit unit tests.

* LoadStoreOptimizer: previously 'HasDisjunctSubRegs' was only true for
register tuples, but with this change to describe the high bits, a
register like 'D0' will also have 'HasDisjunctSubRegs' set to true
(because it's fullly covered by S0 and S0_HI). The fix here is to
explicitly test if the register class is one of the known D/Q/Z tuples.



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