[all-commits] [llvm/llvm-project] 62441b: [RISCV][GISel] Add instruction selection mir test ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62441b9f30a65b2708697f06333cb8bc777cebe9
      https://github.com/llvm/llvm-project/commit/62441b9f30a65b2708697f06333cb8bc777cebe9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-11-13 (Wed, 13 Nov 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir

  Log Message:
  -----------
  [RISCV][GISel] Add instruction selection mir test for f32/f64 fp load/store. NFC

We had a regbank-select test but not an instruction selection test.



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