[all-commits] [llvm/llvm-project] d7263d: [AArch64] Use second reg class in genSubAdd2SubSub...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d7263d6d6d120a833fb45a17924117aad7412a99
      https://github.com/llvm/llvm-project/commit/d7263d6d6d120a833fb45a17924117aad7412a99
  Author: David Green <david.green at arm.com>
  Date:   2024-11-13 (Wed, 13 Nov 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir

  Log Message:
  -----------
  [AArch64] Use second reg class in genSubAdd2SubSub machine combine.

In case the first operand is a physical register with no register class, use
the second operand of the sub as the register class for the new virtual
register in genSubAdd2SubSub machine combine.



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