[all-commits] [llvm/llvm-project] 84e95b: [RISCV] Update SiFive P600's scheduling model on R...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84e95beae980466ffcc555297e0e34d23fca8a76
      https://github.com/llvm/llvm-project/commit/84e95beae980466ffcc555297e0e34d23fca8a76
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-11-12 (Tue, 12 Nov 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vmv.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbb.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvbc.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkg.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvkned.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvknhb.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zvksh.s

  Log Message:
  -----------
  [RISCV] Update SiFive P600's scheduling model on RVV instructions (#115243)

The biggest change is assigning vector crypto instructions to the
correct processor resource.

The majority of these changes are guided by our RVV-capable
llvm-exegesis.



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