[all-commits] [llvm/llvm-project] ab9178: [ARM] Add a couple of new MVE reduction tests. NFC
Michael Kruse via All-commits
all-commits at lists.llvm.org
Tue Nov 12 07:11:24 PST 2024
Branch: refs/heads/users/meinersbur/irbuilder-extract-refactor
Home: https://github.com/llvm/llvm-project
Commit: ab9178e3e73dc715463e1019ed2cd449dc18bb18
https://github.com/llvm/llvm-project/commit/ab9178e3e73dc715463e1019ed2cd449dc18bb18
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
Log Message:
-----------
[ARM] Add a couple of new MVE reduction tests. NFC
Nowadays we generate add(zext(mul(sext, sext)) with nneg zext and the multi-use
test is awkward to get right. This should help our test coverage with the vplan
cost transition.
Commit: 3c3f19ca5ea03428edacbd5d087b991c447c47dc
https://github.com/llvm/llvm-project/commit/3c3f19ca5ea03428edacbd5d087b991c447c47dc
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/IR/Intrinsics.cpp
Log Message:
-----------
Revert "[NFC][LLVM] Use namespace `Intrinsic` in `Intrinsics.cpp` (#114822)"
This reverts commit c2b61fcb3cd4ffa286b24437b7b6d66f0dee6c25.
Intrinsic namespace contains memcpy which is a naming conflict with
memcpy from string.h header.
Commit: 53e6f627d7e81633b2e159675884bfcce11bdc00
https://github.com/llvm/llvm-project/commit/53e6f627d7e81633b2e159675884bfcce11bdc00
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] _mm_movpi64_epi64 - convert to shufflevector pattern instead of bitcasting to i64
Don't bitcast a v1i64 to i64 as constant expressions will struggle to handle this - convert to a shufflevector concat pattern like _mm_move_epi64 instead
Commit: 0f040433d325aa68ec6840aa179f3f314c26153a
https://github.com/llvm/llvm-project/commit/0f040433d325aa68ec6840aa179f3f314c26153a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Update MMX intrinsic tests for both C/C++
Requires update to movmsk call to handle additional markers
Commit: 77bec78878762e34150fe23734fa43df796c873c
https://github.com/llvm/llvm-project/commit/77bec78878762e34150fe23734fa43df796c873c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
Log Message:
-----------
[SLP]Do not look for last instruction in schedule block for buildvectors
If looking for the insertion point for the node and the node is
a buildvector node, the compiler should not use scheduling info for such
nodes, they may contain only partial info, which is not fully correct
and may cause compiler crash.
Fixes #114082
Commit: f7bb12901e2955b972273a06dd028ab4b2822b44
https://github.com/llvm/llvm-project/commit/f7bb12901e2955b972273a06dd028ab4b2822b44
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/newhdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Add tanpif16 function (#115183)
- Implementation of `tan` for 16-bit floating point inputs scaled by pi.
i.e,. `tanpif16()`
- Implementation of Tanpi in MPFRWrapper for MPFR versions < 4.2
- Exhaustive tests for `tanpif16()`
Commit: 1645d99bc9c16b1f9e2f08e36d67054498d8751e
https://github.com/llvm/llvm-project/commit/1645d99bc9c16b1f9e2f08e36d67054498d8751e
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
Log Message:
-----------
[libc++][hardening] Use `static_assert` for `__(static_)bounded_iter` (#115304)
We can't `static_assert` `__libcpp_is_contiguous_iterator` for
`__wrap_iter` currently because `__wrap_iter` is also used for wrapping
user-defined fancy pointers.
Fixes #115002.
Commit: 9aea6671085f02e6127750103ca48ae6a09ceeb8
https://github.com/llvm/llvm-project/commit/9aea6671085f02e6127750103ca48ae6a09ceeb8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Log Message:
-----------
[symbolizer] Change the ErrorHandler from llvm::function_ref to std::function. (#115477)
This fixes dangling `ErrorHandler` references
([here](https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_symbolize.cpp#L48-L53)
is an example).
`llvm::function_ref` doesn't own the callable, and it is not safe to
store a function_ref (the `PlainPrinterBase` stores a
`llvm::function_ref` which can easily lead to dangling references).
Commit: 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
https://github.com/llvm/llvm-project/commit/8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
A clang/test/Sema/attr-lifetimebound.c
Log Message:
-----------
[clang] Permit lifetimebound in all language modes (#115482)
Lifetimebound annotations can help diagnose common cases of dangling
including escaping the address of a stack variable from a function. This
is useful in all C family languages, restricting these diagnostics to
C++ is an artificial limitation.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: da9499ebfb323602c42aeb674571fe89cec20ca6
https://github.com/llvm/llvm-project/commit/da9499ebfb323602c42aeb674571fe89cec20ca6
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293)
This patch introduces the amended feature flag for
[FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES),
'**sve-aes**'. The existing flag associated with this feature,
'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for
backwards compatibility.
The
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension)
documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1
when
> there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions
and if the associated ACLE intrinsics are available.
The front-end has been amended such that it is compatible with +sve2-aes
and +sve2+sve-aes.
Commit: 7844257fc2afe490ae4b923a770d20dabed5c3c6
https://github.com/llvm/llvm-project/commit/7844257fc2afe490ae4b923a770d20dabed5c3c6
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Use explicit #include instead of transitive #include (#115420)
This benchmark test currently uses `std::unique_ptr` without explicitly
`#include <memory>`. I think we should not rely on transitive inclusion.
Commit: c93eb43a63d3b5c90e828608b5c2063644a3b161
https://github.com/llvm/llvm-project/commit/c93eb43a63d3b5c90e828608b5c2063644a3b161
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/test/API/lua_api/TestFileHandle.lua
Log Message:
-----------
[lldb] Fix TestFileHandle.lua
- Explicitly create an `SBFile`.
- Add missing call to `close`.
- Use `SetErrorFile` in TestLegacyFileErr.
Commit: e734de1f5a3c2ec0c88221eb0991b0922e30d902
https://github.com/llvm/llvm-project/commit/e734de1f5a3c2ec0c88221eb0991b0922e30d902
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
R clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
Revert "[Clang][HIP] Deprecate the AMDGCN_WAVEFRONT_SIZE macros" (#115499)
Reverts llvm/llvm-project#112849 due to test failure on Mac, reported by
@nico
Commit: 6737ba40406030cd8a7ea706cd56302f8be7a4b4
https://github.com/llvm/llvm-project/commit/6737ba40406030cd8a7ea706cd56302f8be7a4b4
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Update the lifetimebound doc.
The lifetimebound attr is not C++ only anymore after 8b29c05b73310bba3d7abd007dbbd839c46b0ab4
Commit: c9552283c0bf277eba490cde9fd913510f4111c0
https://github.com/llvm/llvm-project/commit/c9552283c0bf277eba490cde9fd913510f4111c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/mmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for MMX _mm_set*_pi* intrinsics
Commit: 2407ff4645e9124507a4b5d910603ff7fc9e5734
https://github.com/llvm/llvm-project/commit/2407ff4645e9124507a4b5d910603ff7fc9e5734
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/test/CodeGen/X86/sse2-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for _mm_movpi64_epi64
Commit: 51e8f822f39174eaf83b1d5798de329518970b02
https://github.com/llvm/llvm-project/commit/51e8f822f39174eaf83b1d5798de329518970b02
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/pr62014.ll
Log Message:
-----------
[X86] pr62014.ll - regenerate test checks with vpternlog comments
Commit: 71f82bba35c48eaf98c50aeeb4d2675156681c02
https://github.com/llvm/llvm-project/commit/71f82bba35c48eaf98c50aeeb4d2675156681c02
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
Log Message:
-----------
[SPIRV] Use heterogenous lookups with std::map (NFC) (#115425)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 6ce44266fc2d06dfcbefd8146279473ccada52ca
https://github.com/llvm/llvm-project/commit/6ce44266fc2d06dfcbefd8146279473ccada52ca
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/lib/IR/Dialect.cpp
Log Message:
-----------
[mlir] Use heterogenous lookups with std::map (NFC) (#115426)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: a4819d6aa30f849770c258abba67a4b721642ebf
https://github.com/llvm/llvm-project/commit/a4819d6aa30f849770c258abba67a4b721642ebf
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/IR/MLIRContext.cpp
Log Message:
-----------
[mlir] Simplify code with StringMap::operator[] (NFC) (#115427)
Commit: bc7e5c2016e287b768d2a3a1de15f6bb644622ae
https://github.com/llvm/llvm-project/commit/bc7e5c2016e287b768d2a3a1de15f6bb644622ae
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Avoid repeated hash lookups (NFC) (#115428)
Commit: 2f243a5fb754c3688dfa225ce8073a281bca1a24
https://github.com/llvm/llvm-project/commit/2f243a5fb754c3688dfa225ce8073a281bca1a24
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for 0e39b1348e5fcadb129a6f113e5d708a526d8faa
Commit: 3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
https://github.com/llvm/llvm-project/commit/3356eb3b15f391b9b4f62b0157fede16bd8cd5b3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
Log Message:
-----------
[llvm-reduce] Reduce samesign flag from icmp (#115492)
Commit: 92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
https://github.com/llvm/llvm-project/commit/92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
Log Message:
-----------
[AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)
We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]`
from
`fma extract(Rn, lane), Rm, Ra -> fmla`
But for the case of lane==0, we want to prefer the simple `fmadd s0, s1,
s2`. So we have patterns for
`fma extract(Rn, 0), Rm, Ra -> fmadd`
The problem arises when we have two extracts, as tablegen starts to
prefer the second pattern, as it looks more specialized. This patch adds
additional patterns to catch this case:
`fma extract(Rn, index), extract(Rm, 0), Ra -> fmla`
To make sure the simpler fmadd keeps being selected when both lanes are
extracted from lane 0 we need to add patterns for that case too:
`fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`
Commit: 4027400d2ceefb5ce68d4508e5f30dc40c4f535b
https://github.com/llvm/llvm-project/commit/4027400d2ceefb5ce68d4508e5f30dc40c4f535b
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
A clang/test/C/C2y/n3342.c
M clang/test/Misc/warning-flags.c
M clang/test/Sema/declspec.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3342 (#115494)
This paper made qualified function types implementation-defined. We have
always supported this as an extension, so now we're documenting our
behavior.
Note, we still warn about this by default even in C2y mode because a
qualified function type is a sign of programmer confusion.
Commit: f756d38abf2ec40ee06ee5aa668db444e5d6f485
https://github.com/llvm/llvm-project/commit/f756d38abf2ec40ee06ee5aa668db444e5d6f485
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3342.c
Log Message:
-----------
Fix failing test bot
Fixes the issue found by:
https://lab.llvm.org/buildbot/#/builders/144/builds/11191
Commit: e5e15f9128b69f77668465b715b7984b8d5ad75a
https://github.com/llvm/llvm-project/commit/e5e15f9128b69f77668465b715b7984b8d5ad75a
Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
add QuietMisdreavus to Clang/ExtractAPI code owners (#115206)
Adding myself to the ExtractAPI code owners listing so i can participate
in code reviews.
Commit: 19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
https://github.com/llvm/llvm-project/commit/19f657d55d679cc3949e9e4c1a5bf76cc4c031b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/vector-sext.ll
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use broadcast on AVX2+ targets
Make use of AVX2 broadcasts to splat the source integer across all lanes to simplify the per-lane byte shuffles.
Prep work to avoid a regression in the fix for #66150
Commit: 79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
https://github.com/llvm/llvm-project/commit/79c7b7ee9f8b1cec13d9c1026e2bae9b9e91bc6f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineToExtendBoolVectorInReg - use SelectionDAG::getSplat helper instead of shuffle(scalar_to_vector(x))
Commit: 92e0fb0c944254312d7b9c6ca64a026643617f60
https://github.com/llvm/llvm-project/commit/92e0fb0c944254312d7b9c6ca64a026643617f60
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
Log Message:
-----------
[DebugInfo][LoopUnroll] Preserve DebugLocs on optimized cond branches (#114225)
This patch fixes a simple error where as part of loop unrolling we
optimize conditional loop-exiting branches into unconditional branches
when we know that they will or won't exit the loop, but does not
propagate the source location of the original branch to the new one.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: bde3d4a62e714f179c6e859758582d5ef9efa5f8
https://github.com/llvm/llvm-project/commit/bde3d4a62e714f179c6e859758582d5ef9efa5f8
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
Log Message:
-----------
[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)
Fixes 2 old TODOs
Commit: b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
https://github.com/llvm/llvm-project/commit/b535e4ecacf4d93ba9632a0e4e9f0dd616dd0472
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
Log Message:
-----------
[StructurizeCFG] Remove one SSAUpdater::AddAvailableValue. NFCI. (#115472)
Commit: 39358f846d1e336def88ff9c25581fab392d59fe
https://github.com/llvm/llvm-project/commit/39358f846d1e336def88ff9c25581fab392d59fe
Author: stefankoncarevic <skoncare at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/named-ops.mlir
Log Message:
-----------
[mlir][linalg] Add Grouped Convolution Ops: conv_2d_nhwgc_gfhwc and conv_2d_nhwgc_gfhwc_q (#108192)
This patch adds two new ops: linalg::Conv2DNhwgcGfhwcOp and
linalg::Conv2DNhwgcGfhwcQOp, and uses them to convert tosa group conv2d
Ops.
- Added linalg::Conv2DNhwgcGfhwcOp and linalg::Conv2DNhwgcGfhwcQOp.
- Updated the conversion process to use these new ops for tosa group
conv2d operations.
Commit: c3c2f46f7bd5891af13fef56a8754007f11ff6c1
https://github.com/llvm/llvm-project/commit/c3c2f46f7bd5891af13fef56a8754007f11ff6c1
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/test/C/C2y/n3346.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Claim conformance and add test coverage for WG14 N3346 (#115516)
This converts some undefined behaviors during initialization to instead
be constraint violations. Clang has always implemented these as
constraints, so no compiler changes were needed.
Commit: f7eba08497a2a46f2c10737a110f6b778faf1615
https://github.com/llvm/llvm-project/commit/f7eba08497a2a46f2c10737a110f6b778faf1615
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/ObjectYAML/ELFEmitter.cpp
Log Message:
-----------
[ObjectYAML][ELF] Fix misspelling in `Elf_Verdaux` var name (NFC)
Commit: 60972a893e2bf915f6ff043c9396dea9619456fb
https://github.com/llvm/llvm-project/commit/60972a893e2bf915f6ff043c9396dea9619456fb
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/obj2yaml/elf2yaml.cpp
Log Message:
-----------
[ObjectYAML][ELF] Allow verdaux entry offset to be user-defined
Commit: b85e5b49d3efc37e837757a5154884648dc57113
https://github.com/llvm/llvm-project/commit/b85e5b49d3efc37e837757a5154884648dc57113
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Speculatively fix test bots
This should address the issues found by:
https://lab.llvm.org/buildbot/#/builders/12/builds/9226
https://lab.llvm.org/buildbot/#/builders/140/builds/10487
https://lab.llvm.org/buildbot/#/builders/27/builds/1752
Commit: d30a6dcfa06196dd98fc898219eb12bab04a56de
https://github.com/llvm/llvm-project/commit/d30a6dcfa06196dd98fc898219eb12bab04a56de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
Log Message:
-----------
[AMDGPU] Reorganize tests to unblock #112403 (#115503)
We’re facing an issue (#113782) that is currently blocking #112403. However,
since #112403 involves extensive test changes, I’d prefer to land it as soon as
possible. This PR reorganizes the tests by moving test cases expected to fail
into a separate file. Additionally, it changes the `[15 x i32]` arguments to
`[13 x i32]` to bypass the issue.
Commit: e215a1e27d84adad2635a52393621eb4fa439dc9
https://github.com/llvm/llvm-project/commit/e215a1e27d84adad2635a52393621eb4fa439dc9
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
Commit: 4661467003e7bc7f9bb89ab581517617d2a36c62
https://github.com/llvm/llvm-project/commit/4661467003e7bc7f9bb89ab581517617d2a36c62
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
A clang/test/C/C2y/n3341.c
M clang/www/c_status.html
Log Message:
-----------
[C2y] Add test coverage and documentation for WG14 N3341 (#115478)
This paper made empty structures and unions implementation-defined. We
have always supported this as a GNU extension, so now we're documenting
our behavior and removing the extension warning in C2y mode.
Commit: b70d1302cf2edaf95817a90f161691c684945273
https://github.com/llvm/llvm-project/commit/b70d1302cf2edaf95817a90f161691c684945273
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Another speculative fix for WG14 N3346
This time it's for builders that don't default to C11 or later, such as:
https://lab.llvm.org/buildbot/#/builders/144/builds/11201
Commit: 2808f05e83643b3d5ef128340f6f4da994ed71e3
https://github.com/llvm/llvm-project/commit/2808f05e83643b3d5ef128340f6f4da994ed71e3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3341.c
Log Message:
-----------
Update test case for bots which don't default to C17
Commit: 17f3e00911b860d535f41185e605c47babcc2039
https://github.com/llvm/llvm-project/commit/17f3e00911b860d535f41185e605c47babcc2039
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
The increase in fallbacks that was previously reported were not caused
by this change.
Original description:
This matches InstCombine and DAGCombine.
RISC-V only has an ADDI instruction so without this we need additional
patterns to do the conversion.
Some of the AMDGPU tests look like possible regressions. Maybe some
patterns from isel aren't imported.
Commit: e4d57d6a729fd955ccbdd8834065356f26284f3d
https://github.com/llvm/llvm-project/commit/e4d57d6a729fd955ccbdd8834065356f26284f3d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
Log Message:
-----------
[OpenACC] Remove 'loop' link to parent construct
After implementing 'loop', we determined that the link to its parent
only ever uses the type, not the construct itself. This patch removes
it, as it is both a waste and causes problems with serialization.
Commit: e53c46a9084caac115d7f694e5f16f904b0d7124
https://github.com/llvm/llvm-project/commit/e53c46a9084caac115d7f694e5f16f904b0d7124
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
Log Message:
-----------
[Statepoint] Treat result of atomicrmw xchg as a base pointer (#97280)
Atomic RMW Xchg wasn't handled before when searching for known base
pointers in the IR.
Commit: 40740c4494d971ce410e2051b8d3ea7bbe081c76
https://github.com/llvm/llvm-project/commit/40740c4494d971ce410e2051b8d3ea7bbe081c76
Author: Siddhesh Deodhar <153800103+siddhesh195 at users.noreply.github.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
Log Message:
-----------
Fix crash when using when using --finalize-memref-to-llvm (#112433)
This patch fixes crash when attempting to convert uint to int address
space during finalize-memref-to-llvm by doing the following:
1. Add a check to verify that IntegerAttr is signed int before calling
IntegerAttr::getInt()
2. Emit error when getMemRefAddressSpace returns a failure()
Closes #111242
---------
Co-authored-by: Christian Ulmann <christianulmann at gmail.com>
Commit: 2b885f056585f82903f067840e54557a5b444b65
https://github.com/llvm/llvm-project/commit/2b885f056585f82903f067840e54557a5b444b65
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/test/C/C2y/n3346.c
Log Message:
-----------
Fix test for bots that don't default to C17
Commit: a749c98b49dc9a3863b685212d70be98b4f189c3
https://github.com/llvm/llvm-project/commit/a749c98b49dc9a3863b685212d70be98b4f189c3
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Baze] Add missing lldbDataFormatter.py back to BUILD.bazel. (#115519)
- [x] Add `utils/lldbDataFormatters.py` back.
Commit: fe5a64d1160209f22624b112b2629b0d6c4bb264
https://github.com/llvm/llvm-project/commit/fe5a64d1160209f22624b112b2629b0d6c4bb264
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
Log Message:
-----------
[fang][cuda] Allow * in call chevron syntax (#115381)
Using `*` in call chevron syntax should be allowed. This patch updates
the parser to allow this usage.
```
call sub<<<*,nbBlock>>>()
```
Commit: 86405ed1012c97b063cbde12350fdea141e1ab78
https://github.com/llvm/llvm-project/commit/86405ed1012c97b063cbde12350fdea141e1ab78
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
Log Message:
-----------
[DebugInfo][Reassociate] Preserve DebugLocs when reassociating subs (#114226)
In NegateValue in Reassociate, we return the negation of an existing
value in order to break a subtract into an negate + add, potentially
creating a new instruction to perform the negation, but we neglect to
propagate the DebugLoc of the sub being replaced to the negate
instruction if one is created. This patch adds that propagation.
Found using https://github.com/llvm/llvm-project/pull/107279.
Commit: 40e545098e8bb5a18988316331e46c4557378afa
https://github.com/llvm/llvm-project/commit/40e545098e8bb5a18988316331e46c4557378afa
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/CIRGenerator.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
Log Message:
-----------
[clang][CIR] Move CIRGen types into clang::CIRGen (#115385)
https://github.com/llvm/clangir/issues/1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.
Commit: c72389d4feef9eafc902f99c41f85ed218b5bedf
https://github.com/llvm/llvm-project/commit/c72389d4feef9eafc902f99c41f85ed218b5bedf
Author: Shoaib Meenai <smeenai at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
Log Message:
-----------
[clang][CIR] Merge the mlir::cir namespace into cir (#115386)
https://github.com/llvm/clangir/issues/1025 discusses the motivation.
The mechanical parts of this change were done via:
find clang \( -name '*.h' -o -name '*.cpp' -o -name '*.td' \) -print0 |
xargs -0 perl -pi -e 's/mlir::cir/cir/g'
find clang \( -name '*.h' -o -name '*.cpp' \) -print0 | xargs -0 perl
-pi -e 's/::cir/cir/g'
There were some manual fixups and a clang-format run afterwards.
Commit: 0dbdb3251fe1f276785015c1de3b0a1035c9de8f
https://github.com/llvm/llvm-project/commit/0dbdb3251fe1f276785015c1de3b0a1035c9de8f
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Remove mlir-spirv-cpu-runner after 0e39b1348e5fcadb129a6f113e… (#115533)
…5d708a526d8faa
Commit: e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
https://github.com/llvm/llvm-project/commit/e5796321cee0f6b3c2fbf33813d6b3af1ddd8f18
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/AST/Decl.cpp
Log Message:
-----------
[clang] Avoid unnecessary call to clang::NamespaceDecl::isRedundantInlineQualifierFor(). (#115196)
We observed 2X slowdown in lldb's expression evaluation with
https://github.com/llvm/llvm-project/pull/109147 in some cases. It turns
out that calling `isRedundantInlineQualifierFor` is quite expensive.
Using short-circuit evaluation in the if statement to avoid unnecessary
calls to that function.
Commit: 5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
https://github.com/llvm/llvm-project/commit/5005f8d2486d6eec7b2b8ae04f49e8a87ebf4bf6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
Log Message:
-----------
[RISCV] Add sub_to_add to RISCVPostLegalizerCombiner.
Commit: e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
https://github.com/llvm/llvm-project/commit/e8ce76f1a67e99e2eba54a3c8a85a0fd214e3606
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
Log Message:
-----------
[GlobalISel][AArch64] Allow vector ptr to int unmerges (#115228)
Vector pointer -> scalar integer unmerges are already legal. This
loosens the verifier check for vector-of-pointers -> vectors.
Commit: a29e623e1257b100b507c592a405fee2e0ff34b9
https://github.com/llvm/llvm-project/commit/a29e623e1257b100b507c592a405fee2e0ff34b9
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
Log Message:
-----------
[compiler-rt] Make add_custom_libcxx() resilient to DESTDIR being set
If DESTDIR is set in the environment during the build/test stage, the
local libc++ installation will be installed under DESTDIR instead of being
in the build directory.
See https://github.com/llvm/llvm-project/pull/115077#issuecomment-2464640457
and https://gitlab.kitware.com/cmake/cmake/-/issues/18165.
Pull Request: https://github.com/llvm/llvm-project/pull/115525
Commit: bbcd35270ef4597402b924d547d845893e7fd165
https://github.com/llvm/llvm-project/commit/bbcd35270ef4597402b924d547d845893e7fd165
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/CodeGen/aarch64-fmv-dependencies.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesimc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64FMV.td
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
M llvm/test/MC/AArch64/SVE2/aesd.s
M llvm/test/MC/AArch64/SVE2/aese.s
M llvm/test/MC/AArch64/SVE2/aesimc.s
M llvm/test/MC/AArch64/SVE2/aesmc.s
M llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
M llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
M llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
M llvm/test/MC/AArch64/SVE2/directive-cpu.s
M llvm/test/MC/AArch64/SVE2/pmullb-128.s
M llvm/test/MC/AArch64/SVE2/pmullt-128.s
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (#115539)
…293)"
This reverts commit da9499ebfb323602c42aeb674571fe89cec20ca6.
Commit: 6fb36f0bd0a34e6429960247cf088557ae7a6e96
https://github.com/llvm/llvm-project/commit/6fb36f0bd0a34e6429960247cf088557ae7a6e96
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
Log Message:
-----------
[flang][OpenMP] Remove std::variant with single alternative, NFC
Commit: 7dffc96a54f90569d6226dd5713c80fc8f30c76f
https://github.com/llvm/llvm-project/commit/7dffc96a54f90569d6226dd5713c80fc8f30c76f
Author: vporpo <vporpodas at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
Log Message:
-----------
[SandboxVec][BottomUpVec] Clean up dead instructions (#115267)
When scalars get replaced by vectors the original scalars may become
dead. In that case erase them.
Commit: 144bdf3eb7128518ed162c5a168e3ec90922cd9e
https://github.com/llvm/llvm-project/commit/144bdf3eb7128518ed162c5a168e3ec90922cd9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
Log Message:
-----------
[VPlan] Also check if plan for best legacy VF contains simplifications.
The plan for the VF chosen by the legacy cost model could also contain
additional simplifications that cause cost differences. Also check if it
contains simplifications.
Fixes https://github.com/llvm/llvm-project/issues/114860.
Commit: db6f476e8e29c42691a3c3ea97d7230af2be5df8
https://github.com/llvm/llvm-project/commit/db6f476e8e29c42691a3c3ea97d7230af2be5df8
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
Log Message:
-----------
AMDGPU: Use "countMaxActiveBits() <= 5" to define uint5Bits (#115543)
countMaxTrailingOnes() is not correct. This patch follows the suggestion
from https://github.com/llvm/llvm-project/pull/115372.
Commit: 30ee3f4ec767f2f183d74eb949afa80b8b6261e2
https://github.com/llvm/llvm-project/commit/30ee3f4ec767f2f183d74eb949afa80b8b6261e2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
Log Message:
-----------
AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)
Commit: 552f6fe4d503900cae7620f2ddfd7393be670d27
https://github.com/llvm/llvm-project/commit/552f6fe4d503900cae7620f2ddfd7393be670d27
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
Log Message:
-----------
[RISCV] Custom promote s32 G_UDIV/UREM/SDIV on RV64. Promote SREM using G_SEXT. (#115402)
We don't add a custom node for REMW as we can detect it with (srem
(sexti32), (sexti32)).
Commit: dbad9412909a1879f29a4f717b2bf149c9a58369
https://github.com/llvm/llvm-project/commit/dbad9412909a1879f29a4f717b2bf149c9a58369
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Basic/Attributes.cpp
Log Message:
-----------
[NFC][Clang] Use StringSwitch instead of array for parsing attribute scope (#115414)
Commit: b99d4112585302cbd01f9b851a04adc6e4fb5218
https://github.com/llvm/llvm-project/commit/b99d4112585302cbd01f9b851a04adc6e4fb5218
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Refactoring breakpoints to not use the `g_dap` reference. (#115208)
Refactoring breakpoints to not use the `g_dap` reference.
Instead, when a breakpoint is constructed it will be passed a DAP
reference that it should use for its lifetime.
This is part of a larger refactor to remove the global `g_dap` variable
to allow us to create multiple DAP instances.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: ca33649abe5fad93c57afef54e43ed9b3249cd86
https://github.com/llvm/llvm-project/commit/ca33649abe5fad93c57afef54e43ed9b3249cd86
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
R llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
Commit: ccc9d7dc7af535aa240a96bc999911ee9ba2d534
https://github.com/llvm/llvm-project/commit/ccc9d7dc7af535aa240a96bc999911ee9ba2d534
Author: David Green <david.green at arm.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Update and extend ptradd.ll test. NFC
We can now support v4p0 pointers without running into verifier issues.
Commit: 441b82b20bf3a622155354e17ae66e0ccff50796
https://github.com/llvm/llvm-project/commit/441b82b20bf3a622155354e17ae66e0ccff50796
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/test/Dialect/Vector/int-range-interface.mlir
Log Message:
-----------
[mlir][NFC] IntegerRangeAnalysis: don't loop over splat attr (#115399)
Reland https://github.com/llvm/llvm-project/pull/115229 which was
reverted by https://github.com/llvm/llvm-project/pull/115388 because it
was hitting an assertion in IREE. From the original change: If the
`DenseIntElementsAttr` is a splat value, there is no need to loop over
the entire attr. Instead, just update with the splat value.
The problem with the original implementation is that `SplatElementsAttr`
might be an attr of non `APInt` (e.g. float) elements. Instead, check if
`DenseIntElementsAttr` is splat and use the splat value. Added a test to
ensure there's no crash when handling float attrs.
Commit: 8a7a7b5ffc690bd012cf090d31d47ec938248ba3
https://github.com/llvm/llvm-project/commit/8a7a7b5ffc690bd012cf090d31d47ec938248ba3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Remove unneeded code connecting blocks in VPBB:splitAt (NFC).
insertBlockAfter already takes care of transferring successors. Remove
unneeded code to transfer them manually.
Commit: 26a9f3f5906c62cff7f2245b98affa432b504a87
https://github.com/llvm/llvm-project/commit/26a9f3f5906c62cff7f2245b98affa432b504a87
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Cleanup getSameOpcode, return InstructionsState::invalid() for non-valid inputs
Just a cleanup and related changes
Commit: 8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
https://github.com/llvm/llvm-project/commit/8d8d9f0ece2337d0ce34f464f0ce3d5193460ca4
Author: John Harrison <harjohn at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/JSONUtils.cpp
Log Message:
-----------
[lldb-dap] Fix lldb-dap build for windows, missing PATH_MAX. (#115551)
This should fix https://lab.llvm.org/buildbot/#/builders/141/builds/3722
Commit: 7a6a52a2f0c6af63f210562d4a0345232d30d54d
https://github.com/llvm/llvm-project/commit/7a6a52a2f0c6af63f210562d4a0345232d30d54d
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/SandboxIR/Instruction.cpp
Log Message:
-----------
[SandboxIR] Remove incorrect assertion. (#115553)
`insertBefore` can be called on a detached instruction, and we can't
check that the underlying instructions are ordered because instructions
without BB parents have no order.
This problem showed up as a different assertion failure in
`llvm::Instruction::comesBefore` in one of the unit tests when
`EXPENSIVE_CHECKS` are enabled.
Commit: fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
https://github.com/llvm/llvm-project/commit/fef4c8a43ac2dbec7921de7963a7bc3fde4f90f6
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
Log Message:
-----------
[AMDGPU] Disable verifier in `call-args-inreg-no-sgpr-for-csrspill-xfail.ll`
Similar to f9bd083, this could fix expensive check failure.
Commit: d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
https://github.com/llvm/llvm-project/commit/d4eb430c9e4abe0aa1d98915ec4529cc9be9b36b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
Log Message:
-----------
[flang][cuda] Support derived type in cuf.alloc (#115550)
Number of bytes to allocate was not computed when using `cuf.alloc` with
a derived type. Update the conversion to compute the number of bytes and
emit an error when type is not supported.
Commit: 023483f5ba6bbbec64bb340578b00bfa3399691d
https://github.com/llvm/llvm-project/commit/023483f5ba6bbbec64bb340578b00bfa3399691d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
Log Message:
-----------
[flang][cuda][NFC] Add test for <<<*, block>>> lowering (#115534)
Chevron syntax has been update to allow `*` to be used for the grid
value. Make sure we set the three grid values to -1, 1, 1 in lowering.
Commit: 6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
https://github.com/llvm/llvm-project/commit/6b21cf8ccad84e2670e458d8bdaccbd0ae37b46b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M flang/runtime/CUDA/kernel.cpp
Log Message:
-----------
[flang][cuda] Compute grid x when calling a kernel with <<<*, block>>> (#115538)
`-1, 1, 1` is passed when calling a kernel with the `<<<*, block>>>`
syntax. Query the device to compute the grid.x value.
Commit: 50850bc78b00b991cb361cb94a151befd83f6a5d
https://github.com/llvm/llvm-project/commit/50850bc78b00b991cb361cb94a151befd83f6a5d
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[LV] Add test for preserving flags when widening casts; NFC
Commit: 8af5ae0648f85b9196a794700ebe5468a0cefd6b
https://github.com/llvm/llvm-project/commit/8af5ae0648f85b9196a794700ebe5468a0cefd6b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
Log Message:
-----------
[VPlan] Preserve IR flags when widening casts
We have `nneg` for both `sext` and `uitofp`.
Fixes #114856
Closes #115373
Commit: 738250989ce516f02f809bdfde474a039c77e81f
https://github.com/llvm/llvm-project/commit/738250989ce516f02f809bdfde474a039c77e81f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
Log Message:
-----------
[Clang][perf-training] Do build of libLLVMSupport for perf training (#111625)
This adds a build of the libLLVMSupport to the lit suite that is used
for generating profile data. This helps to improve both PGO and BOLT
optimization of clang over the existing hello world training program.
I considered building all of LLVM instead of just libLLVMSupport, but
there is only a marginal increase in performance for PGO only builds
when training with a build of all of LLVM, and I didn't think it was
enough to justify the increased build times given that it is the default
configuration.
The benchmark[1] I did showed that using libLLVMSupport for training
gives a 1.35 +- 0.02 speed up for clang optimized with PGO + BOLT vs
just 1.05 +- 0.01 speed up when training with hello world.
For comparison, training with a full LLVM build gave a speed up of 1.35
+- 0.1.
Raw data:
| PGO Training | BOLT Training | Speed Up | Error Range |
| ------------ | ------------- | -------- | ----------- |
| LLVM Support | LLVM Support | 1.35 | 0.02 |
| LLVM All | LLVM All | 1.34 | 0.01 |
| LLVM Support | Hello World | 1.29 | 0.02 |
| LLVM All | PGO-ONLY | 1.27 | 0.02 |
| LLVM Support | PGO-ONLY | 1.22 | 0.02 |
| Hello World | Hello World | 1.05 | 0.01 |
| Hello World | PGO-ONLY | 1.03 | 0.01 |
Time it takes to generate profile data (on a 64-core system):
| Training Data | PGO | BOLT |
| ------------- | ----- | ----- |
| LLVM All | 1090s | 3239s |
| LLVM Support | 91s | 655s |
| Hello World | 2s | 9s |
[1] Benchmark was compiling SemaDecl.cpp
Commit: d936924f5e22e8efbc27873f62e8dfc6e410fcf9
https://github.com/llvm/llvm-project/commit/d936924f5e22e8efbc27873f62e8dfc6e410fcf9
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Profile/YAMLProfileReader.cpp
Log Message:
-----------
[BOLT][NFC] Make YamlProfileToFunction a DenseMap (#108712)
YAML function profiles have sparse function IDs, assigned from
sequential function IDs from profiled binary. For example, for one large
binary, YAML profile has 15K functions, but the highest ID is ~600K,
close to number of functions in the profiled binary.
In `matchProfileToFunction`, `YamlProfileToFunction` vector was resized
to match function ID, which entails a 40X overcommit. Change the type of
`YamlProfileToFunction` to DenseMap to reduce memory utilization.
#99891 makes use of it for profile lookup associated with a given binary
function.
Commit: 62a7bb09e3646780b7bceb7cef4eba257e3a9818
https://github.com/llvm/llvm-project/commit/62a7bb09e3646780b7bceb7cef4eba257e3a9818
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Resolve CHECK prefix conflict and add a bunch of FIXMEs to bitmanip tests. NFC
Commit: bc1aa2863bd33756a5cc0b729792be0aabed67f4
https://github.com/llvm/llvm-project/commit/bc1aa2863bd33756a5cc0b729792be0aabed67f4
Author: Lei Wang <wlei at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/test/Other/new-pm-pgo-O0.ll
Log Message:
-----------
[SampleFDO] Support enabling sample loader pass in O0 mode (#113985)
Add support for enabling sample loader pass in O0 mode(under
`-fsample-profile-use`). This can help verify PGO raw profile count
quality or provide a more accurate performance proxy(predictor), as O0
mode has minimal or no compiler optimizations that might otherwise
impact profile count accuracy.
- Explicitly disable the sample loader inlining to ensure it only emits
sampling annotation.
- Use flattened profile for O0 mode.
- Add the pass after `AddDiscriminatorsPass` pass to work with
`-fdebug-info-for-profiling`.
Commit: cb98366ea4ce02e739eb4091c6227b67b60616c9
https://github.com/llvm/llvm-project/commit/cb98366ea4ce02e739eb4091c6227b67b60616c9
Author: Pranav Kant <prka at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add exp10m1f (#115565)
Commit: ff98efa329f3866ed7ddd461e9473729c2b91568
https://github.com/llvm/llvm-project/commit/ff98efa329f3866ed7ddd461e9473729c2b91568
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV][GISel] Enable shift_immed_chain in RISCVPostLegalizerCombiner
This helps combine back to back shifts that may get created when
sext_inreg is legalized.
Commit: 818d715989a82a54bac038b9c293e34dbea45f5c
https://github.com/llvm/llvm-project/commit/818d715989a82a54bac038b9c293e34dbea45f5c
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
Log Message:
-----------
[Analysis] atan2: isTriviallyVectorizable; add to massv and accelerate veclibs (#113637)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
- Return true for atan2 from isTriviallyVectorizable
- Add atan2 to VecFuncs.def for massv and accelerate libraries.
- Add atan2 to hasOptimizedCodeGen
- Add atan2 support in llvm/lib/Analysis/ValueTracking.cpp
llvm::getIntrinsicForCallSite and update vectorization tests
- Add atan2 name check to isLoweredToCall in
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
- Note: there's no test coverage for these names in isLoweredToCall, except that Transforms/TailCallElim/inf-recursion.ll is impacted by the "fabs" case
Thanks to @jroelofs for the atan2 accelerate veclib and associated test
additions, plus the hasOptimizedCodeGen addition.
Part of: Implement the atan2 HLSL Function #70096.
Commit: ff2251543069d9a195256617620b5fdf81512471
https://github.com/llvm/llvm-project/commit/ff2251543069d9a195256617620b5fdf81512471
Author: Alan Zhao <ayzhao at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
R clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
R clang/test/CodeGen/X86/amx_avx512_api.c
R clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
R llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
R llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
R llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
R llvm/test/MC/Disassembler/X86/amx-avx512.txt
R llvm/test/MC/X86/amx-avx512-att.s
R llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070
Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
Commit: f791cfc822fab3fa87b4aa10ef96a3401481850f
https://github.com/llvm/llvm-project/commit/f791cfc822fab3fa87b4aa10ef96a3401481850f
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port ff2251543069
Commit: 7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
https://github.com/llvm/llvm-project/commit/7ec682b16b49c754d5b4aa6347f8f5a00bd7dd78
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/lib/MC/MCPseudoProbe.cpp
Log Message:
-----------
[MC] Use StringRefs from pseudo_probe_desc section if it's mapped
Add `IsMMapped` flag to `buildGUID2FuncDescMap` controlling whether to
allocate a string in `FuncNameAllocator` or use StringRef directly.
Keep it false by default, only set it for BOLT use case because BOLT
keeps file sections in memory while processing them. llvm-profgen
constructs GUID2FuncDescMap and then releases the binary.
For medium sized binary with 0.8 GiB .pseudo_probe_desc section, this
saves 0.7 GiB peak RSS in perf2bolt.
Test Plan: no-op for llvm-profgen, NFC for perf2bolt
Reviewers: maksfb, dcci, wlei-llvm, rafaelauler, ayermolo
Reviewed By: wlei-llvm
Pull Request: https://github.com/llvm/llvm-project/pull/112996
Commit: b70eb8631386bbccca5a07bb0253aa738d4cda81
https://github.com/llvm/llvm-project/commit/b70eb8631386bbccca5a07bb0253aa738d4cda81
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
Log Message:
-----------
[lld][WebAssemlby] Implement --thinlto-object-suffix-replace/--thinlto-prefix-replace (#114625)
Fixes: #79604
Commit: 6548b6354d1d990e1c98736f5e7c3de876bedc8e
https://github.com/llvm/llvm-project/commit/6548b6354d1d990e1c98736f5e7c3de876bedc8e
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
Commit: d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
https://github.com/llvm/llvm-project/commit/d413335ccf5cad3a8cb4ebce49a1d22daabbf3ad
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
Log Message:
-----------
[HLSL] Add Append/ConsumeStructuredBuffer definitions to HLSLExternalSemaSource (#113643)
Adds `AppendStructuredBuffer` and `ConsumeStructuredBuffer` definition
to HLSLExternalSemaSource. Adds separate tests for the AST shape and
element types, and adds constructor/handle.fromBinding test case to
shared test file for structured buffers.
These buffers do not have any subscript operators. Append and Consume
methods will be added later in llvm/llvm-project#112968.
Fixes #112777
Commit: c93e001ca695e905cb965b36d63f7a348d1dd809
https://github.com/llvm/llvm-project/commit/c93e001ca695e905cb965b36d63f7a348d1dd809
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
Log Message:
-----------
[FIX][AMDGPU] Fix test case failures that caused by reapply of #112403
Commit: 60ea60e36eb6de19e8e509e5b50a390e95801321
https://github.com/llvm/llvm-project/commit/60ea60e36eb6de19e8e509e5b50a390e95801321
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Log Message:
-----------
[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC
Commit: c61832444d7539eddb939df1107a751a6784aff3
https://github.com/llvm/llvm-project/commit/c61832444d7539eddb939df1107a751a6784aff3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
Log Message:
-----------
[memprof] Teach extractCallsFromIR to look into inline stacks (#115441)
To undrift the profile, we need to extract as many caller-callee pairs
from the IR as we can to maximize the number of call sites in the
profile we can undrift.
Now, since MemProfUsePass runs after early inlining, some functions
have been inlined, and we may no longer have bodies for those
functions in the IR. To cope with this, this patch teaches
extractCallsFromIR to extract caller-calee pairs from inline stacks.
The output format of extractCallsFromIR remains the same. We still
return a map from caller GUIDs to lists of corresponding call sites.
Commit: 1bf385f10291101163a346c8f075d56e1578351b
https://github.com/llvm/llvm-project/commit/1bf385f10291101163a346c8f075d56e1578351b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
Log Message:
-----------
AMDGPU: Default to selecting frame indexes to SGPRs (#115060)
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
Commit: fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
https://github.com/llvm/llvm-project/commit/fb4f426c81d7e87dbb30df7abeba15ffc2f9f41a
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Add a comment why an export file is needed. (#115556)
- [x] Add follow-up comment on why the export file is needed in
BUILD.bazel
Commit: 501a58344179242f702f55e0ee5c039290426c54
https://github.com/llvm/llvm-project/commit/501a58344179242f702f55e0ee5c039290426c54
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
Log Message:
-----------
[TableGen][SelectionDAG] Remove the `implicit` DAG node (#115295)
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`
However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`
The latter form is also more flexible as it allows reordering output
operands.
In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.
Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.
Commit: 5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
https://github.com/llvm/llvm-project/commit/5e02fd8d0b3c6638220c95e997c43fdc9d7ded3c
Author: Mirko <mirkomueller97 at live.de>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/LiveRangeShrink.cpp
A llvm/test/CodeGen/X86/lrshrink-debug.ll
Log Message:
-----------
[CodeGen][X86] LiveRangeShrink: fix increment after end (#115276)
This fixes the infinite loop discovered in #114195.
Since we skip debug instructions at the start of the loop we do not need
to skip them again at the end of the loop.
Commit: 8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
https://github.com/llvm/llvm-project/commit/8f4401374ca1a1eaf47d90d0fc3d189c862ae4f2
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxavx512intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_avx512_api.c
A clang/test/CodeGen/X86/amxavx512-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86PreTileConfig.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll
A llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll
A llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll
A llvm/test/MC/Disassembler/X86/amx-avx512.txt
A llvm/test/MC/X86/amx-avx512-att.s
A llvm/test/MC/X86/amx-avx512-intel.s
Log Message:
-----------
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
Commit: cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
https://github.com/llvm/llvm-project/commit/cdc1c1ac84ea525b8c2dceaeb7d29ede94346acf
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 8f4401374ca1
Commit: 09b372aa60548b8ee94a801d3d966001ad60a677
https://github.com/llvm/llvm-project/commit/09b372aa60548b8ee94a801d3d966001ad60a677
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576)
SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses
a literal constant operand.
For vectors, SelectionDAG uses a type with the same number of elements
as other operand of the sext_inreg. I assume for GISel we would just use
the scalar size.
Commit: b83399eab603320d3c2998450f4ada83e7fe746c
https://github.com/llvm/llvm-project/commit/b83399eab603320d3c2998450f4ada83e7fe746c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-08 (Fri, 08 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
Log Message:
-----------
[GlobalISel] Remove unused includes (NFC) (#115429)
Identified with misc-include-cleaner.
Commit: fe6366928201b7500ee7e903c01bf4bbd661ee2d
https://github.com/llvm/llvm-project/commit/fe6366928201b7500ee7e903c01bf4bbd661ee2d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
A llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Support `MachineFunction` in `OptNoneInstrumentation` (#115471)
Support `MachineFunction` in `OptNoneInstrumentation`, also add
`isRequired` to all necessary passes.
Commit: 9afec3ca3e926cd481af372b72ee5bd7e54942d0
https://github.com/llvm/llvm-project/commit/9afec3ca3e926cd481af372b72ee5bd7e54942d0
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/optnone.mir
Log Message:
-----------
[Instrumentation] Fix test failure in #115471 (#115596)
Add triple to indicate this is x86 test.
Commit: 5a41800ea1d9bf382cf1039da6016550ddb072d7
https://github.com/llvm/llvm-project/commit/5a41800ea1d9bf382cf1039da6016550ddb072d7
Author: Afanasyev Ivan <ivafanas at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[SROA] Fix NumPromoted statistic for SROA pass (#115586)
`NumPromoted` stat should not be increased if `SROASkipMem2Reg` is set
and nothing is changed.
Commit: 10f35a04c94e96c1cc0497f2b3b2ab8536a98059
https://github.com/llvm/llvm-project/commit/10f35a04c94e96c1cc0497f2b3b2ab8536a98059
Author: Princeton Ferro <pferro at nvidia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Log Message:
-----------
[InstCombine] add control for SimplifyDemandedVectorElts depth limit (#113717)
Allows customizing the depth of the recursive search on vectors that
InstCombine does when looking for unused elements.
We find it helpful to be able to customize this for compile time
reasons.
Commit: 5a08acc1e7874a6cb4b273988b83e587e6fea605
https://github.com/llvm/llvm-project/commit/5a08acc1e7874a6cb4b273988b83e587e6fea605
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
Log Message:
-----------
[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)
Without this, you get an error "Do not know how to soften the result of
this operator!" when compiling for a soft float target.
The libcall names match those defined in glibc
<https://www.gnu.org/software/libc/manual/html_node/Misc-FP-Arithmetic.html>
and more recently added to LLVM's libc
<https://github.com/llvm/llvm-project/pull/86016>.
Commit: ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
https://github.com/llvm/llvm-project/commit/ae4fc80574cfbbf2b2b53f2728cd785db76e9e69
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
Log Message:
-----------
[RISCV] When using global merging, don't enable merging of external globals by default (#115484)
AArch64 left this disabled after seeing some cases of slightly worse
codegen that weren't tracked down, so I suggest as a path to
incrementally moving towards enable globals merging we follow suit, and
evaluate turning on later.
This patch disables merging of external globals, but also adds a flag to
override that. This reduces churn in test cases, simplifies benchmarking
runs, and this flag can be removed later.
A follow-on PR enables the globals merging pass by default (and as it's
based on this commit, merging of external globals is disabled just as
they are for AArch64).
Commit: 8833a4474654f7413ae3c53a15e350e06bce2d2e
https://github.com/llvm/llvm-project/commit/8833a4474654f7413ae3c53a15e350e06bce2d2e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Connect scalar header to CFG in VPlan unit test.
This makes sure the VPIRBasicBlock is deleted when the VPlan is
destroyed.
Fixes https://github.com/llvm/llvm-project/issues/114623.
Commit: 581106759a3eb85d37aa004e0ad795dc8b433080
https://github.com/llvm/llvm-project/commit/581106759a3eb85d37aa004e0ad795dc8b433080
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lld/COFF/InputFiles.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/lto-arm64ec.ll
Log Message:
-----------
[LLD][COFF] Support ARM64EC in BitcodeFile::getMachineType (#115474)
Commit: 1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
https://github.com/llvm/llvm-project/commit/1aff96b3dfcc58d62fda5b1452a8029f1a737cc2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
Log Message:
-----------
[InstCombine] Add extra tests for preserving load metadata.
Test cases for https://github.com/llvm/llvm-project/issues/115595.
Commit: 56253c79c61fb5478bc3162cfe1e25e98791a148
https://github.com/llvm/llvm-project/commit/56253c79c61fb5478bc3162cfe1e25e98791a148
Author: David Green <david.green at arm.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/ptradd.ll
Log Message:
-----------
[GlobalISel][AArch64] Generate ptrtoint/inttoptr as opposed to bitcast in unmerge combine. (#115225)
When combining unmerge we could end up with ptr to i64 bitcasts. Make
sure they are created as ptrtoint/inttoptr instead.
Commit: 7ac62f33cffb618758edb6a0997c21b2319fbf9b
https://github.com/llvm/llvm-project/commit/7ac62f33cffb618758edb6a0997c21b2319fbf9b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
Log Message:
-----------
[InstCombine] Add load/select test with noundef/invariant.load.
Further extends the test coverage added in 1aff96b3dfc with a load with
noundef and invariant.load metadata, which may trigger UB.
Commit: 6beaa123a2899f52dd5f37b881d7fc398d70e167
https://github.com/llvm/llvm-project/commit/6beaa123a2899f52dd5f37b881d7fc398d70e167
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrUtils.td
Log Message:
-----------
[X86] Make use of `null_frag` (NFC) (#115601)
Commit: 1d41543c95f884e6ebecc63ab9d0d30ce481345c
https://github.com/llvm/llvm-project/commit/1d41543c95f884e6ebecc63ab9d0d30ce481345c
Author: lntue <lntue at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M libc/src/math/generic/log1p.cpp
M libc/test/src/math/smoke/log1p_test.cpp
Log Message:
-----------
[libc][math] Fix log1p SEGV with large inputs when FTZ/DAZ flags are set. (#115541)
Commit: 3654183afb283c9515a482f07fde730dd458a883
https://github.com/llvm/llvm-project/commit/3654183afb283c9515a482f07fde730dd458a883
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Allow promotion if target is a declaration (#115555)
Fixes an oversight in the MemProf ICP handling, that was blocking
promotion/cloning of indirect calls when the profiled target is a
declaration (i.e wasn't imported). There is no issue promoting in
that case, and in fact the comment mentions we should attempt to at
least import as declarations to enable more promotion.
Note that normal ICP currently requires that the target be a definition,
which is how this check ended up here. The comment there says that it
must be a definition because ThinLTO could remove declarations for
symbols found to be globally dead in the binary. However, here we are
always performing MemProf ICP in the ThinLTO backends, which is after
the globally dead symbols are removed (via dropDeadSymbols before
starting the optimization pipeline) [1].
For now, guard this with an option (flag is off which means the new
promotion is enabled by default) to simplify debugging or disabling it
if
this proves problematic.
[1] In fact we could also be more aggressive in regular ICP when invoked
in the ThinLTO backend
Commit: 6fb2a6044f11e251c3847d227049d9dae8b87796
https://github.com/llvm/llvm-project/commit/6fb2a6044f11e251c3847d227049d9dae8b87796
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] Add test coverage for #115575
Commit: 958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
https://github.com/llvm/llvm-project/commit/958e37cd1feabf29fb1cc3fb5ac82051ad8d43eb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/pr115575.ll
Log Message:
-----------
[VectorCombine] scalarizeBinopOrCmp - check for out of bounds element indices
Fixes #115575
Commit: ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
https://github.com/llvm/llvm-project/commit/ccaded2b1d0d2cf3d8041baeeec9cfad632c9450
Author: Harald van Dijk <harald.vandijk at codeplay.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
Log Message:
-----------
[Inliner] Prevent adding pointer attributes to non-pointer arguments (#115569)
Fixes a crash seen after #114311
Commit: c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
https://github.com/llvm/llvm-project/commit/c3c424d2eafeba4ec25df8698e6311a8fa78fbfe
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
Log Message:
-----------
[lldb-dap] Use heterogenous lookups with std::map (NFC) (#115590)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: eedff8b4c0c667c39b034f02c9a40693dff63eda
https://github.com/llvm/llvm-project/commit/eedff8b4c0c667c39b034f02c9a40693dff63eda
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
Log Message:
-----------
[DebugInfo] Simplify code with std::map::operator[] (NFC) (#115591)
Commit: dfe43bd1ca46c59399b7cbbf81b09256232e27f9
https://github.com/llvm/llvm-project/commit/dfe43bd1ca46c59399b7cbbf81b09256232e27f9
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
Log Message:
-----------
[X86] Remove unused includes (NFC) (#115593)
Identified with misc-include-cleaner.
Commit: 95eeae195e608797314d71f7327e638a98764471
https://github.com/llvm/llvm-project/commit/95eeae195e608797314d71f7327e638a98764471
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add PredIdx and SuccIdx arguments to connectBlocks (NFC).
Add extra arguments to connectBlocks which allow selecting which
existing predecessor/successor to update. This avoids having to
disconnect blocks first unnecessarily.
Suggested in https://github.com/llvm/llvm-project/pull/114292.
Commit: f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
https://github.com/llvm/llvm-project/commit/f8fea5d49ba6f9e6c6fedc5a6e1f7c30cefd5357
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/tools/llvm-pdbutil/PdbYaml.h
Log Message:
-----------
[llvm] Add explicit visibility macros to YAMLTraits classes (#111484)
These symbols need to be exported for llvm-pdbutil when using windows
shared library builds.
Exclude the YAML traits declared in llvm-pdbutil so there not declared
as dllimported which will causing missing symbol errors for windows
shared library builds.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
window.
Commit: 230946fad69c952dc434aa3e2f92853c1ee8d304
https://github.com/llvm/llvm-project/commit/230946fad69c952dc434aa3e2f92853c1ee8d304
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
Log Message:
-----------
[ADT] Mark reverse and concat as nodiscard (#115611)
It may not be immediately obvious if these two functions modify the
given ranges or return a view over them. We have seen downstream code
that mistakenly assumed the given range would be mutated.
Add the `[[nodiscard]]` attribute to prevent these errors. Also clarify
the lack of mutation in the documentation comments.
Commit: 69fb9bcde0312e672e6f2280f8662784731d79e6
https://github.com/llvm/llvm-project/commit/69fb9bcde0312e672e6f2280f8662784731d79e6
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
Log Message:
-----------
Fix false positive in bugprone-throw-keyword-missing (#115302)
Fixes #115055
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
https://github.com/llvm/llvm-project/commit/ccb40b0b7a51a0619acc8a6b479b86ff28a19e5b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add insertOnEdge to VPBlockUtils (NFC).
Add a new helper to insert a new VPBlockBase on an edge between 2
blocks. Suggested in https://github.com/llvm/llvm-project/pull/114292
and also useful for some existing code.
Commit: c236dbc343b497c11790adc61cf4e041aeb42dbc
https://github.com/llvm/llvm-project/commit/c236dbc343b497c11790adc61cf4e041aeb42dbc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[Vectorize] Simplify code with MapVector::operator[] (NFC) (#115592)
Commit: 0ac4821b718dd14e80d3856efa532d52df6878bb
https://github.com/llvm/llvm-project/commit/0ac4821b718dd14e80d3856efa532d52df6878bb
Author: Javed Absar <106147771+javedabsar1 at users.noreply.github.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
Log Message:
-----------
[mlir][linalg] unfold projected permutation. (#114704)
Patterns to decompose the input operand(s) of a linalg.generic that has
a projected permutation` affine-map -- i.e. effectively a folded `transpose`,
`broadcast`, or a mixture of two -- into explicit transpose and broadcast.
This is useful for instance when trying to recognize named ops.
email: quic_mabsar at quicinc.com
Commit: 10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
https://github.com/llvm/llvm-project/commit/10b80ff0cc3e6af8fddb9003571e2cc22f9c58b2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
Log Message:
-----------
[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: 38b0e1c939e818564019bb5bff95a0f1abbf9d19
https://github.com/llvm/llvm-project/commit/38b0e1c939e818564019bb5bff95a0f1abbf9d19
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Add legalizer-info-validation test. NFC
Based on the same test from AArch64. I used a reasonable superset
ISA string to get the most coverage. Might be worth adding more
RUN lines in the future.
Commit: 08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
https://github.com/llvm/llvm-project/commit/08af115d97e39223b5cc8bdbc56b1dfb758bf6d3
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
Log Message:
-----------
Fix mistakes in #113532 (#115631)
Found during review #115151
Commit: d6e65a66095cc3c93ea78669bc41d0885780e8ea
https://github.com/llvm/llvm-project/commit/d6e65a66095cc3c93ea78669bc41d0885780e8ea
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
Log Message:
-----------
Fix a warning. [-Wunused-but-set-variable]
Commit: 3cdd86bb476bb90e535552fe86ba5f9d15f33d37
https://github.com/llvm/llvm-project/commit/3cdd86bb476bb90e535552fe86ba5f9d15f33d37
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Make GetMinMaxCost support FixedVectorType when REVEC is enabled. (#115417)
Commit: 639cafd05f5559c8fed92d58705dec817f876e23
https://github.com/llvm/llvm-project/commit/639cafd05f5559c8fed92d58705dec817f876e23
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-09 (Sat, 09 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[RISCV][GISel] Use boolean predicated legalization action methods to remove a custom lambda. (#115628)
Commit: f344367f583538746b13a5560bcdedacbd295ee7
https://github.com/llvm/llvm-project/commit/f344367f583538746b13a5560bcdedacbd295ee7
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/test/ELF/aarch64-feature-pac.s
Log Message:
-----------
[PAC][lld] Test warning emitted for non-PAuth-marked files with `-z pac-plt` (#112958)
b6162622c054f changed semantics of `-z pac-plt` initially introduced in
e208208a3132c, so, the following comment from test/ELF/aarch64-feature-pac.s
is no longer true:
> There are no warnings in this case as the choice to use PAC in PLT entries
> is orthogonal to the choice of using PAC in relocatable objects. The
> presence of the PAC .note.gnu.property is an indication of preference by
> the relocatable object.
This patch updates the test so we ensure a warning is emitted for an
input file when `-z pac-plt` is passed but the file does not have
GNU_PROPERTY_AARCH64_FEATURE_1_PAC set in GNU_PROPERTY_AARCH64_FEATURE_1_AND
property.
Commit: e4c14190bb097162e15cd5822b3de97ea7bac0d6
https://github.com/llvm/llvm-project/commit/e4c14190bb097162e15cd5822b3de97ea7bac0d6
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
M mlir/test/Analysis/test-dominance.mlir
M mlir/test/lib/IR/TestDominance.cpp
Log Message:
-----------
[mlir][IR] `DominanceInfo`: Fix inconsistency in proper block/op dominance (#115413)
An operation is considered to properly dominate itself in a graph
region. That's because there is no concept of "dominance" in a graph
region. (`dominates` returns "true" for all pairs of ops in the same
block. It makes sense to do the same for `properlyDominates`.)
Previously, a block was *not* considered to dominate itself in a graph
region. This commit fixes this asymmetry between ops and blocks: both
are now properly dominating themselves in a graph region.
Commit: e1495283cf74590fbdeb6d46ad815b4d10b1902f
https://github.com/llvm/llvm-project/commit/e1495283cf74590fbdeb6d46ad815b4d10b1902f
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/test/Driver/riscv-profiles.c
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.
We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024
So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.
Commit: 59770a43826f19ed2a735b1e461a43c63bd456bf
https://github.com/llvm/llvm-project/commit/59770a43826f19ed2a735b1e461a43c63bd456bf
Author: c8ef <c8ef at outlook.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
Log Message:
-----------
[NFC] Correct imprecise file location in the comment. (#115630)
Commit: 4edd711b4d7ec60117bf77ab79491dba8cf3bb76
https://github.com/llvm/llvm-project/commit/4edd711b4d7ec60117bf77ab79491dba8cf3bb76
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
Log Message:
-----------
[NVPTX] Add TMA bulk tensor prefetch intrinsics (#115527)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.prefetch.1D -> 5D variants, supporting both Tile
and Im2Col modes. These intrinsics optionally support cache_hints as
indicated by the boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in cp-async-bulk-tensor-prefetch.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d822c099eeacc69f6bf834a6373a41d0c9f84a3e
https://github.com/llvm/llvm-project/commit/d822c099eeacc69f6bf834a6373a41d0c9f84a3e
Author: Douglas <8796590+dgg5503 at users.noreply.github.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[JITLink] Use `rsplit` on `-sectcreate` argument in llvm-jitlink (#115511)
This accounts for cases where the file path may contain an `@` symbol.
In such cases, the split occurs too early causing argument parsing to
fail.
Commit: 27bf45aa36386136db179c494358670a994a98a5
https://github.com/llvm/llvm-project/commit/27bf45aa36386136db179c494358670a994a98a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
Log Message:
-----------
[InstCombine] Fix poison safety of folding shufflevector into select (#115483)
We are allowed to fold shufflevector into select iff the condition is
guaranteed not to be poison or the RHS is a poison.
Alive2: https://alive2.llvm.org/ce/z/28zEWR
Closes https://github.com/llvm/llvm-project/issues/115465.
Commit: a5a1612deb7af713835b5c8cf22105c5699bc62d
https://github.com/llvm/llvm-project/commit/a5a1612deb7af713835b5c8cf22105c5699bc62d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
Log Message:
-----------
[VPlan] Consistently use DEBUG_TYPE loop-vectorize.
This ensures debug messages in VPlan.cpp are included in the commonly
used -debug-only=loop-vectorize.
Commit: 81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
https://github.com/llvm/llvm-project/commit/81613ddcd6fe04a029c1a15a3454b5b0cd18a24c
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
Log Message:
-----------
[ORC] Move some typedefs from Core.h to a new header, CoreContainers.h. NFC.
This is a first step towards breaking up Core.h
Commit: 3d2849bd151f415b59044736e069c7605339b8e2
https://github.com/llvm/llvm-project/commit/3d2849bd151f415b59044736e069c7605339b8e2
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Move MaterializationUnit from Core.h into its own header. NFC.
Continuing Core.h clean-up.
Commit: 7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
https://github.com/llvm/llvm-project/commit/7085ac8a0718a3a37c7cb6641203e72fbc0b1aea
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
Log Message:
-----------
[ORC] Switch to C++17 nested namespaces. NFC.
Commit: ac30a0f349c960184c0165adcd87baecfc48a1af
https://github.com/llvm/llvm-project/commit/ac30a0f349c960184c0165adcd87baecfc48a1af
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
Log Message:
-----------
[PAC][lld] Do not emit warnings for `-z pac-plt` with valid PAuth core info (#112959)
When PAuth core info is present and (platform,version) is not (0,0),
treat input files as pac-enabled and do not emit a warning with
`-z pac-plt` passed.
Commit: 2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
https://github.com/llvm/llvm-project/commit/2c10664afafcd5915ebbde9cb7cb0e9cf8751b34
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/any
M libcxx/include/module.modulemap
M libcxx/include/type_traits
M libcxx/include/variant
Log Message:
-----------
[libc++][NFC] Merge add_{const, cv, volatile}.h into a single header (#115610)
There isn't much benefit in having granular headers for only a few
simple lines of code.
Commit: ad2d313f7455fe27896db8df9ea9aadd60b53436
https://github.com/llvm/llvm-project/commit/ad2d313f7455fe27896db8df9ea9aadd60b53436
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2c10664afafc
Commit: 7c13477351046c115ad86e047f3f7346bb925b19
https://github.com/llvm/llvm-project/commit/7c13477351046c115ad86e047f3f7346bb925b19
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
Log Message:
-----------
[X86] Delete unused X86setcc_commute node (NFC) (#115650)
The last use was removed by 87aa59a0.
Commit: 99f1019f596f745c720e97137bcadb239c573e3e
https://github.com/llvm/llvm-project/commit/99f1019f596f745c720e97137bcadb239c573e3e
Author: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/docs/SafeBuffers.rst
Log Message:
-----------
[NFC] Trivial doc fixup in SafeBuffers.rst
Commit: 1d6d073fbbaebbde6891501fe20f02a0ea345131
https://github.com/llvm/llvm-project/commit/1d6d073fbbaebbde6891501fe20f02a0ea345131
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
Log Message:
-----------
[AArch64] Remove FeatureUseScalarIncVL
FeatureUseScalarIncVL is a tuning feature, used to control whether addvl or
add+cnt is used. It was previously added as a dependency for FeatureSVE2, an
architecture feature but this can be seen as a layering violation. The main
disadvantage is that -use-scalar-inc-vl cannot be used without disabling sve2
and all dependant features.
This patch now replaces that with an option that if unset defaults to hasSVE ||
hasSME, but is otherwise overriden by the option. The hope is that no cpus will
rely on the tuning feature (or we can readdit if needed.
Commit: c8f33738a5a801b5bc083ae9b2ced39ef1b12980
https://github.com/llvm/llvm-project/commit/c8f33738a5a801b5bc083ae9b2ced39ef1b12980
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64] Rewrite arm64-ext.ll test and cleanup. NFC
Commit: 91a48e06463b23679907e151bdfec3e6093e9f16
https://github.com/llvm/llvm-project/commit/91a48e06463b23679907e151bdfec3e6093e9f16
Author: David Green <david.green at arm.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-ext.ll
Log Message:
-----------
[AArch64][GlobalISel] Implicitly truncate APInt in matchExt combine.
The APInt using FirstRealElt + 1 is intended to match the next element, which
might overflow the size of MaskBits. This prevents a new assert in APInt from
triggering.
Commit: 5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
https://github.com/llvm/llvm-project/commit/5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115626)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: a44ee8ec1c87be76e147d97f3be90a7e8630421b
https://github.com/llvm/llvm-project/commit/a44ee8ec1c87be76e147d97f3be90a7e8630421b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115633)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: 2c0f463b2546a98e6215f3a85940ab9c0971d2aa
https://github.com/llvm/llvm-project/commit/2c0f463b2546a98e6215f3a85940ab9c0971d2aa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[Vectorize] Simplify code with DenseMap::operator[] (NFC) (#115635)
Commit: 1e25c921d523151e6ed2ffe86029ea2e2b267a6c
https://github.com/llvm/llvm-project/commit/1e25c921d523151e6ed2ffe86029ea2e2b267a6c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Log Message:
-----------
[AArch64/GISel] Remove unused includes (NFC) (#115636)
Identified with misc-include-cleaner.
Commit: 15ce2e183fb801ff418eb1347a9d5893e5665782
https://github.com/llvm/llvm-project/commit/15ce2e183fb801ff418eb1347a9d5893e5665782
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/source/Commands/CommandObjectMultiword.cpp
Log Message:
-----------
[lldb] Use heterogenous lookups with std::map (NFC) (#115590) (#115634)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: ff0698b258eba9afd888159358c7369c3f85e9ae
https://github.com/llvm/llvm-project/commit/ff0698b258eba9afd888159358c7369c3f85e9ae
Author: Will <william.fedele1 at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix examples for float to int saturating intrinsics (#115629)
As per the [LangRef:Simple
Constants](https://llvm.org/docs/LangRef.html#simple-constants), exact
decimal values of floating-point constants are required. For instance,
23.9 is a repeating decimal in binary and results in the reported error.
https://godbolt.org/z/1h7ETPnf6
Fixes #113529.
Commit: 028ea71fdda0c02cd11421cd1d26bec6f378666e
https://github.com/llvm/llvm-project/commit/028ea71fdda0c02cd11421cd1d26bec6f378666e
Author: Julian Schmidt <git.julian.schmidt at gmail.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
Log Message:
-----------
[clang-tidy] fix insertion location for function pointers in cppcoreguidelines-init-variables (#112091)
Previously, the insertion location for the `= nullptr` fix would be
after the variable name. However, if the variable is of type function
pointer that is not an alias, then the insertion would happen inside the
type specification: `void (*a1)(void*);` -> `void (*a1 =
nullptr)(void*);`.
With this change, the insertion location will be at the next
'terminator'. That is, at the next `,` or `;`, as that will finish the
current declaration: `void (a1)(void*) = nullptr;`.
Fixes #112089
Commit: 7111d031f19ce7d523796b4812d6afcb2958b025
https://github.com/llvm/llvm-project/commit/7111d031f19ce7d523796b4812d6afcb2958b025
Author: Fangrui Song <i at maskray.me>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
Log Message:
-----------
[Xtensa] Fix Clang -Wundefined-bool-conversion after #113450
Commit: 3006dddfe091bcb95924d72dddbb84f73186a344
https://github.com/llvm/llvm-project/commit/3006dddfe091bcb95924d72dddbb84f73186a344
Author: Janis Heims <janis.heims at undertheprinter.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/test/CodeGen/M68k/multiple-return.ll
Log Message:
-----------
[M68k] fix call frame destruction elimination when returning structs (#107579)
Fixes #106213.
This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.
Commit: dc11c0601577afb8f67513d041ee25dabe3555b9
https://github.com/llvm/llvm-project/commit/dc11c0601577afb8f67513d041ee25dabe3555b9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
Log Message:
-----------
[ORC] Move absoluteSymbols from Core.h to new AbsoluteSymbols.h header. NFC.
Continuing Core.h clean-up.
If you see any errors about a missing absoluteSymbols function you need to
include the new AbsoluteSymbols.h header.
Commit: 0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
https://github.com/llvm/llvm-project/commit/0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port dc11c0601577
Commit: 3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
https://github.com/llvm/llvm-project/commit/3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd
Author: Doug Wyatt <doug at sonosphere.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/test/Sema/attr-nonblocking-constraints.cpp
Log Message:
-----------
[Clang] SemaFunctionEffects: When verifying a function, ignore any conditional noexcept expression. (#115342)
---------
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
Commit: e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
https://github.com/llvm/llvm-project/commit/e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (#115436)
This is a follow-up patch for
https://github.com/llvm/llvm-project/pull/101811.
That we can remove the type checking for fp16 from SemaRISCV.cpp.
Fixes: https://github.com/llvm/llvm-project/issues/101621 and
https://github.com/llvm/llvm-project/issues/94306
Commit: 595f3e925adaffcb10d40e2e704c67556e9afb18
https://github.com/llvm/llvm-project/commit/595f3e925adaffcb10d40e2e704c67556e9afb18
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/IR/Dominance.h
M mlir/lib/IR/Dominance.cpp
Log Message:
-----------
[mlir][IR][NFC] `PostDominanceInfo`: Mark all functions as `const` (#115597)
Same as `DominanceInfo`, all functions should be `const`.
Commit: 5082acce4fd3646d5760c02b2c21d9cd2a1d7130
https://github.com/llvm/llvm-project/commit/5082acce4fd3646d5760c02b2c21d9cd2a1d7130
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Add custom libc++ workaround for CMake < 3.26
The INSTALL_BYPRODUCTS ExternalProject_Add() argument was only added in
CMake 3.26 and the current minimum is 3.20. Work around this by using an
explicit ExternalProject_Add_Step() call for the install step with a
BYPRODUCTS argument. We can't keep using the `install` name here since that
is reserved by the CMake implementation and results in errors when used.
This commit should be reverted once LLVM depends on CMake 3.26.
Pull Request: https://github.com/llvm/llvm-project/pull/115677
Commit: 5ca082cdfed2e0d3d9499d2c70d8a38dacd2539e
https://github.com/llvm/llvm-project/commit/5ca082cdfed2e0d3d9499d2c70d8a38dacd2539e
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Fix evl type on float VP reduction intrinsics (#115421)
Looks like a search-and-replace typo
Commit: b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
https://github.com/llvm/llvm-project/commit/b2e2d8b3f6bb7c647c1e4cfe6d2765e1b0a15497
Author: Luke Lau <luke at igalia.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
Log Message:
-----------
[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)
This PR enables scalable loop vectorization for f16 with zvfhmin and
bf16 with zvfbfmin.
Enabling this was dependent on filling out the gaps for scalable
zvfhmin/zvfbfmin codegen, but everything that the loop vectorizer might
emit should now be handled.
It does this by marking f16 and bf16 as legal in
`isLegalElementTypeForRVV`. There are a few users of
`isLegalElementTypeForRVV` that have already been enabled in other PRs:
- `isLegalStridedLoadStore` #115264
- `isLegalInterleavedAccessType` #115257
- `isLegalMaskedLoadStore` #115145
- `isLegalMaskedGatherScatter` #114945
The remaining user is `isLegalToVectorizeReduction`. We can't promote
f16/bf16 reductions to f32 so we need to disable them for scalable
vectors. The cost model actually marks these as invalid, but for
out-of-tree reductions `ComputeReductionResult` doesn't get costed and
it will end up emitting a reduction intrinsic regardless, so we still
need to mark them as illegal. We might be able to remove this
restriction later for fmax and fmin reductions.
Commit: a912c81f651109c677dcfdf2b1173a78e853a19d
https://github.com/llvm/llvm-project/commit/a912c81f651109c677dcfdf2b1173a78e853a19d
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/Core/LVLocation.cpp
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
Log Message:
-----------
[llvm-debuginfo-analyzer] Fix crash with thread local storage. (#113904)
The DW_OP_GNU_push_tls_address, DW_OP_form_tls_address DWARF
location forms generated for thread local storage variables, caused a
crash in the DWARFReader, due to incorrect number of operands.
Commit: ffc7feadece139c88f0e6930f16bfa9293747adc
https://github.com/llvm/llvm-project/commit/ffc7feadece139c88f0e6930f16bfa9293747adc
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
Log Message:
-----------
[mlir][mesh] Handling changed halo region sizes during spmdization (#114238)
* Changed `MeshSharding::sharded_dims_sizes` from representing sizes per
shard to offsets to origin per shard.
- Local shard size are now a simple subtraction
- Offsets are now readily available without a reduction operation
- Enables constant value/shape propagation through standard
canonicalization
- Renamed to `sharded_dims_offsets` accordingly.
* First spmdization pattern for halo regions.
- Triggers when source and destination shardings differ only in their
halo sizes
- Copies local data from source into a new tensor and calls update_halo
- Supports arbitrary mesh dimensions (unlike the other patterns which
work on 1d meshes only)
* `UpdateHaloOp` implements `DestinationStyleOpInterface` and accepts
tensors and memrefs
- also accepts target and source halo sizes; both are required for
proper lowering
* minor refactoring for testing partial MeshSharding equality
* Canonicalization for ShardingOp folding constant values into
respective `static_*` attributes
Commit: 2eaf50716abae064804b9f9d27e157a98c83be2b
https://github.com/llvm/llvm-project/commit/2eaf50716abae064804b9f9d27e157a98c83be2b
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/jr-without-ra.ll
Log Message:
-----------
[LoongArch] Precommit test for avoid indirect branch jumps through ra. NFC
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/115423
Commit: 21ef17c626456496a18e2a078a11d8eccf26ee31
https://github.com/llvm/llvm-project/commit/21ef17c626456496a18e2a078a11d8eccf26ee31
Author: wanglei <wanglei at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
M llvm/test/CodeGen/LoongArch/jr-without-ra.ll
Log Message:
-----------
[LoongArch] Avoid indirect branch jumps using the ra register
Micro-architecture unconditionally treats a "jr $ra" as "return from
subroutine", hence doing "jr $ra" would interfere with both subroutine
return prediction and the more general indirect branch prediction.
GCC thread: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110136
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/115424
Commit: d8ebb08a89734478bc66341cb95559b00a05b0b5
https://github.com/llvm/llvm-project/commit/d8ebb08a89734478bc66341cb95559b00a05b0b5
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/test/Shell/Commands/command-disassemble-process.yaml
M lldb/test/Shell/Commands/command-disassemble.s
Log Message:
-----------
[lldb] Have disassembler show load addresses when using a core file (#115453)
We got a bug report that the disassember output was not relocated (i.e.
a load address) for a core file (like it is for a live process). It
turns out this behavior it depends on whether the instructions were read
from an executable file or from process memory (a core file will not
typically contain the memory image for segments backed by an executable
file).
It's unclear whether this behavior is intentional, or if it was just
trying to handle the case where we're dissassembling a module without a
process, but I think it's undesirable. What makes it particularly
confusing is that the instruction addresses are relocated in this case
(unlike the when we don't have a process), so with large files and
adresses it gets very hard to see whether the relocation has been
applied or not.
This patch removes the data_from_file check so that the instruction is
relocated regardless of where it was read from. It will still not get
relocated for the raw module use case, as those can't be relocated
anywhere as they don't have a load address.
Commit: eddb79d56dd50bc6832c7d906ab4a0df2ae1d846
https://github.com/llvm/llvm-project/commit/eddb79d56dd50bc6832c7d906ab4a0df2ae1d846
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxtf32intrin.h
A clang/lib/Headers/amxtf32transposeintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_tf32.c
A clang/test/CodeGen/X86/amx_tf32_api.c
A clang/test/CodeGen/X86/amx_tf32_errors.c
A clang/test/CodeGen/X86/amx_tf32_inline_asm.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx-tf32-internal.ll
A llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
A llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
A llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
A llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: b7db403e701029c801fd990dceeb219de9fb800c
https://github.com/llvm/llvm-project/commit/b7db403e701029c801fd990dceeb219de9fb800c
Author: Han Qi <my at rhanqtl.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/test/CodeGen/aarch64-pure-scalable-args.c
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/test/Transforms/CorrelatedValuePropagation/ashr.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll
M llvm/test/Transforms/CorrelatedValuePropagation/deopt.ll
M llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
M llvm/test/Transforms/CorrelatedValuePropagation/minmaxabs.ll
M llvm/test/Transforms/CorrelatedValuePropagation/overflow_predicate.ll
M llvm/test/Transforms/CorrelatedValuePropagation/range.ll
M llvm/test/Transforms/CorrelatedValuePropagation/sdiv.ll
M llvm/test/Transforms/CorrelatedValuePropagation/srem.ll
M llvm/test/Transforms/CorrelatedValuePropagation/udiv-expansion.ll
M llvm/test/Transforms/CorrelatedValuePropagation/urem-expansion.ll
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
Log Message:
-----------
[CVP] Add `samesign` flag to `icmp` (#115642)
Closes #114820.
Commit: 01a5596b5295d1585716d2deade407adaa40fe20
https://github.com/llvm/llvm-project/commit/01a5596b5295d1585716d2deade407adaa40fe20
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-10 (Sun, 10 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
Log Message:
-----------
[llvm-exegesis][X86] Groups ports 2,3, and 11 for Golden Cove (#115645)
This patch updates the PFM counter mappings for Sapphire Rapids and
Alder Lake (p-cores) to group ports 2,3, and 11 despite the naming of
the performance counters. This is how the scheduling models assume
things work within LLVM, and seems to be a mistake within the Intel
perfmon documentation.
Fixes #113941.
Commit: 40f52e849b63a18510e915236bce390ead9b4575
https://github.com/llvm/llvm-project/commit/40f52e849b63a18510e915236bce390ead9b4575
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port eddb79d56dd5
Commit: d893c5ad3560af5cd44d79f764ef879aefc671d7
https://github.com/llvm/llvm-project/commit/d893c5ad3560af5cd44d79f764ef879aefc671d7
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/docs/AMDGPUSupport.rst
M clang/docs/HIPSupport.rst
M clang/include/clang/Basic/MacroBuilder.h
M clang/lib/Basic/Targets/AMDGPU.cpp
A clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
Log Message:
-----------
[Clang][HIP] Reapply: Deprecate the AMDGCN_WAVEFRONT_SIZE macros (#115507)
So far, these macros can be used in contexts where no meaningful
wavefront size is available. We therefore deprecate these macros, to
replace them with a more resilient interface to access wavefront size
information where it is available.
Reapplies #112849 with a fix for the non-hermetic clang test that failed
on Mac after the revert in #115499.
For SWDEV-491529.
Commit: b9fb6b6cb52fd99f3136d8680a5cad5a10a7977c
https://github.com/llvm/llvm-project/commit/b9fb6b6cb52fd99f3136d8680a5cad5a10a7977c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115681)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: ebcdc700d68582a44dd059c40f382583126f29a6
https://github.com/llvm/llvm-project/commit/ebcdc700d68582a44dd059c40f382583126f29a6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
Log Message:
-----------
[lldb] Use heterogenous lookups with std::map (NFC) (#115684)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string. Note that CommandMap just
started accepting heterogeneous lookups (#115634).
Commit: d1aa0da7e28f70715bd92b2bc2809ac04a832aa8
https://github.com/llvm/llvm-project/commit/d1aa0da7e28f70715bd92b2bc2809ac04a832aa8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port for ffc7feadece139c88f0e6930f16bfa9293747adc
Commit: 2a448da6e63e2cd3dac63d5398bf121e994d7fc2
https://github.com/llvm/llvm-project/commit/2a448da6e63e2cd3dac63d5398bf121e994d7fc2
Author: Ingo Müller <ingomueller at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/lib/Bindings/Python/MainModule.cpp
M mlir/python/mlir/_mlir_libs/_mlir/__init__.pyi
Log Message:
-----------
[mlir][python] Make types in register_(dialect|operation) more narrow. (#115307)
This PR makes the `pyClass`/`dialectClass` arguments of the pybind11
functions `register_dialect` and `register_operation` as well as their
return types more narrow, concretely, a `py::type` instead of a
`py::object`. As the name of the arguments indicate, they have to be
called with a type instance (a "class"). The PR also updates the typing
stubs of these functions (in the corresponding `.pyi` file), such that
static type checkers are aware of the changed type. With the previous
typing information, `pyright` raised errors on code generated by
tablegen.
Signed-off-by: Ingo Müller <ingomueller at google.com>
Commit: 1277bea4311692d3bd3d1a6566ec1011d3e72f65
https://github.com/llvm/llvm-project/commit/1277bea4311692d3bd3d1a6566ec1011d3e72f65
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py
Log Message:
-----------
[lldb] Disable TestCancelAttach for Windows host (#115619)
See #115618 for details.
Commit: 75c2888209473884cb3fa5720899d8199dafb8cb
https://github.com/llvm/llvm-project/commit/75c2888209473884cb3fa5720899d8199dafb8cb
Author: Zhaoxin Yang <yangzhaoxin at loongson.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/test/CodeGen/LoongArch/e_flags.ll
Log Message:
-----------
[MC][LoongArch] Change default cpu in `MCSubtargetInfo`. (#114922)
The default value of this CPU affects the `FeatureBits` obtained by
`LoongArchTargetELFStreamer` when creating an ELF file, and it will
further affect the `Flags` field in the generated file.
So, the default CPU value should be consistent with the
`initializeSubtargetDependencies` in `LoongArchSubtarget.cpp`.
Otherwise, the `Flags` field may be unexpected.
Commit: aa15421b9ff67f362283657f74b2fa7314c25308
https://github.com/llvm/llvm-project/commit/aa15421b9ff67f362283657f74b2fa7314c25308
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86PfmCounters.td
Log Message:
-----------
[llvm-exegesis][X86] Update uop counter mappings for IceLake+
This patch updates the uop counter mappings for IceLake, AlderLake, and
SapphireRapids. The names of the counters were changed slightly between
these revisions for whatever reason. Validated by reading the libpfm4
source code and testing the exegesis binary with these changes on a
SapphireRapids system.
Commit: 34f8fbd269fc0d2d7d527d3661faea3eeb4587ac
https://github.com/llvm/llvm-project/commit/34f8fbd269fc0d2d7d527d3661faea3eeb4587ac
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
Log Message:
-----------
[Clang][AArch64] svadda is not available in streaming mode
And Clang should give a diagnostic when it is used in a streaming
context.
Commit: 44a6b3a4b69185d3cf0076ae3cad765a10205bc0
https://github.com/llvm/llvm-project/commit/44a6b3a4b69185d3cf0076ae3cad765a10205bc0
Author: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/depobj_codegen.cpp
Log Message:
-----------
Fix for codegen Crash in Clang when using locator omp_all_memory with depobj construct (#114221)
A codegen crash is occurring when a depend object was initialized with
omp_all_memory in the depobj directive.
https://github.com/llvm/llvm-project/issues/114214(url)
The root cause of issue looks to be the improper handling of the
dependency list when omp_all_memory was specified.
The change introduces the use of OMPTaskDataTy to manage dependencies.
The buildDependences function is called to construct the dependency
list, and the list is iterated over to emit and store the dependencies.
Reduced Test Case :
```
#include <omp.h>
int main()
{ omp_depend_t obj; #pragma omp depobj(obj) depend(inout: omp_all_memory) }
```
```
#1 0x0000000003de6623 SignalHandler(int) Signals.cpp:0:0
#2 0x00007f8e4a6b990f (/lib64/libpthread.so.0+0x1690f)
#3 0x00007f8e4a117d2a raise (/lib64/libc.so.6+0x4ad2a)
#4 0x00007f8e4a1193e4 abort (/lib64/libc.so.6+0x4c3e4)
#5 0x00007f8e4a10fc69 __assert_fail_base (/lib64/libc.so.6+0x42c69)
#6 0x00007f8e4a10fcf1 __assert_fail (/lib64/libc.so.6+0x42cf1)
#7 0x0000000004114367 clang::CodeGen::CodeGenFunction::EmitOMPDepobjDirective(clang::OMPDepobjDirective const&) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x4114367)
#8 0x00000000040f8fac clang::CodeGen::CodeGenFunction::EmitStmt(clang::Stmt const*, llvm::ArrayRef<clang::Attr const*>) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x40f8fac)
#9 0x00000000040ff4fb clang::CodeGen::CodeGenFunction::EmitCompoundStmtWithoutScope(clang::CompoundStmt const&, bool, clang::CodeGen::AggValueSlot) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x40ff4fb)
#10 0x00000000041847b2 clang::CodeGen::CodeGenFunction::EmitFunctionBody(clang::Stmt const*) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x41847b2)
#11 0x0000000004199e4a clang::CodeGen::CodeGenFunction::GenerateCode(clang::GlobalDecl, llvm::Function*, clang::CodeGen::CGFunctionInfo const&) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x4199e4a)
#12 0x00000000041f7b9d clang::CodeGen::CodeGenModule::EmitGlobalFunctionDefinition(clang::GlobalDecl, llvm::GlobalValue*) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x41f7b9d)
#13 0x00000000041f16a3 clang::CodeGen::CodeGenModule::EmitGlobalDefinition(clang::GlobalDecl, llvm::GlobalValue*) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x41f16a3)
#14 0x00000000041fd954 clang::CodeGen::CodeGenModule::EmitDeferred() (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x41fd954)
#15 0x0000000004200277 clang::CodeGen::CodeGenModule::Release() (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x4200277)
#16 0x00000000046b6a49 (anonymous namespace)::CodeGeneratorImpl::HandleTranslationUnit(clang::ASTContext&) ModuleBuilder.cpp:0:0
#17 0x00000000046b4cb6 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x46b4cb6)
#18 0x0000000006204d5c clang::ParseAST(clang::Sema&, bool, bool) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x6204d5c)
#19 0x000000000496b278 clang::FrontendAction::Execute() (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x496b278)
#20 0x00000000048dd074 clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x48dd074)
#21 0x0000000004a38092 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0x4a38092)
#22 0x0000000000fd4e9c cc1_main(llvm::ArrayRef<char const*>, char const*, void*) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0xfd4e9c)
#23 0x0000000000fcca73 ExecuteCC1Tool(llvm::SmallVectorImpl<char const*>&, llvm::ToolContext const&) driver.cpp:0:0
#24 0x0000000000fd140c clang_main(int, char**, llvm::ToolContext const&) (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0xfd140c)
#25 0x0000000000ee2ef3 main (/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/bin/clang-18+0xee2ef3)
#26 0x00007f8e4a10224c __libc_start_main (/lib64/libc.so.6+0x3524c)
#27 0x0000000000fcaae9 _start /home/abuild/rpmbuild/BUILD/glibc-2.31/csu/../sysdeps/x86_64/start.S:120:0
clang: error: unable to execute command: Aborted
```
---------
Co-authored-by: Chandra Ghale <ghale at pe31.hpc.amslabs.hpecorp.net>
Commit: 911cee2fd086524517588a7bc8cffb88091612b4
https://github.com/llvm/llvm-project/commit/911cee2fd086524517588a7bc8cffb88091612b4
Author: CHANDRA GHALE <chandra.nitdgp at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/Headers/openmp_wrappers/complex_cmath.h
Log Message:
-----------
Fix for OpenMP offloading compilation error with GNU++20 option when using complex header (#115306)
The change done is to fix this issue.
[[Issue](https://github.com/llvm/llvm-project/issues/113207)] discussion
available in link provided.
When using the -std=c++20 flag with -fopenmp for OpenMP offloading
results in the following compilation error.
Reduced test Case :
```
> cat foo.cpp
#include <complex>
void foo(){
}
> CC -fopenmp -std=gnu++20 -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a foo.cpp -c
In file included from foo.cpp:1:
In file included from /opt/cray/pe/cce/18.0.1/cce-clang/x86_64/lib/clang/18/include/openmp_wrappers/complex:51:
/opt/cray/pe/cce/18.0.1/cce-clang/x86_64/lib/clang/18/include/openmp_wrappers/complex_cmath.h:68:40: error: non-constexpr declaration of 'conj' follows constexpr declaration
68 | template <class _Tp> std::complex<_Tp> conj(const std::complex<_Tp> &__c) {
| ^
/usr/lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/complex:970:5: note: previous declaration is here
970 | conj(const complex<_Tp>& __z)
| ^
1 error generated.
```
Co-authored-by: Chandra Ghale <ghale at pe31.hpc.amslabs.hpecorp.net>
Commit: 69b39e7cc7ace46ebffd8077820b29fe0768b5d9
https://github.com/llvm/llvm-project/commit/69b39e7cc7ace46ebffd8077820b29fe0768b5d9
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/sve-hadd.ll
Log Message:
-----------
[SelectionDAG] Add support for extending masked loads in computeKnownBits (#115450)
We already support computing known bits for extending loads, but not for
masked loads. For now I've only added support for zero-extends because
that's the only thing currently tested. Even when the passthru value is
poison we still know the top X bits are zero.
Commit: a4e507df7a07f234350669395d3521ed343a06ea
https://github.com/llvm/llvm-project/commit/a4e507df7a07f234350669395d3521ed343a06ea
Author: David Green <david.green at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Log Message:
-----------
[AArch64][GlobalISel] Do not create LIFETIME instructions in functions. (#115669)
For the same reason that we do not translate lifetime markers in a -O0,
we should not translate them for optnone functions too.
Commit: a5d09f4ad94fab718e787fb6dce7933e7742eb1b
https://github.com/llvm/llvm-project/commit/a5d09f4ad94fab718e787fb6dce7933e7742eb1b
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/MachineVerifier/test_step-vector.mir
Log Message:
-----------
[GlobalISel] Add G_STEP_VECTOR instruction (#115598)
aka llvm.stepvector Intrinsic
Commit: 04b295e8938778251821f8a39903fdad0501112c
https://github.com/llvm/llvm-project/commit/04b295e8938778251821f8a39903fdad0501112c
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
Log Message:
-----------
[lldb][ObjC] Fix method list entry offset calculation (#115571)
The `relative_list_list_entry_t` offset field in the Objective-C runtime
is of type `int64_t`. There are cases where these offsets are negative
values. For negative offsets, LLDB would currently incorrectly
zero-extend the offset (dropping the fact that the offset was negative),
instead producing large offsets that, when added to the
`m_baseMethods_ptr` result in addresses that had their upper bits set
(e.g., `0x00017ff81b3241b0`). We then would try to `GetMethodList` from
such an address but fail to read it (because it's an invalid address).
This would manifest in Objective-C decls not getting completed correctly
(and formatters not working). We noticed this in CI failures on our
Intel bots. This happened to work fine on arm64 because we strip the
upper bits when calling `ClassDescriptorV2::method_list_t::Read` using
the `FixCodeAddress` ABI plugin API (which doesn't do that on Intel).
The fix is to sign-extend the offset calculation.
Example failure before this patch:
```
======================================================================
FAIL: test_break_dwarf (TestRuntimeTypes.RuntimeTypesTestCase)
Test setting objc breakpoints using '_regexp-break' and 'breakpoint set'.
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/michaelbuch/Git/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/michaelbuch/Git/llvm-project/lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py", line 48, in test_break
self.expect(
File "/Users/michaelbuch/Git/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 2370, in expect
self.runCmd(
File "/Users/michaelbuch/Git/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1000, in runCmd
self.assertTrue(self.res.Succeeded(), msg + output)
AssertionError: False is not true : Got a valid type
Error output:
error: <user expression 1>:1:11: no known method '+stringWithCString:encoding:'; cast the message send to the method's return type
1 | [NSString stringWithCString:"foo" encoding:1]
| ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Config=x86_64-/Users/michaelbuch/Git/lldb-build-main-no-modules/bin/clang
---------------------------------------------------------------------- ```
Commit: 00a1f1ab71302d190f8059d86a53ec62485fbce9
https://github.com/llvm/llvm-project/commit/00a1f1ab71302d190f8059d86a53ec62485fbce9
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/test/Dialect/MemRef/ops.mlir
M mlir/test/IR/core-ops.mlir
R mlir/test/IR/memory-ops.mlir
Log Message:
-----------
[MLIR] NFC. Move leftover memref op test cases out of test/IR (#115583)
Move memref dialect ops' test cases of test/IR/. It was also surprising
to not find test cases of ops like memref.view in test/Dialect/MemRef/.
NFC.
Commit: b91b6235dee3be69b429cace319ff39f1eadfe14
https://github.com/llvm/llvm-project/commit/b91b6235dee3be69b429cace319ff39f1eadfe14
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Mesh/IR/CMakeLists.txt
Log Message:
-----------
adding missing lib MLIRDestinationStyleOpInterface (#115703)
fixing CI failures caused by #114238 by adding
MLIRDestinationStyleOpInterface lib
@jplehr @mfrancio @rengolin
Commit: 8f9dbb0a780feed60416ebc6ef8e89f4b0c2dca7
https://github.com/llvm/llvm-project/commit/8f9dbb0a780feed60416ebc6ef8e89f4b0c2dca7
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/implicit-dsa.f90
M flang/test/Lower/OpenMP/statement-function.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/OpenMP/task2.f90
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
Log Message:
-----------
[flang][OpenMP] delayed privatisation lowering for TASK (#113591)
Commit: 6dc23b70097e4135ecde33f49550b1f473a5c385
https://github.com/llvm/llvm-project/commit/6dc23b70097e4135ecde33f49550b1f473a5c385
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/LoopStrengthReduce/Power/incomplete-phi.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
Log Message:
-----------
[SCEVExpander] Don't try to reuse SCEVUnknown values (#115141)
The expansion of a SCEVUnknown is trivial (it's just the wrapped value).
If we try to reuse an existing value it might be a more complex
expression that simplifies to the SCEVUnknown.
This is inspired by https://github.com/llvm/llvm-project/issues/114879,
because SCEVExpander replacing a constant with a phi node is just silly.
(I don't consider this a fix for that issue though.)
Commit: 6ad1dd3bdcc8f9bfdf9f6074c8dffe0675a2e4cf
https://github.com/llvm/llvm-project/commit/6ad1dd3bdcc8f9bfdf9f6074c8dffe0675a2e4cf
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/load-cmp.ll
A llvm/test/Transforms/InstCombine/sext-and.ll
Log Message:
-----------
[InstCombine] Fold (sext(a) & c1) == c2 to (a & c3) == trunc(c2) (#112646)
Fixes https://github.com/llvm/llvm-project/issues/85830.
Updated Alive proof: https://alive2.llvm.org/ce/z/KnvoP5
Commit: 7c3bbfdcf62e0a8806e3ae3130e8dc537fe5c775
https://github.com/llvm/llvm-project/commit/7c3bbfdcf62e0a8806e3ae3130e8dc537fe5c775
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/pr40730.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
Log Message:
-----------
[X86] lowerShuffleAsLanePermuteAndPermute - simplify lane crossing mask based on demanded elts
Don't demand every element of each demanded sublane - set the undemanded mask elements to UNDEF to allow simplification (usually to a VBROADCAST).
Fixes #66150
Commit: a7b249e4708d61e491390773d3bb1ee88db91a57
https://github.com/llvm/llvm-project/commit/a7b249e4708d61e491390773d3bb1ee88db91a57
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/include/llvm/ADT/STLFunctionalExtras.h
Log Message:
-----------
Reland "Add clang::lifetimebound annotation to llvm::function_ref"
This relands 9f79615, which was reverted in e109c49. The compiler-rt breakage is fixed.
Commit: c315c01a7ea92b562f8b63159e113abaf0b50e5a
https://github.com/llvm/llvm-project/commit/c315c01a7ea92b562f8b63159e113abaf0b50e5a
Author: Matthias Springer <me at m-sp.org>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/Transforms/Passes.h
M mlir/test/Transforms/cse.mlir
Log Message:
-----------
[mlir][Transforms][NFC] CSE: Split tests and fix typo (#115680)
Add `-split-input-file` to CSE tests and fix a typo in `Passes.h`. (The
typo is harmless as long as the pass has no options.)
Commit: 1ca64c5fb74270661ca2f9ebd821f47dcb3152b4
https://github.com/llvm/llvm-project/commit/1ca64c5fb74270661ca2f9ebd821f47dcb3152b4
Author: Lee Wei <lee10202013 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/Transforms/CodeGenPrepare/X86/2008-11-24-RAUW-Self.ll
M llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
M llvm/test/Transforms/ConstantHoisting/AArch64/consthoist-unreachable.ll
M llvm/test/Transforms/ConstantHoisting/ARM/same-offset-multi-types.ll
M llvm/test/Transforms/ConstantHoisting/PowerPC/masks.ll
M llvm/test/Transforms/ConstantHoisting/X86/pr43903-not-all-uses-rebased.ll
M llvm/test/Transforms/Coroutines/coro-async-remat.ll
M llvm/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/crash.ll
M llvm/test/Transforms/CorrelatedValuePropagation/pr35807.ll
M llvm/test/Transforms/DeadStoreElimination/overlap.ll
M llvm/test/Transforms/DeadStoreElimination/simple.ll
M llvm/test/Transforms/EarlyCSE/X86/preserve_memoryssa.ll
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionSpecialization/bug55000-read-uninitialized-value.ll
M llvm/test/Transforms/IRCE/pr57335.ll
Log Message:
-----------
[llvm] Remove `br i1 undef` from some regression tests [NFC] (#115691)
This PR aims to remove undefined behavior from tests under the directory
`llvm/transforms/CodegenPrepare, ConstantHoisting, Coroutines` etc.
Commit: 5e7662efec36b0117cfdf85c0182e026e0019c4e
https://github.com/llvm/llvm-project/commit/5e7662efec36b0117cfdf85c0182e026e0019c4e
Author: Carlos Alberto Enciso <Carlos.Enciso at sony.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
Log Message:
-----------
[llvm-debuginfo-analyzer] Incorrect DW_AT_call_line/DW_AT_call_file. (#115701)
The code dealing with DW_AT_call_line/DW_AT_call_file is in the wrong
place. The correct functions were call, but with incorrect values:
DW_AT_call_line <-- Filename Index
DW_AT_call_file <-- Line number
Commit: 89aaf2cf68d00e86dfd102a449fc68ff7ea5c85c
https://github.com/llvm/llvm-project/commit/89aaf2cf68d00e86dfd102a449fc68ff7ea5c85c
Author: lfrenot <leon.frenot at ens-lyon.fr>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Target/LLVMIR/Import/nneg.ll
A mlir/test/Target/LLVMIR/nneg.mlir
Log Message:
-----------
[mlir][LLVM] Add nneg flag (#115498)
This implementation is based on the existing one for the exact flag.
If the nneg flag is set and the argument is negative, the result is a
poison value.
Commit: bc368e4b578730bf0b10acd5412e476ccf7a5807
https://github.com/llvm/llvm-project/commit/bc368e4b578730bf0b10acd5412e476ccf7a5807
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
Log Message:
-----------
[lldb][test] TestConstStaticIntegralMember.py: skip dsym variant for older compiler versions
The existing XFAIL was being ignored because of the `expectedFailureDarwin`
causing failures on the matrix macOS bot:
```
======================================================================
FAIL: test_inline_static_members_dwarf5_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 151, in test_inline_static_members_dwarf5
self.check_inline_static_members("-gdwarf-5")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 129, in check_inline_static_members
self.check_global_var("A::int_val", "const int", "1")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
Config=x86_64-/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/clang_1501_build/bin/clang
======================================================================
FAIL: test_shadowed_static_inline_members_dwarf5_dsym (TestConstStaticIntegralMember.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/packages/Python/lldbsuite/test/lldbtest.py", line 1769, in test_method
return attrvalue(self)
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 205, in test_shadowed_static_inline_members_dwarf5
self.check_shadowed_static_inline_members("-gdwarf-5")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 192, in check_shadowed_static_inline_members
self.check_global_var("ns::Foo::mem", "const int", "10")
File "/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/llvm-project/lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py", line 118, in check_global_var
self.assertGreaterEqual(len(var_list), 1)
AssertionError: 0 not greater than or equal to 1
Config=x86_64-/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/clang_1501_build/bin/clang
----------------------------------------------------------------------
```
Commit: 60641b0aae4ebf966285ac95e381c5709a83d1ac
https://github.com/llvm/llvm-project/commit/60641b0aae4ebf966285ac95e381c5709a83d1ac
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
Log Message:
-----------
[LLVM][SVE] Extend dup(extract_elt(v,i)) isel patterns to cover more combinations. (#115189)
Adds missing bfloat patterns for unpacked scalable vectors.
Adds patterns for splatting extracts from fixed length vectors.
Commit: 5ea852ebafea9f29d34ed380066ee4f2fcf366ec
https://github.com/llvm/llvm-project/commit/5ea852ebafea9f29d34ed380066ee4f2fcf366ec
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
Log Message:
-----------
[X86] Add test coverage for #114001
Commit: 8941f898f1921857720034b9a0950e4ec32d5d87
https://github.com/llvm/llvm-project/commit/8941f898f1921857720034b9a0950e4ec32d5d87
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/test/API/lit.cfg.py
Log Message:
-----------
[lldb] Transfer some environment variables into the tests on Windows build host (#115613)
Some API tests (compiler calls) create a lot of garbage and cause
unexpected behavior in case of Windows host and Linux target, e.g.
```
lldb/test/API/commands/process/attach/%SystemDrive%/
lldb/test/API/functionalities/deleted-executable/%SystemDrive%/
lldb/test/API/functionalities/exec/%SystemDrive%/
lldb/test/API/functionalities/load_unload/%SystemDrive%/
lldb/test/API/functionalities/target-new-solib-notifications/%SystemDrive%/
lldb/test/API/functionalities/thread/create_after_attach/%SystemDrive%/
```
It can be fixed by transfer some standard Windows environment variables
into API tests.
Commit: f87737f3fdb6b2a7fa0d7b9c245eab0c39e6fb50
https://github.com/llvm/llvm-project/commit/f87737f3fdb6b2a7fa0d7b9c245eab0c39e6fb50
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Parser/OpenMP/depobj-construct.f90
A flang/test/Parser/OpenMP/doacross-clause.f90
A flang/test/Parser/OpenMP/ordered-depend.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend06.f90
M flang/test/Semantics/OpenMP/depobj-construct-v50.f90
M flang/test/Semantics/OpenMP/depobj-construct-v51.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
M flang/test/Semantics/OpenMP/ordered01.f90
M flang/test/Semantics/OpenMP/ordered03.f90
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Parse DOACROSS clause (#115396)
Extract the SINK/SOURCE parse tree elements into a separate class
`OmpDoacross`, share them between DEPEND and DOACROSS clauses. Most of
the changes in Semantics are to accommodate the new contents of
OmpDependClause, and a mere introduction of OmpDoacrossClause.
There are no semantic checks specifically for DOACROSS.
Commit: 30feb35c1ebc6f09d85df814f8aac57e8eb6fcc2
https://github.com/llvm/llvm-project/commit/30feb35c1ebc6f09d85df814f8aac57e8eb6fcc2
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__cxx03/CMakeLists.txt
M libcxx/utils/libcxx/header_information.py
Log Message:
-----------
[libc++] Update CMake dependency for generate_iwyu_mapping.py (#115387)
This script does not depend on the generated headers since those are
already special-cased in header_information.py. Change the dependency
list to depend on header_information.py instead. While looking at this
code also simplify the assignment to libcxx_root inside this script.
Commit: 3af4c2e16ec1cf8a099d69d69f40f3aa8bb43cc7
https://github.com/llvm/llvm-project/commit/3af4c2e16ec1cf8a099d69d69f40f3aa8bb43cc7
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/test/benchmarks/GenerateInput.h
Log Message:
-----------
[libc++][test] Clean up code in GenerateInput.h for benchmark testing (#115560)
This PR refines the code in `GenerateInput.h` used for benchmark testing
by implementing the following changes:
- Replaced all unqualified usages of `size_t` with `std::size_t`.
- Removed unnecessary curly braces `{}` from for loops that contain
simple single-statement bodies, in accordance with LLVM coding
standards.
Commit: 9f471fd12b9e2d6264f27974feaf893445e92393
https://github.com/llvm/llvm-project/commit/9f471fd12b9e2d6264f27974feaf893445e92393
Author: A. Jiang <de34 at live.cn>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
M libcxx/include/__iterator/wrap_iter.h
A libcxx/test/libcxx/iterators/contiguous_iterators.conv.compile.pass.cpp
Log Message:
-----------
[libc++][hardening] Constrain construction for `__{(static_)bounded,wrap}_iter` (#115271)
This PR restricts construction to cases where reference types of
source/destination iterators are (`T&`, `T&`) or (`T&`, `const T&`) (
where `T` can be const).
Fixes #50058.
Commit: 4988376f76be755929fc017a27158e8b91fafb9c
https://github.com/llvm/llvm-project/commit/4988376f76be755929fc017a27158e8b91fafb9c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
Log Message:
-----------
[X86] Add test coverage for #113396
Commit: 4c4db3c943d686ff7c1fcf2dbc975e8462497efe
https://github.com/llvm/llvm-project/commit/4c4db3c943d686ff7c1fcf2dbc975e8462497efe
Author: ziereis <44057120+ziereis at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir
Log Message:
-----------
add pattern for arith::UIToFPOp to VectorNarrowTypeRewritePatterns (#115485)
This pr just adds the patterns from
https://github.com/llvm/llvm-project/pull/89131 for the arith::UIToFPOp.
Also does some slight renaming and moving of the tests for better
readability.
Commit: 173529104d598785c2f8c36c047a6d0f1d0f060e
https://github.com/llvm/llvm-project/commit/173529104d598785c2f8c36c047a6d0f1d0f060e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/utils/TableGen/NeonEmitter.cpp
Log Message:
-----------
[TableGen] Use heterogenous lookups with std::map (NFC) (#115682)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
Commit: a41922ad7530ef5e311afbff2721e69cbf520890
https://github.com/llvm/llvm-project/commit/a41922ad7530ef5e311afbff2721e69cbf520890
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
M llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
M llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
Log Message:
-----------
[AArch64] Remove unused includes (NFC) (#115685)
Identified with misc-include-cleaner.
Commit: 3fcb9684cf6ba4ff9009ebabd9ff966eeb8b15f7
https://github.com/llvm/llvm-project/commit/3fcb9684cf6ba4ff9009ebabd9ff966eeb8b15f7
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstSimplify/cmp-alloca-offsets.ll
Log Message:
-----------
[InstSimplify] Add tests for comparison with zero-sized allocs (NFC)
Commit: 4981f8cb72ea7d04da601c868763b38bdc11e74e
https://github.com/llvm/llvm-project/commit/4981f8cb72ea7d04da601c868763b38bdc11e74e
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
Log Message:
-----------
[PowerPC] Fix vector_shuffle combines when inputs are scalar_to_vector of differing types. (#80784)
This patch fixes the combines for vector_shuffles when either or both of
its left and right hand side inputs are scalar_to_vector nodes.
Previously, when both left and right side inputs are scalar_to_vector
nodes, the current combine could not handle this situation, as the shuffle
mask was updated incorrectly. To temporarily solve this solution, this combine
was simply disabled and not performed.
Now, not only does this patch aim to resolve the previous issue of the
incorrect shuffle mask adjustments respectively, but it also updates any test
cases that are affected by this change.
Patch migrated from https://reviews.llvm.org/D130487.
Commit: 3338186d463b32a3bababaa345da861d93c83152
https://github.com/llvm/llvm-project/commit/3338186d463b32a3bababaa345da861d93c83152
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/canonicalize.mlir
Log Message:
-----------
[mlir][affine] Remove one-element linearize_index as a canonicalization (#115542)
By analogy to the canonicalization for affine.delinearize_index, remove
affine.linearize_index ops that only have one multi-index input.
Example:
Canonicalize
```mlir
%1 = affine.linearize_index [%0] by (64)
```
to
```mlir
%1 = %0
```
While I'm here, get rid of an extra space in the syntax.
Commit: b08b252a023eeead07b3e77ce799c3a7d783a0b3
https://github.com/llvm/llvm-project/commit/b08b252a023eeead07b3e77ce799c3a7d783a0b3
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenMP/Todo/ordered.f90
A flang/test/Semantics/OpenMP/doacross.f90
M flang/test/Semantics/OpenMP/ordered01.f90
M flang/test/Semantics/OpenMP/ordered03.f90
Log Message:
-----------
[flang][OpenMP] Semantic checks for DOACROSS clause (#115397)
Keep track of loop constructs and OpenMP loop constructs that have been
entered. Use the information to validate the variables in the SINK loop
iteration vector.
---------
Co-authored-by: Tom Eccles <tom.eccles at arm.com>
Commit: e19d74016971faed321e5cca20da7016047eb029
https://github.com/llvm/llvm-project/commit/e19d74016971faed321e5cca20da7016047eb029
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/CMakeLists.txt
M lldb/cmake/modules/FindLuaAndSwig.cmake
M lldb/docs/resources/build.rst
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/API/lldbtest.py
M lldb/test/API/lua_api/TestLuaAPI.py
Log Message:
-----------
[lldb] Support both Lua 5.3 and Lua 5.4 (#115500)
Lua 5.3 and Lua 5.4 are similar enough that we can easily support both
in LLDB. This patch adds support for building LLDB with both and updates
the documentation accordingly.
Commit: bf601ba3322dd908ee9290af7f0d9bafa051a734
https://github.com/llvm/llvm-project/commit/bf601ba3322dd908ee9290af7f0d9bafa051a734
Author: lfrenot <leon.frenot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/nsw_nuw.ll
M mlir/test/Target/LLVMIR/nsw_nuw.mlir
Log Message:
-----------
[mlir][LLVM] Add nsw and nuw flags to trunc (#115509)
This implementation is based on the one already existing for the binary
operations.
If the nuw keyword is present, and any of the truncated bits are
non-zero, the result is a poison value. If the nsw keyword is present,
and any of the truncated bits are not the same as the top bit of the
truncation result, the result is a poison value.
Commit: 4a68e4cbd2423dcacada8162ab7c4bb8d7f7e2cf
https://github.com/llvm/llvm-project/commit/4a68e4cbd2423dcacada8162ab7c4bb8d7f7e2cf
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/include/string
A libcxx/test/libcxx/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
Log Message:
-----------
[libc++] Fix throwing away smaller allocations in string::shrink_to_fit (#115659)
Currently `string::shrink_to_fit()` throws away any allocations which
return more capacity than we requested, even if that allocation is still
smaller than the current capacity. This patch fixes this to compare the
returned allocation against the current capacity of the string instead
of against the requested capacity.
Commit: 8c4331c1abeb33eabf3cdbefa7f2b6e0540e7f4f
https://github.com/llvm/llvm-project/commit/8c4331c1abeb33eabf3cdbefa7f2b6e0540e7f4f
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/AST/attr-lifetime-capture-by.cpp
A clang/test/SemaCXX/attr-lifetime-capture-by.cpp
Log Message:
-----------
[clang] Introduce [[clang::lifetime_capture_by(X)]] (#111499)
This implements the RFC
https://discourse.llvm.org/t/rfc-introduce-clang-lifetime-capture-by-x/81371
In this PR, we introduce `[[clang::lifetime_capture_by(X)]]` attribute
as discussed in the RFC.
As an implementation detail of this attribute, we store and use param
indices instead of raw param expressions. The parameter indices are
computed lazily at the end of function declaration since the function
decl (and therefore the subsequent parameters) are not visible yet while
parsing a parameter annotation.
In subsequent PR, we will infer this attribute for STL containers and
perform lifetime analysis to detect dangling cases.
Commit: 6c3d374d12bf04f8d4b24c093067d82746260292
https://github.com/llvm/llvm-project/commit/6c3d374d12bf04f8d4b24c093067d82746260292
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
Log Message:
-----------
[X86] vector-shuffle-v1.ll - regenerate test checks with vpternlog comments
Commit: 3ce544e6be098b5c355140de78bc49069fda33c3
https://github.com/llvm/llvm-project/commit/3ce544e6be098b5c355140de78bc49069fda33c3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/matrix-multiply.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
Log Message:
-----------
[X86] lowerShuffleAsBroadcast - improve handling of non-zero element index broadcasts
On AVX2+, support broadcasting of any element if it occurs in the bottom 128-bit subvector by shuffling the element down to element 0 and then broadcasting.
Fixes #113396
Commit: f895fc9550a207decc4b93dffb9d86ec8ac24985
https://github.com/llvm/llvm-project/commit/f895fc9550a207decc4b93dffb9d86ec8ac24985
Author: Lei Huang <lei at ca.ibm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
Log Message:
-----------
[NFC][PowerPC] Add getScalarIntVT to return MVT based on arch (#115203)
Add `getScalarIntVT()` to return scalar int VT based on if arch is 32 or
64bit.
Commit: 9d4837f47c48c634d4a0ac799188e1f5332495ef
https://github.com/llvm/llvm-project/commit/9d4837f47c48c634d4a0ac799188e1f5332495ef
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/test/ClangScanDeps/diagnostics.c
M clang/test/ClangScanDeps/header-search-pruning-transitive.c
M clang/test/ClangScanDeps/link-libraries.c
M clang/test/ClangScanDeps/modules-context-hash.c
M clang/test/ClangScanDeps/modules-dep-args.c
M clang/test/ClangScanDeps/modules-extern-submodule.c
M clang/test/ClangScanDeps/modules-extern-unrelated.m
M clang/test/ClangScanDeps/modules-file-path-isolation.c
M clang/test/ClangScanDeps/modules-fmodule-name-no-module-built.m
M clang/test/ClangScanDeps/modules-full-by-mod-name.c
M clang/test/ClangScanDeps/modules-full.cpp
M clang/test/ClangScanDeps/modules-implicit-dot-private.m
M clang/test/ClangScanDeps/modules-incomplete-umbrella.c
M clang/test/ClangScanDeps/modules-inferred.m
M clang/test/ClangScanDeps/modules-no-undeclared-includes.c
M clang/test/ClangScanDeps/modules-pch-common-submodule.c
M clang/test/ClangScanDeps/modules-pch-common-via-submodule.c
M clang/test/ClangScanDeps/modules-pch.c
M clang/test/ClangScanDeps/modules-priv-fw-from-pub.m
M clang/test/ClangScanDeps/modules-redefinition.m
M clang/test/ClangScanDeps/modules-symlink-dir-vfs.c
M clang/test/ClangScanDeps/modules-transitive.c
M clang/test/ClangScanDeps/optimize-vfs.m
M clang/test/ClangScanDeps/removed-args.c
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang][deps][modules] Allocate input file paths lazily (#114457)
This PR builds on top of #113984 and attempts to avoid allocating input
file paths eagerly. Instead, the `InputFileInfo` type used by
`ASTReader` now only holds `StringRef`s that point into the PCM file
buffer, and the full input file paths get resolved on demand.
The dependency scanner makes use of this in a bit of a roundabout way:
`ModuleDeps` now only holds (an owning copy of) the short unresolved
input file paths, which get resolved lazily. This can be a big win, I'm
seeing up to a 5% speedup.
Commit: 396ed9c2a12daffdb0349c850beb59e891e2a42b
https://github.com/llvm/llvm-project/commit/396ed9c2a12daffdb0349c850beb59e891e2a42b
Author: Duncan <duncpro at icloud.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/arm/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/libc_search.rst
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__lsearchcompare_t.h
M libc/newhdrgen/yaml/search.yaml
M libc/spec/posix.td
M libc/src/search/CMakeLists.txt
A libc/src/search/lfind.cpp
A libc/src/search/lfind.h
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/lfind_test.cpp
Log Message:
-----------
[libc][search] implement posix `lfind` function (#114692)
# Changes
- Implement the POSIX
[`lfind`](https://man7.org/linux/man-pages/man3/lsearch.3.html)
function.
- Put a checkmark in the [posix support table
docs](https://libc.llvm.org/libc_search.html) next to `lfind`.
Commit: c11b6e80b6121ebbec6fdc32e51938b6a13ef104
https://github.com/llvm/llvm-project/commit/c11b6e80b6121ebbec6fdc32e51938b6a13ef104
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/stdfix-types.h
M libc/newhdrgen/yaml/stdfix.yaml
M libc/spec/stdc_ext.td
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/hkbits.cpp
A libc/src/stdfix/hkbits.h
A libc/src/stdfix/hrbits.cpp
A libc/src/stdfix/hrbits.h
A libc/src/stdfix/kbits.cpp
A libc/src/stdfix/kbits.h
A libc/src/stdfix/lkbits.cpp
A libc/src/stdfix/lkbits.h
A libc/src/stdfix/lrbits.cpp
A libc/src/stdfix/lrbits.h
A libc/src/stdfix/rbits.cpp
A libc/src/stdfix/rbits.h
A libc/src/stdfix/uhkbits.cpp
A libc/src/stdfix/uhkbits.h
A libc/src/stdfix/uhrbits.cpp
A libc/src/stdfix/uhrbits.h
A libc/src/stdfix/ukbits.cpp
A libc/src/stdfix/ukbits.h
A libc/src/stdfix/ulkbits.cpp
A libc/src/stdfix/ulkbits.h
A libc/src/stdfix/ulrbits.cpp
A libc/src/stdfix/ulrbits.h
A libc/src/stdfix/urbits.cpp
A libc/src/stdfix/urbits.h
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/FxBitsTest.h
A libc/test/src/stdfix/hkbits_test.cpp
A libc/test/src/stdfix/hrbits_test.cpp
A libc/test/src/stdfix/kbits_test.cpp
A libc/test/src/stdfix/lkbits_test.cpp
A libc/test/src/stdfix/lrbits_test.cpp
A libc/test/src/stdfix/rbits_test.cpp
A libc/test/src/stdfix/uhkbits_test.cpp
A libc/test/src/stdfix/uhrbits_test.cpp
A libc/test/src/stdfix/ukbits_test.cpp
A libc/test/src/stdfix/ulkbits_test.cpp
A libc/test/src/stdfix/ulrbits_test.cpp
A libc/test/src/stdfix/urbits_test.cpp
Log Message:
-----------
[libc][stdfix] Implement fixed point fxbits functions in llvm-libc (#114912)
Commit: a2171d7f0e2366ea5017c70673ce9b4e8be97f09
https://github.com/llvm/llvm-project/commit/a2171d7f0e2366ea5017c70673ce9b4e8be97f09
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
[GISel][AArch64][RISCV] Don't call markAllIdxsAsCovered from minScalarSameAs/maxScalarSameAs. (#115637)
The predicate isn't user defined so we don't need to call
markAllIdxsAsCovered. Call actionIf instead of
widenScalarIf/narrowScalarIf.
Commit: 8366be73de39c446961fa56828390ad3438f8bc7
https://github.com/llvm/llvm-project/commit/8366be73de39c446961fa56828390ad3438f8bc7
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/spec/stdc_ext.td
Log Message:
-----------
[libc] fix typo and trailing whitespace
Fixes #114912
Commit: 2778af9a70bd4b4365bba2d20d50568f7ee3d18f
https://github.com/llvm/llvm-project/commit/2778af9a70bd4b4365bba2d20d50568f7ee3d18f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang] Fix warnings
This patch fixes:
flang/lib/Semantics/check-omp-structure.cpp:979:24: error: unused
variable 'top' [-Werror,-Wunused-variable]
flang/lib/Semantics/check-omp-structure.cpp:4441:24: error: unused
variable 'top' [-Werror,-Wunused-variable]
Commit: 11cc826c0a5802b03c85aa271b6fd16214f8f4d8
https://github.com/llvm/llvm-project/commit/11cc826c0a5802b03c85aa271b6fd16214f8f4d8
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amdgpuintrin.h
A clang/lib/Headers/gpuintrin.h
A clang/lib/Headers/nvptxintrin.h
A clang/test/Headers/gpuintrin.c
A clang/test/Headers/gpuintrin_lang.c
Log Message:
-----------
[Clang] Implement resource directory headers for common GPU intrinsics (#110179)
Summary:
All GPU based languages provide some way to access things like the
thread ID or other resources. However, this is spread between many
different languages and it varies between targets. The goal here is to
provide a resource directory header that just provides these in an
easier to understand way, primarily so this can be used for C/C++ code.
The interface aims to be common, to faciliate easier porting, but target
specific stuff could be put in the individual headers.
Commit: 9c3a7ad7faab0e172d08e5873b88141ab9866985
https://github.com/llvm/llvm-project/commit/9c3a7ad7faab0e172d08e5873b88141ab9866985
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/apple.h
R libcxx/include/__locale_dir/locale_base_api/freebsd.h
A libcxx/include/__locale_dir/support/apple.h
A libcxx/include/__locale_dir/support/bsd_like.h
A libcxx/include/__locale_dir/support/freebsd.h
M libcxx/include/iomanip
M libcxx/include/module.modulemap
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.assign/member_swap.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.assign/move_assign.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.cons/move.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.cons/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/bool.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/double.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/float.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/int.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long_double.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/short.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_int.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_long_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_short.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/signed_char.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/signed_char_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/unsigned_char.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/unsigned_char_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/wchar_t_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.manip/ws.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_pointer_size.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_pointer_size_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/getline_pointer_size.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/getline_pointer_size_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/ignore.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/peek.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/putback.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/read.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/readsome.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/seekg.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/seekg_off.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/sync.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/tellg.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/unget.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.assign/member_swap.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.assign/move_assign.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.cons/move.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.cons/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream_sentry/ctor.pass.cpp
Log Message:
-----------
[libc++] Cleanly implement the base locale API for BSD-like platforms (#115176)
Instead of going through the old locale entry points, define the base
localization API for BSD-like platforms (Apple and FreeBSD) from
scratch, using <xlocale.h> as a basis. This doesn't actually change how
that functionality is implemented, it only avoids going through a maze
to do so.
This clean new support is implemented in a separate __locale_dir/support
directory, which mirrors what we do for the threading support API.
Eventually, everything under __locale_dir/locale_base_api will go away.
rdar://131476632
Commit: 87605b1fbafa7e8fcb1aac057a47886f3be0daa3
https://github.com/llvm/llvm-project/commit/87605b1fbafa7e8fcb1aac057a47886f3be0daa3
Author: Nico Weber <thakis at chromium.org>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn] Port e19d74016971f
Commit: 0b07aaec38eaae0885c6f05b4bb1ef62cc3fe004
https://github.com/llvm/llvm-project/commit/0b07aaec38eaae0885c6f05b4bb1ef62cc3fe004
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/spec/stdc_ext.td
Log Message:
-----------
[libc] fix missing trailing commas
Fixes: #114912
Commit: 7c6d809dfc41e2f2de86b88f0ca14be4af432cd7
https://github.com/llvm/llvm-project/commit/7c6d809dfc41e2f2de86b88f0ca14be4af432cd7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port 11cc826c0a58
Commit: e8fe895df12cfc2da6e584d893e12970f9d443eb
https://github.com/llvm/llvm-project/commit/e8fe895df12cfc2da6e584d893e12970f9d443eb
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 9c3a7ad7faab
Commit: da78ac5d331953d3386fd56cd7979022be7400cf
https://github.com/llvm/llvm-project/commit/da78ac5d331953d3386fd56cd7979022be7400cf
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/test/Headers/gpuintrin_lang.c
Log Message:
-----------
[Clang] Fix GPU intrinsics test on different range metadata
Summary:
For some reason, a few compilers do not emit the range metadata which
makes this test fail. I can't reproduce it locally so hopefully removing
that will ecourage it to fix.
Commit: 058ac837bc35419bbbb34f3206f5aa229c669811
https://github.com/llvm/llvm-project/commit/058ac837bc35419bbbb34f3206f5aa229c669811
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
Log Message:
-----------
[SLP]Use generic createShuffle for buildvector
Use generic createShuffle function, which know how to adjust the vectors
correctly, to avoid compiler crash when trying to build a buildvector as
a shuffle
Fixes #115732
Commit: a2f9d1d078cefc3ee7b19610f7117d1fb1369f18
https://github.com/llvm/llvm-project/commit/a2f9d1d078cefc3ee7b19610f7117d1fb1369f18
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/GeneratePCH.cpp
Log Message:
-----------
[clang][serialization] Enable `ASTWriter` to work with `Preprocessor` only (#115237)
This PR builds on top of
https://github.com/llvm/llvm-project/pull/115235 and makes it possible
to call `ASTWriter::WriteAST()` with `Preprocessor` only instead of full
`Sema` object. So far, there are no clients that leverage the new
capability - that will come in a follow-up commit.
Commit: b242ae32f56372d7858945df72ce2f00f7e97bc3
https://github.com/llvm/llvm-project/commit/b242ae32f56372d7858945df72ce2f00f7e97bc3
Author: David Green <david.green at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/concat-vector.ll
Log Message:
-----------
[AArch64][GlobalISel] Protect against undef first element in CombineShuffleConcat.
In case the first element is undef, we need to look through to find a valid
type for the inputs.
Commit: 74003f11b3e4dd90665f8f8d911f40a22dd940d4
https://github.com/llvm/llvm-project/commit/74003f11b3e4dd90665f8f8d911f40a22dd940d4
Author: Daniel Sanders <daniel_l_sanders at apple.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M llvm/include/llvm/MC/MCDwarf.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCDwarf.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
A llvm/test/MC/AArch64/cfi_val_offset.s
Log Message:
-----------
[mc] Add CFI directive to emit val_offset() rules (#113971)
These specify that the value of the given register in the previous frame
is the CFA plus some offset. This isn't very common but can be necessary
if the original value is normally reconstructed from the stack/frame
pointer instead of being saved on the stack and reloaded from there.
Commit: 750247bc1cc34629a73f8311ccb87e3d7c03ae23
https://github.com/llvm/llvm-project/commit/750247bc1cc34629a73f8311ccb87e3d7c03ae23
Author: David Green <david.green at arm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/Thumb2/csel.ll
Log Message:
-----------
[ARM] Fix APInt assert for CSNEG known bits.
Use APInt::getAllOnes(32), to avoid the assert when constructing an APInt
from -1.
Commit: 2b58458225fb0f9cce6dabce7e4451f86c8c73a5
https://github.com/llvm/llvm-project/commit/2b58458225fb0f9cce6dabce7e4451f86c8c73a5
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
A llvm/test/CodeGen/MIR/skip-mir-comment-trailing-whitespace.mir
Log Message:
-----------
[MIRLexer][RISCV] Eat a space after the Machine comment (#115365)
The MIRPrinter emits ` :: ` at the start of a MMO. The MIRLexer eats all
the white space after the operand and before the `::` when there is no
comment. We need to eat the space after the comment to allow MIRLexer to
parse comments on a MMO.
Commit: 582a4799e1fc8e46b5872fdd38369d097bce79f2
https://github.com/llvm/llvm-project/commit/582a4799e1fc8e46b5872fdd38369d097bce79f2
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/linux/api.td
M libc/spec/posix.td
Log Message:
-----------
[libc] fix lfind old hdrgen (#115760)
Fixes: #114692
Commit: 3a03513fc6ef8f3272d33be19164243c9dbf0452
https://github.com/llvm/llvm-project/commit/3a03513fc6ef8f3272d33be19164243c9dbf0452
Author: Nikita Popov <nikita.ppv at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
R clang/test/AST/attr-lifetime-capture-by.cpp
R clang/test/SemaCXX/attr-lifetime-capture-by.cpp
Log Message:
-----------
Revert "[clang] Introduce [[clang::lifetime_capture_by(X)]] (#111499)"
This reverts commit 8c4331c1abeb33eabf3cdbefa7f2b6e0540e7f4f.
Causes a large compile-time regression, see:
https://llvm-compile-time-tracker.com/compare.php?from=4a68e4cbd2423dcacada8162ab7c4bb8d7f7e2cf&to=8c4331c1abeb33eabf3cdbefa7f2b6e0540e7f4f&stat=instructions:u
Commit: b816c2628919de9a978132347f039ad23794837d
https://github.com/llvm/llvm-project/commit/b816c2628919de9a978132347f039ad23794837d
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
A llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir
R llvm/test/CodeGen/MIR/skip-mir-comment-trailing-whitespace.mir
Log Message:
-----------
[RISCV][MIR] Move skip-mir-comment-trailing-whitespace.mir into RISCV subdirectory
Commit: ef2d6dafc40c5a58532eb773fc74ddd8e1f53a33
https://github.com/llvm/llvm-project/commit/ef2d6dafc40c5a58532eb773fc74ddd8e1f53a33
Author: Rajat Bajpai <rbajpai at nvidia.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/include/llvm/IR/FMF.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
A llvm/test/Transforms/InstCombine/fcmp-fadd-select.ll
Log Message:
-----------
[InstCombine] Transform (fcmp + fadd + sel) into (fcmp + sel + fadd) (#106492)
Transform `fcmp + fadd + sel` into `fcmp + sel + fadd` which enables the
possibility of transforming `fcmp + sel` into `maxnum/minnum`
intrinsics.
Alive2 results:
https://alive2.llvm.org/ce/z/2cmimW
https://alive2.llvm.org/ce/z/Qh9ZJt
https://alive2.llvm.org/ce/z/vtLj3R
Commit: e399322d5ef2919ccd12f28a00e6b24621b11072
https://github.com/llvm/llvm-project/commit/e399322d5ef2919ccd12f28a00e6b24621b11072
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
Log Message:
-----------
[GlobalISel] Import llvm.stepvector (#115721)
Commit: 3d73dbe7f0411a40562773c6a44d4a5d3dede523
https://github.com/llvm/llvm-project/commit/3d73dbe7f0411a40562773c6a44d4a5d3dede523
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
Log Message:
-----------
[AMDGPU] Remove unused AMDGPUISD enum members (NFC) (#115582)
Those were only used in `getTargetNodeName`.
Commit: bf1c86ce1d8e4020c44376176d4aff5cde66bda2
https://github.com/llvm/llvm-project/commit/bf1c86ce1d8e4020c44376176d4aff5cde66bda2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/fcmp-fadd-select.ll
Log Message:
-----------
InstCombine: Regenerate test after "Transform (fcmp + fadd + sel)"
Update for the splat vector syntax, which landed after the last
precheck run.
Commit: c02b8a01b7caf2e4ffe17a123f1bcf59192e4b39
https://github.com/llvm/llvm-project/commit/c02b8a01b7caf2e4ffe17a123f1bcf59192e4b39
Author: Rolf Morel <rolf.morel at intel.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
Log Message:
-----------
[MLIR][Linalg] Fix unclosed code block which broke generated docs - NFC (#115763)
#115319 added a tablegen description for an op (MatmulOp) but missed
closing one of the code blocks in the description. As a result the
generated docs broke, i.e. https://mlir.llvm.org/docs/Dialects/Linalg
was broken after this code block.
Commit: 9eefa922f8ef60a8032db28a33f13ed6d5249d0a
https://github.com/llvm/llvm-project/commit/9eefa922f8ef60a8032db28a33f13ed6d5249d0a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Log Message:
-----------
AMDGPU/GlobalISel: Remove getVRegDef null checks in selector (#115530)
We should be able to assume every virtual register is defined.
Commit: 25d1ac11d537debb217c65c2bcdd087a60cff58e
https://github.com/llvm/llvm-project/commit/25d1ac11d537debb217c65c2bcdd087a60cff58e
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/include/clang/Lex/HeaderSearchOptions.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/GeneratePCH.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
Log Message:
-----------
[clang][deps] Only write preprocessor info into PCMs (#115239)
This patch builds on top of
https://github.com/llvm/llvm-project/pull/115237 and
https://github.com/llvm/llvm-project/pull/115235, only passing the
`Preprocessor` object to `ASTWriter`. This reduces the size of scanning
PCM files by 1/3 and speeds up scans by 16%.
Commit: 77ddcf7cbfb135f09c75c1d611b241f6e851df86
https://github.com/llvm/llvm-project/commit/77ddcf7cbfb135f09c75c1d611b241f6e851df86
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
A llvm/test/CodeGen/SystemZ/dag-combine-07.ll
Log Message:
-----------
[SystemZ] Fix bitwidth problem in FindReplicatedImm(). (#115383)
A test case emerged with an i32 truncating store of an i64 constant
operand, where the i64 constant did not fit in 32 bits, which caused
FindReplicatedImm() to crash.
Make sure to truncate the APInt in these cases.
Commit: 9254b81990a403f0a5d4a96a4e9efc69e19870bc
https://github.com/llvm/llvm-project/commit/9254b81990a403f0a5d4a96a4e9efc69e19870bc
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Log Message:
-----------
[tsan] Fix typo in type (#115769)
Introduced with #114931
Fixes https://github.com/golang/go/issues/70283
Commit: 515e11ae1cd4a29225f61aa31c7f657c8848a539
https://github.com/llvm/llvm-project/commit/515e11ae1cd4a29225f61aa31c7f657c8848a539
Author: Hugh Delaney <hugh.delaney at codeplay.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
Log Message:
-----------
[NVPTX] Use PTX 7.0 in DebugInfo tests (#115757)
Not doing so makes `%ptxas-verify` fail with:
`Feature 'Defining labels in .section' requires PTX ISA .version 7.0 or
later.`
Commit: f1800df5d53e14e2d865273e42bb0a3968129a7f
https://github.com/llvm/llvm-project/commit/f1800df5d53e14e2d865273e42bb0a3968129a7f
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/arm/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/windows/entrypoints.txt
Log Message:
-----------
[libc] fix lfind entrypoints (#115771)
- move arm entrypoint to fullbuild only
- remove baremetal entrypoints; we avoid POSIX on baremetal
- remove darwin/arm and windows entrypoints since these are untested
Fixes: #114692
Commit: 54ae9e7bbae60a2ddc629e0a7a854492c241774d
https://github.com/llvm/llvm-project/commit/54ae9e7bbae60a2ddc629e0a7a854492c241774d
Author: Quinn Dawkins <quinn.dawkins at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
Log Message:
-----------
[mlir][SCF] Fix condition for fusability in consumer fusion API (#115768)
It was previously allowing either a tilable or dps op to be fused. Both
are required for consumer fusion.
Commit: bbf2ad026eb0b399364a889799ef6b45878cd299
https://github.com/llvm/llvm-project/commit/bbf2ad026eb0b399364a889799ef6b45878cd299
Author: Caslyn Tonelli <6718161+Caslyn at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
[libc++] Amend error message for _LIBCPP_HAS_THREAD_API_EXTERNAL (#115774)
Noticed this while debugging a few things following
https://github.com/llvm/llvm-project/pull/112094. Amended error message
to reflect conditional check.
Commit: 36cbc09e636f3c0e93dc450a9464de8dbe92c75f
https://github.com/llvm/llvm-project/commit/36cbc09e636f3c0e93dc450a9464de8dbe92c75f
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][bazel] config macros is a support library (#115776)
Previously __support_macros_config was a cc_library, but making it a
libc_support_library makes things cleaner.
Commit: 1ae0dae368e4bbf2177603d5c310e794c4fd0bd8
https://github.com/llvm/llvm-project/commit/1ae0dae368e4bbf2177603d5c310e794c4fd0bd8
Author: Michael Jones <michaelrj at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/src/stdio/scanf_core/reader.h
M libc/src/stdio/sscanf.cpp
M libc/src/wchar/CMakeLists.txt
M libc/src/wchar/btowc.cpp
M libc/test/integration/src/unistd/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/scanf_core/converter_test.cpp
M libc/test/src/sys/statvfs/linux/CMakeLists.txt
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
Log Message:
-----------
[libc] Clean up skipped and failing cmake (#115400)
I normally run my cmake with LIBC_CMAKE_VERBOSE_LOGGING set to ON so I
can debug build issues more easily. One of the effects of this is I see
which tests/entrypoints are skipped on my machine. This patch fixes up
the tests and entrypoints that were skipped, but easily fixed. These
were:
libc.src.pthread.pthread_spin_destroy
libc.src.pthread.pthread_spin_init
libc.src.pthread.pthread_spin_lock
libc.src.pthread.pthread_spin_trylock
libc.src.pthread.pthread_spin_unlock
(entrypoints were just missing)
libc.src.wchar.btowc
(I forgot to finish it)
libc.test.src.sys.statvfs.linux.statvfs_test
libc.test.src.sys.statvfs.linux.fstatvfs_test
(Incorrect includes for rmdir, needed some cleanup)
libc.test.integration.src.unistd.execve_test
(wrong dep for errno)
libc.test.src.math.smoke.fmaf_test
(add_fp_unittest doesn't support flags)
libc.test.src.stdio.scanf_core.converter_test
(needed to be moved away from string_reader, further cleanup needed)
Commit: 448d7da5626f412fead00114dc7612c0844b4125
https://github.com/llvm/llvm-project/commit/448d7da5626f412fead00114dc7612c0844b4125
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
Log Message:
-----------
[libc][stdfix] disable lkbits on riscv (#115781)
Link: #114912
Link: #115778
Commit: 5098b56d22b53196e92788fbfd70b01212376db4
https://github.com/llvm/llvm-project/commit/5098b56d22b53196e92788fbfd70b01212376db4
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__utility/exception_guard.h
A libcxx/include/__utility/scope_guard.h
M libcxx/include/module.modulemap
M libcxx/include/string
Log Message:
-----------
[libc++] Introduce a standalone __scope_guard and use it in <string> (#114867)
This introduces a new `__scope_guard` without any fancy features. The
scope guard is used in `<string>` to simplify some of the ASan
annotations (especially by making it harder to forget them where
exceptions are thrown).
Commit: ad35450d85bd0d1f222e94cac91d884b7ed6c77b
https://github.com/llvm/llvm-project/commit/ad35450d85bd0d1f222e94cac91d884b7ed6c77b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 5098b56d22b5
Commit: 615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c
https://github.com/llvm/llvm-project/commit/615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
Log Message:
-----------
[RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.
Commit: 375bb38f728874c371ea044bcd62b3869ea25e98
https://github.com/llvm/llvm-project/commit/375bb38f728874c371ea044bcd62b3869ea25e98
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Add i32 zext.h pattern for Zbkb.
This resolves a FIXME and reduces tests diffs from later patches
remove i32 as a legal type.
Commit: e8c4842f0ce7a81440e2147a0c9bcc690714a6e5
https://github.com/llvm/llvm-project/commit/e8c4842f0ce7a81440e2147a0c9bcc690714a6e5
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/Parse/ParseOpenMP.cpp
Log Message:
-----------
[clang][OpenMP][NFC] Move 'allocate' clause modifier parsing into fun… (#115775)
…ction
Parsing of 'allocate' clause modifier ('allocator') has been moved into
a separate function in anticipation of adding another modifier
('align').
Commit: 28cdebf7bae4aae5f79272cbdf324f9e8110aed3
https://github.com/llvm/llvm-project/commit/28cdebf7bae4aae5f79272cbdf324f9e8110aed3
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libc/config/linux/riscv/entrypoints.txt
Log Message:
-----------
[libc][stdfix] disable ulkbits on riscv (#115781) (#115792)
I should have disabled this in #115781. Mea culpa.
Link: #114912
Link: #115778
Link: #115781
Commit: eaed095a566cf75aa7df208defeb101ce1a6ed96
https://github.com/llvm/llvm-project/commit/eaed095a566cf75aa7df208defeb101ce1a6ed96
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
Log Message:
-----------
Revert "Reapply "[libc++abi] Stop copying headers to the build directory"" (#115793)
Reverts llvm/llvm-project#115379
Reverting since this broke the Fuchsia builders.
Commit: c280522f7e359117adde10de4158f9f6fec20a7b
https://github.com/llvm/llvm-project/commit/c280522f7e359117adde10de4158f9f6fec20a7b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Remove s32 support for G_ADD/SUB/AND/OR/XOR on RV64.
This is consistent with other patches to remove s32 recently.
Commit: f109517d153609d4a8a3a3d3d3cc06da1b629364
https://github.com/llvm/llvm-project/commit/f109517d153609d4a8a3a3d3d3cc06da1b629364
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M lldb/include/lldb/Core/Disassembler.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/API/SBFunction.cpp
M lldb/source/API/SBSymbol.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectDisassemble.h
M lldb/source/Commands/Options.td
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.cpp
M lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/Symbol.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/ThreadPlanTracer.cpp
M lldb/source/Target/TraceDumper.cpp
A lldb/test/Shell/Commands/command-disassemble-cpu-features.yaml
M lldb/unittests/Disassembler/ARM/TestArm64Disassembly.cpp
M lldb/unittests/Disassembler/ARM/TestArmv7Disassembly.cpp
M lldb/unittests/Disassembler/RISCV/TestMCDisasmInstanceRISCV.cpp
M lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp
Log Message:
-----------
[lldb] Support overriding the disassembly CPU & features (#115382)
Add the ability to override the disassembly CPU and CPU features through
a target setting (`target.disassembly-cpu` and
`target.disassembly-features`) and a `disassemble` command option
(`--cpu` and `--features`).
This is especially relevant for architectures like RISC-V which relies
heavily on CPU extensions.
The majority of this patch is plumbing the options through. I recommend
looking at DisassemblerLLVMC and the test for the observable change in
behavior.
Commit: 49e004fbe0416bc23ebea8824805fd7f07f90fa8
https://github.com/llvm/llvm-project/commit/49e004fbe0416bc23ebea8824805fd7f07f90fa8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg.ll
Log Message:
-----------
[nfc][msan] Regenerate tests missing FileCheck (#115794)
Extracted and updated from #115018
Co-authored-by: Kamil Kashapov <kashapov at ispras.ru>
Commit: da032a609c1bde6f6775cf1650e08a205920d920
https://github.com/llvm/llvm-project/commit/da032a609c1bde6f6775cf1650e08a205920d920
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
Log Message:
-----------
[Wunsafe-buffer-usage] Fix false positives in handling string literals. (#115552)
Do not warn when a string literal is indexed and the idex value is
within the bounds of the length of the string.
(rdar://139106996)
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 31dc2b9aa06f998472fa4a7f147a778ebdc80003
https://github.com/llvm/llvm-project/commit/31dc2b9aa06f998472fa4a7f147a778ebdc80003
Author: Douglas <Douglas.Gliner at sony.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M flang/include/flang/Lower/CustomIntrinsicCall.h
Log Message:
-----------
[flang] Fix typo in `CustomIntrinsicCall.h` (NFC) (#115789)
Fix typo in `CustomIntrinsicCall.h`: `DEPRICATED` -> `DEPRECATED`
Commit: de2fad32513f7420988df1cf99aff90e0a067469
https://github.com/llvm/llvm-project/commit/de2fad32513f7420988df1cf99aff90e0a067469
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
Log Message:
-----------
[Clang] Fix dependent expression handling for assumptions (#115646)
The function definition instantiation assumes any declarations used
inside are already transformed before transforming the body, so we need
to preserve the transformed expression of CXXAssumeAttr even if it is
not a constant expression. Moreover, the full expression of the
assumption should also entail a potential lambda capture transformation,
hence the call to ActOnFinishFullExpr() after TransformExpr().
Fixes #114787
Commit: aad256598d7fd14d736eda76ee9eba8905bd84b8
https://github.com/llvm/llvm-project/commit/aad256598d7fd14d736eda76ee9eba8905bd84b8
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll
A llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll
Log Message:
-----------
[LoongArch] Pre-commit test for vreplgr2vr + vinsgr2vr intrinsics (#115702)
Inspired by https://github.com/llvm/llvm-project/issues/101624.
A later commit will optimize it.
Commit: 3b29a8a00809e868e3df7e687695670ff5077fbd
https://github.com/llvm/llvm-project/commit/3b29a8a00809e868e3df7e687695670ff5077fbd
Author: Min <45393763+MinxuanZ at users.noreply.github.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilPosix.cpp
Log Message:
-----------
[libfuzzer] use timer_create() instead of setitimer() for linux (#110274)
SetTimer() now uses setitimer() to sending SIGALRM every `
UnitTimeoutSec/2 + 1` s
Set UnitTimeoutSec with the `-timeout=` option
"POSIX.1-2008 marks getitimer() and setitimer() obsolete" and also has
some issues regarding accuracy of the timers under load . See
https://linux.die.net/man/2/setitimer.
I propose using timer_create() and sigaction() ,See
http://man7.org/linux/man-pages/man2/timer_create.2.html
# test result on my x86_64 linux
`make check-fuzzer`
Commit: e855feac41fd89aebf540a155d21f12a3e82f05b
https://github.com/llvm/llvm-project/commit/e855feac41fd89aebf540a155d21f12a3e82f05b
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/SizeofExpressionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/sizeof-expression.cpp
Log Message:
-----------
[clang-tidy] fix bugprone-sizeof-expression when sizeof expression with template types (#115275)
Fixed: #115175.
`dependent type` are not the same even pointers are the same.
---------
Co-authored-by: whisperity <whisperity at gmail.com>
Commit: f9125ddc1faafaceac9064e889cd9b4a77523677
https://github.com/llvm/llvm-project/commit/f9125ddc1faafaceac9064e889cd9b4a77523677
Author: Florian Mayer <fmayer at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilPosix.cpp
Log Message:
-----------
Revert "[libfuzzer] use timer_create() instead of setitimer() for linux" (#115811)
Reverts llvm/llvm-project#110274
Buildbots broke
Commit: d1e17a3f23a30815030b784d813141a469b3d7fb
https://github.com/llvm/llvm-project/commit/d1e17a3f23a30815030b784d813141a469b3d7fb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
Log Message:
-----------
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
Unless the shift amount is constant. In that case we zero extend the
shift amount and promote the other input the same way widenScalar would.
I'm not using widenScalar because that requires a separate call for each
operand so it was easier to do both operands at once.
Commit: b4339dd612597bf3fae01e42d644ba709e4ae446
https://github.com/llvm/llvm-project/commit/b4339dd612597bf3fae01e42d644ba709e4ae446
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[RISCV] Promote s32 G_SEXT_INREG for RV64
Commit: 3aa24eae52aa463ce47b528879a9a24e04956b88
https://github.com/llvm/llvm-project/commit/3aa24eae52aa463ce47b528879a9a24e04956b88
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Log Message:
-----------
[SelectionDAG] Simplify classof of MemSDNode and MemIntrinsicSDNode (NFC) (#115720)
`SDNodeBits.IsMemIntrinsic` is set if and only if the node is an
instance of `MemIntrinsicSDNode`. Thus, to check if a node is an
instance of `MemIntrinsicSDNode` we only need to check this bit.
Commit: ffa45f2e6aafaf3ed51919beb886325e908d4c20
https://github.com/llvm/llvm-project/commit/ffa45f2e6aafaf3ed51919beb886325e908d4c20
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
Log Message:
-----------
[RISCV][GISel] Use correct constant for i32 INT_MAX in test. NFC
Commit: 23fbaff9a3fd2b26418e0c2f10b701049399251f
https://github.com/llvm/llvm-project/commit/23fbaff9a3fd2b26418e0c2f10b701049399251f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Source.cpp
M clang/lib/AST/ByteCode/Source.h
Log Message:
-----------
[ByteCode] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115809)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: 82d5dd28b4de7245088f7ed40da37f8cf80461e4
https://github.com/llvm/llvm-project/commit/82d5dd28b4de7245088f7ed40da37f8cf80461e4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.cpp
M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
Log Message:
-----------
[RISCV] Remove unused includes (NFC) (#115814)
Identified with misc-include-cleaner.
Commit: f77101ea7913ab6a6b28ad03c152c615a89900f6
https://github.com/llvm/llvm-project/commit/f77101ea7913ab6a6b28ad03c152c615a89900f6
Author: Malay Sanghi <malay.sanghi at intel.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amxmovrsintrin.h
A clang/lib/Headers/amxmovrstransposeintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/amx_movrs.c
A clang/test/CodeGen/X86/amx_movrs_api.c
A clang/test/CodeGen/X86/amx_movrs_errors.c
A clang/test/CodeGen/X86/amx_movrs_tranpose.c
A clang/test/CodeGen/X86/amx_movrs_tranpose_api.c
A clang/test/CodeGen/X86/amx_movrs_transpose_errors.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/amx_movrs_intrinsics.ll
A llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
A llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
A llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
A llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
Log Message:
-----------
[X86][AMX] Support AMX-MOVRS (#115151)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: adb476b0125127939fd116f616a0c18909d4a377
https://github.com/llvm/llvm-project/commit/adb476b0125127939fd116f616a0c18909d4a377
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[nfc][msan] Clang-format MemorySanitizer.cpp (#115828)
Extracted from #109284
Co-authored-by: Kamil Kashapov <kashapov at ispras.ru>
Commit: 0c5bf565ba7059ca8542c522fcab019f2e2c82bb
https://github.com/llvm/llvm-project/commit/0c5bf565ba7059ca8542c522fcab019f2e2c82bb
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port f77101ea7913
Commit: 6a857fe8b960cb26cf03a0c825250726589a7771
https://github.com/llvm/llvm-project/commit/6a857fe8b960cb26cf03a0c825250726589a7771
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-11-11 (Mon, 11 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
Log Message:
-----------
[RISCV][GISel] Promote s32 G_CONSTANT on RV64.
Commit: 956361ca080a689a96b6552d28681aaf0ad2f494
https://github.com/llvm/llvm-project/commit/956361ca080a689a96b6552d28681aaf0ad2f494
Author: Jim Lin <jim at andestech.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Zabha/Zacas implies Zaamo (#115694)
The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.
Commit: 28e4aad45a64ec893c02f21b9c2afe7efe5f4a2a
https://github.com/llvm/llvm-project/commit/28e4aad45a64ec893c02f21b9c2afe7efe5f4a2a
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/trunctfbf2.c
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/test/CodeGen/X86/bfloat.ll
Log Message:
-----------
[X86][BF16] Add libcall for FP128 -> BF16 (#115825)
This is to fix #115710.
Commit: fa9888747548a8965ed9932daa53281794ebc5b6
https://github.com/llvm/llvm-project/commit/fa9888747548a8965ed9932daa53281794ebc5b6
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[MLIR][LLVM] Cleanup attr-dict printing (NFC) (#115765)
This commit simplifies the custom attribute dictionary printing and uses
it only for printing ops that have fast math flags.
Commit: 93589057830b2c3c35500ee8cac25c717a1e98f9
https://github.com/llvm/llvm-project/commit/93589057830b2c3c35500ee8cac25c717a1e98f9
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrFormats.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrSPE.td
M llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
M llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
M llvm/test/MC/PowerPC/ppc64-errors.s
Log Message:
-----------
[PowerPC] Add error for incorrect use of memory operands (#114277)
If an instruction doesn't support memory operands, but one is provided,
an error should be raised. And conversely, if an instruction requires a
memory operand, but none is given, an error should be raised.
Commit: e8db4a5d4351fec0d9a1f1a214b7d2e1c2cb876d
https://github.com/llvm/llvm-project/commit/e8db4a5d4351fec0d9a1f1a214b7d2e1c2cb876d
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M .github/CODEOWNERS
M bolt/include/bolt/Profile/YAMLProfileReader.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/PseudoProbeRewriter.cpp
M clang-tools-extra/clang-tidy/bugprone/SizeofExpressionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ThrowKeywordMissingCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/sizeof-expression.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/throw-keyword-missing.cpp
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/CIR/CIRGenerator.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Lex/HeaderSearchOptions.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/AST/ByteCode/Descriptor.h
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Source.cpp
M clang/lib/AST/ByteCode/Source.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Attributes.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amdgpuintrin.h
M clang/lib/Headers/amxavx512intrin.h
A clang/lib/Headers/amxmovrsintrin.h
A clang/lib/Headers/amxmovrstransposeintrin.h
A clang/lib/Headers/amxtf32intrin.h
A clang/lib/Headers/amxtf32transposeintrin.h
M clang/lib/Headers/emmintrin.h
A clang/lib/Headers/gpuintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/mmintrin.h
A clang/lib/Headers/nvptxintrin.h
M clang/lib/Headers/openmp_wrappers/complex_cmath.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaFunctionEffects.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/Serialization/GeneratePCH.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
A clang/test/AST/HLSL/AppendStructuredBuffer-AST.hlsl
A clang/test/AST/HLSL/ConsumeStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/RWStructuredBuffer-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffer-AST.hlsl
A clang/test/C/C2y/n3341.c
A clang/test/C/C2y/n3342.c
A clang/test/C/C2y/n3346.c
M clang/test/ClangScanDeps/diagnostics.c
M clang/test/ClangScanDeps/header-search-pruning-transitive.c
M clang/test/ClangScanDeps/link-libraries.c
M clang/test/ClangScanDeps/modules-context-hash.c
M clang/test/ClangScanDeps/modules-dep-args.c
M clang/test/ClangScanDeps/modules-extern-submodule.c
M clang/test/ClangScanDeps/modules-extern-unrelated.m
M clang/test/ClangScanDeps/modules-file-path-isolation.c
M clang/test/ClangScanDeps/modules-fmodule-name-no-module-built.m
M clang/test/ClangScanDeps/modules-full-by-mod-name.c
M clang/test/ClangScanDeps/modules-full.cpp
M clang/test/ClangScanDeps/modules-implicit-dot-private.m
M clang/test/ClangScanDeps/modules-incomplete-umbrella.c
M clang/test/ClangScanDeps/modules-inferred.m
M clang/test/ClangScanDeps/modules-no-undeclared-includes.c
M clang/test/ClangScanDeps/modules-pch-common-submodule.c
M clang/test/ClangScanDeps/modules-pch-common-via-submodule.c
M clang/test/ClangScanDeps/modules-pch.c
M clang/test/ClangScanDeps/modules-priv-fw-from-pub.m
M clang/test/ClangScanDeps/modules-redefinition.m
M clang/test/ClangScanDeps/modules-symlink-dir-vfs.c
M clang/test/ClangScanDeps/modules-transitive.c
M clang/test/ClangScanDeps/optimize-vfs.m
M clang/test/ClangScanDeps/removed-args.c
A clang/test/CodeGen/X86/amx_movrs.c
A clang/test/CodeGen/X86/amx_movrs_api.c
A clang/test/CodeGen/X86/amx_movrs_errors.c
A clang/test/CodeGen/X86/amx_movrs_tranpose.c
A clang/test/CodeGen/X86/amx_movrs_tranpose_api.c
A clang/test/CodeGen/X86/amx_movrs_transpose_errors.c
A clang/test/CodeGen/X86/amx_tf32.c
A clang/test/CodeGen/X86/amx_tf32_api.c
A clang/test/CodeGen/X86/amx_tf32_errors.c
A clang/test/CodeGen/X86/amx_tf32_inline_asm.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/aarch64-pure-scalable-args.c
A clang/test/CodeGenHLSL/builtins/AppendStructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/builtins/ConsumeStructuredBuffer-elementtype.hlsl
M clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl
M clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip
M clang/test/Driver/riscv-profiles.c
M clang/test/Driver/x86-target-features.c
A clang/test/Headers/gpuintrin.c
A clang/test/Headers/gpuintrin_lang.c
M clang/test/Misc/warning-flags.c
M clang/test/OpenMP/depobj_codegen.cpp
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
A clang/test/Sema/attr-lifetimebound.c
M clang/test/Sema/attr-nonblocking-constraints.cpp
M clang/test/Sema/declspec.c
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/loop-ast.cpp
M clang/test/SemaOpenACC/loop-construct-gang-ast.cpp
M clang/test/SemaOpenACC/loop-construct-vector-ast.cpp
M clang/test/SemaOpenACC/loop-construct-worker-ast.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/utils/TableGen/NeonEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/bolt.lit.site.cfg.in
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/lit.site.cfg.in
A clang/utils/perf-training/llvm-support/build.test
M clang/www/c_status.html
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/trunctfbf2.c
M compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
M compiler-rt/lib/fuzzer/CMakeLists.txt
M compiler-rt/lib/fuzzer/tests/CMakeLists.txt
M compiler-rt/lib/msan/tests/CMakeLists.txt
M compiler-rt/lib/tsan/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Lower/CustomIntrinsicCall.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Transforms/CUFOpConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/parse-tree.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/runtime/CUDA/kernel.cpp
M flang/test/Fir/CUDA/cuda-alloc-free.fir
M flang/test/Lower/CUDA/cuda-kernel-calls.cuf
A flang/test/Lower/OpenMP/Todo/ordered.f90
M flang/test/Lower/OpenMP/implicit-dsa.f90
M flang/test/Lower/OpenMP/statement-function.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/task.f90
M flang/test/Lower/OpenMP/task2.f90
M flang/test/Parser/OpenMP/depobj-construct.f90
A flang/test/Parser/OpenMP/doacross-clause.f90
A flang/test/Parser/OpenMP/ordered-depend.f90
M flang/test/Parser/cuf-sanity-common
M flang/test/Parser/cuf-sanity-tree.CUF
M flang/test/Parser/cuf-sanity-unparse.CUF
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend06.f90
M flang/test/Semantics/OpenMP/depobj-construct-v50.f90
M flang/test/Semantics/OpenMP/depobj-construct-v51.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
A flang/test/Semantics/OpenMP/doacross.f90
M flang/test/Semantics/OpenMP/ordered01.f90
M flang/test/Semantics/OpenMP/ordered03.f90
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/libc_search.rst
M libc/docs/math/index.rst
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__lsearchcompare_t.h
A libc/include/llvm-libc-types/stdfix-types.h
M libc/newhdrgen/yaml/math.yaml
M libc/newhdrgen/yaml/search.yaml
M libc/newhdrgen/yaml/stdfix.yaml
M libc/spec/posix.td
M libc/spec/stdc_ext.td
M libc/src/__support/fixed_point/fx_bits.h
M libc/src/math/CMakeLists.txt
M libc/src/math/cospif16.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/log1p.cpp
A libc/src/math/generic/tanpif16.cpp
A libc/src/math/tanpif16.h
M libc/src/search/CMakeLists.txt
A libc/src/search/lfind.cpp
A libc/src/search/lfind.h
M libc/src/stdfix/CMakeLists.txt
A libc/src/stdfix/hkbits.cpp
A libc/src/stdfix/hkbits.h
A libc/src/stdfix/hrbits.cpp
A libc/src/stdfix/hrbits.h
A libc/src/stdfix/kbits.cpp
A libc/src/stdfix/kbits.h
A libc/src/stdfix/lkbits.cpp
A libc/src/stdfix/lkbits.h
A libc/src/stdfix/lrbits.cpp
A libc/src/stdfix/lrbits.h
A libc/src/stdfix/rbits.cpp
A libc/src/stdfix/rbits.h
A libc/src/stdfix/uhkbits.cpp
A libc/src/stdfix/uhkbits.h
A libc/src/stdfix/uhrbits.cpp
A libc/src/stdfix/uhrbits.h
A libc/src/stdfix/ukbits.cpp
A libc/src/stdfix/ukbits.h
A libc/src/stdfix/ulkbits.cpp
A libc/src/stdfix/ulkbits.h
A libc/src/stdfix/ulrbits.cpp
A libc/src/stdfix/ulrbits.h
A libc/src/stdfix/urbits.cpp
A libc/src/stdfix/urbits.h
M libc/src/stdio/scanf_core/reader.h
M libc/src/stdio/sscanf.cpp
M libc/src/wchar/CMakeLists.txt
M libc/src/wchar/btowc.cpp
M libc/test/integration/src/unistd/CMakeLists.txt
M libc/test/src/math/CMakeLists.txt
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/log1p_test.cpp
A libc/test/src/math/smoke/tanpif16_test.cpp
A libc/test/src/math/tanpif16_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/lfind_test.cpp
M libc/test/src/stdfix/CMakeLists.txt
A libc/test/src/stdfix/FxBitsTest.h
A libc/test/src/stdfix/hkbits_test.cpp
A libc/test/src/stdfix/hrbits_test.cpp
A libc/test/src/stdfix/kbits_test.cpp
A libc/test/src/stdfix/lkbits_test.cpp
A libc/test/src/stdfix/lrbits_test.cpp
A libc/test/src/stdfix/rbits_test.cpp
A libc/test/src/stdfix/uhkbits_test.cpp
A libc/test/src/stdfix/uhrbits_test.cpp
A libc/test/src/stdfix/ukbits_test.cpp
A libc/test/src/stdfix/ulkbits_test.cpp
A libc/test/src/stdfix/ulrbits_test.cpp
A libc/test/src/stdfix/urbits_test.cpp
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/scanf_core/converter_test.cpp
M libc/test/src/sys/statvfs/linux/CMakeLists.txt
M libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp
M libc/test/src/sys/statvfs/linux/statvfs_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libcxx/include/CMakeLists.txt
M libcxx/include/__config
M libcxx/include/__cxx03/CMakeLists.txt
M libcxx/include/__flat_map/flat_map.h
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/static_bounded_iter.h
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/apple.h
R libcxx/include/__locale_dir/locale_base_api/freebsd.h
A libcxx/include/__locale_dir/support/apple.h
A libcxx/include/__locale_dir/support/bsd_like.h
A libcxx/include/__locale_dir/support/freebsd.h
R libcxx/include/__type_traits/add_const.h
R libcxx/include/__type_traits/add_cv.h
A libcxx/include/__type_traits/add_cv_quals.h
R libcxx/include/__type_traits/add_volatile.h
M libcxx/include/__type_traits/is_trivially_assignable.h
M libcxx/include/__utility/as_const.h
M libcxx/include/__utility/exception_guard.h
A libcxx/include/__utility/scope_guard.h
M libcxx/include/any
M libcxx/include/iomanip
M libcxx/include/module.modulemap
M libcxx/include/string
M libcxx/include/type_traits
M libcxx/include/variant
M libcxx/test/benchmarks/GenerateInput.h
M libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.conv.compile.pass.cpp
A libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
A libcxx/test/libcxx/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.assign/member_swap.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.assign/move_assign.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.cons/move.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/iostreamclass/iostream.cons/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/bool.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/double.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/float.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/int.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long_double.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/long_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/short.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_int.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_long_long.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream.formatted.arithmetic/unsigned_short.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/signed_char.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/signed_char_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/unsigned_char.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/unsigned_char_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.formatted/istream_extractors/wchar_t_pointer.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.manip/ws.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_pointer_size.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_pointer_size_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/get_streambuf_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/getline_pointer_size.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/getline_pointer_size_chart.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/ignore.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/peek.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/putback.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/read.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/readsome.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/seekg.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/seekg_off.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/sync.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/tellg.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream.unformatted/unget.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.assign/member_swap.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.assign/move_assign.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.cons/move.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream.cons/streambuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/input.streams/istream/istream_sentry/ctor.pass.cpp
M libcxx/utils/libcxx/header_information.py
M libcxxabi/CMakeLists.txt
M libcxxabi/include/CMakeLists.txt
M lld/COFF/InputFiles.cpp
M lld/ELF/Driver.cpp
M lld/test/COFF/Inputs/loadconfig-arm64ec.s
M lld/test/COFF/arm64ec-pdb.test
A lld/test/COFF/lto-arm64ec.ll
M lld/test/ELF/aarch64-feature-pac.s
M lld/test/ELF/aarch64-feature-pauth.s
A lld/test/wasm/lto/thinlto-emit-index.ll
A lld/test/wasm/lto/thinlto-object-suffix-replace.ll
A lld/test/wasm/lto/thinlto-prefix-replace.ll
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/InputFiles.h
M lld/wasm/LTO.cpp
M lld/wasm/Options.td
M lldb/CMakeLists.txt
M lldb/cmake/modules/FindLuaAndSwig.cmake
M lldb/docs/resources/build.rst
M lldb/include/lldb/Core/Disassembler.h
M lldb/include/lldb/Interpreter/CommandObject.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-private-interfaces.h
M lldb/source/API/SBFunction.cpp
M lldb/source/API/SBSymbol.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectDisassemble.cpp
M lldb/source/Commands/CommandObjectDisassemble.h
M lldb/source/Commands/CommandObjectMultiword.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/DumpDataExtractor.cpp
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
M lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/Process/Utility/StopInfoMachException.cpp
M lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
M lldb/source/Symbol/Function.cpp
M lldb/source/Symbol/Symbol.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Target/ThreadPlanTracer.cpp
M lldb/source/Target/TraceDumper.cpp
M lldb/test/API/lang/cpp/const_static_integral_member/TestConstStaticIntegralMember.py
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/API/lldbtest.py
M lldb/test/API/lua_api/TestFileHandle.lua
M lldb/test/API/lua_api/TestLuaAPI.py
M lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py
A lldb/test/Shell/Commands/command-disassemble-cpu-features.yaml
M lldb/test/Shell/Commands/command-disassemble-process.yaml
M lldb/test/Shell/Commands/command-disassemble.s
M lldb/tools/lldb-dap/Breakpoint.cpp
M lldb/tools/lldb-dap/Breakpoint.h
M lldb/tools/lldb-dap/BreakpointBase.cpp
M lldb/tools/lldb-dap/BreakpointBase.h
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/DAPForward.h
M lldb/tools/lldb-dap/ExceptionBreakpoint.cpp
M lldb/tools/lldb-dap/ExceptionBreakpoint.h
M lldb/tools/lldb-dap/FunctionBreakpoint.cpp
M lldb/tools/lldb-dap/FunctionBreakpoint.h
M lldb/tools/lldb-dap/InstructionBreakpoint.cpp
M lldb/tools/lldb-dap/InstructionBreakpoint.h
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/tools/lldb-dap/JSONUtils.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/tools/lldb-dap/SourceBreakpoint.h
M lldb/tools/lldb-dap/Watchpoint.cpp
M lldb/tools/lldb-dap/Watchpoint.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/unittests/Disassembler/ARM/TestArm64Disassembly.cpp
M lldb/unittests/Disassembler/ARM/TestArmv7Disassembly.cpp
M lldb/unittests/Disassembler/RISCV/TestMCDisasmInstanceRISCV.cpp
M lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp
M llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
M llvm/docs/GlobalISel/GenericOpcode.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/ADT/STLFunctionalExtras.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/CodeGen/FinalizeISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/LocalStackSlotAllocation.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineVerifier.h
M llvm/include/llvm/CodeGen/PHIElimination.h
M llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/SelectionDAGISel.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/DebugInfo/GSYM/OutputAggregator.h
M llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
A llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/FMF.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/RuntimeLibcalls.def
M llvm/include/llvm/MC/MCDwarf.h
M llvm/include/llvm/MC/MCPseudoProbe.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ProfileData/CtxInstrContextNode.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/IPO/SampleProfile.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/CFIInstrInserter.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LiveRangeShrink.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/OptimizePHIs.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TailDuplication.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DebugInfo/LogicalView/Core/LVLocation.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
A llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
M llvm/lib/ExecutionEngine/Orc/Speculation.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCDwarf.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/SandboxIR/Instruction.cpp
M llvm/lib/SandboxIR/Tracker.cpp
M llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
M llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
M llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
M llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
M llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/SMEPeepholeOpt.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/M68k/M68kFrameLowering.cpp
M llvm/lib/Target/MSP430/MSP430InstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrFormats.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrSPE.td
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVCombine.td
M llvm/lib/Target/RISCV/RISCVConstantPoolValue.cpp
M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
M llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVProfiles.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
M llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
M llvm/lib/Target/X86/X86CallingConv.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86FastTileConfig.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86IndirectThunks.cpp
M llvm/lib/Target/X86/X86InsertPrefetch.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFMA3Info.cpp
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
M llvm/lib/Target/X86/X86LowerAMXType.cpp
M llvm/lib/Target/X86/X86LowerTileCopy.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86PadShortFunction.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/X86/X86PfmCounters.td
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86SchedAlderlakeP.td
M llvm/lib/Target/X86/X86SchedSapphireRapids.td
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Target/X86/X86WinFixupBufferSecurityCheck.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stepvector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/always-uniform.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.o
M llvm/test/CodeGen/AMDGPU/amdpal-elf.ll
M llvm/test/CodeGen/AMDGPU/andorbitset.ll
M llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/attributor-noopt.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-combine.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/code-object-v3.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dag-preserve-disjoint-flag.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/ds_write2.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fma.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
M llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll
M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
M llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-i16-load-store.ll
M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/global_smrd.ll
M llvm/test/CodeGen/AMDGPU/greedy-reverse-local-assignment.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8s.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
M llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/max.i16.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/memcpy-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.ll
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
M llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
M llvm/test/CodeGen/AMDGPU/permlane-op-sel.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
M llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/rcp-pattern.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/required-export-priority.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f32.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
M llvm/test/CodeGen/AMDGPU/sad.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
M llvm/test/CodeGen/AMDGPU/shift-i128.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
M llvm/test/CodeGen/AMDGPU/sign_extend.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-select.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/LoongArch/e_flags.ll
A llvm/test/CodeGen/LoongArch/jr-without-ra.ll
A llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll
A llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll
M llvm/test/CodeGen/M68k/multiple-return.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
A llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir
A llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
M llvm/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/sext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zext-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-and-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-ext-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-or-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-xor-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/float-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
A llvm/test/CodeGen/SystemZ/dag-combine-07.ll
M llvm/test/CodeGen/Thumb2/csel.ll
M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
A llvm/test/CodeGen/X86/amx-tf32-internal.ll
A llvm/test/CodeGen/X86/amx-tf32-intrinsics.ll
A llvm/test/CodeGen/X86/amx_movrs_intrinsics.ll
A llvm/test/CodeGen/X86/amx_movrs_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/amx_transpose_intrinsics.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
A llvm/test/CodeGen/X86/lrshrink-debug.ll
M llvm/test/CodeGen/X86/matrix-multiply.ll
A llvm/test/CodeGen/X86/optnone.mir
M llvm/test/CodeGen/X86/pr40730.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
A llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
R llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
M llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
M llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
M llvm/test/Instrumentation/MemorySanitizer/i386/vararg.ll
A llvm/test/MC/AArch64/cfi_val_offset.s
A llvm/test/MC/Disassembler/RISCV/rv32-invalid-shift.txt
A llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-movrs.txt
A llvm/test/MC/Disassembler/X86/AMX/x86-64-amx-tf32.txt
M llvm/test/MC/PowerPC/ppc64-errors.s
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/X86/AMX/x86-64-amx-movrs-att.s
A llvm/test/MC/X86/AMX/x86-64-amx-movrs-intel.s
A llvm/test/MC/X86/AMX/x86-64-amx-tf32-att.s
A llvm/test/MC/X86/AMX/x86-64-amx-tf32-intel.s
A llvm/test/MachineVerifier/test_step-vector.mir
M llvm/test/Other/new-pm-pgo-O0.ll
M llvm/test/ThinLTO/X86/memprof-icp.ll
M llvm/test/Transforms/CodeGenPrepare/X86/2008-11-24-RAUW-Self.ll
M llvm/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll
M llvm/test/Transforms/ConstantHoisting/AArch64/consthoist-unreachable.ll
M llvm/test/Transforms/ConstantHoisting/ARM/same-offset-multi-types.ll
M llvm/test/Transforms/ConstantHoisting/PowerPC/masks.ll
M llvm/test/Transforms/ConstantHoisting/X86/pr43903-not-all-uses-rebased.ll
M llvm/test/Transforms/Coroutines/coro-async-remat.ll
M llvm/test/Transforms/CorrelatedValuePropagation/2010-09-26-MergeConstantRange.ll
M llvm/test/Transforms/CorrelatedValuePropagation/ashr.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll
M llvm/test/Transforms/CorrelatedValuePropagation/crash.ll
M llvm/test/Transforms/CorrelatedValuePropagation/deopt.ll
M llvm/test/Transforms/CorrelatedValuePropagation/icmp.ll
M llvm/test/Transforms/CorrelatedValuePropagation/minmaxabs.ll
M llvm/test/Transforms/CorrelatedValuePropagation/overflow_predicate.ll
M llvm/test/Transforms/CorrelatedValuePropagation/pr35807.ll
M llvm/test/Transforms/CorrelatedValuePropagation/range.ll
M llvm/test/Transforms/CorrelatedValuePropagation/sdiv.ll
M llvm/test/Transforms/CorrelatedValuePropagation/srem.ll
M llvm/test/Transforms/CorrelatedValuePropagation/udiv-expansion.ll
M llvm/test/Transforms/CorrelatedValuePropagation/urem-expansion.ll
M llvm/test/Transforms/CorrelatedValuePropagation/uscmp.ll
M llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll
M llvm/test/Transforms/DeadStoreElimination/overlap.ll
M llvm/test/Transforms/DeadStoreElimination/simple.ll
M llvm/test/Transforms/EarlyCSE/X86/preserve_memoryssa.ll
M llvm/test/Transforms/FixIrreducible/bug45623.ll
M llvm/test/Transforms/FixIrreducible/unreachable.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionSpecialization/bug55000-read-uninitialized-value.ll
M llvm/test/Transforms/IRCE/pr57335.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/Inline/arg-attr-propagation.ll
A llvm/test/Transforms/InstCombine/fcmp-fadd-select.ll
M llvm/test/Transforms/InstCombine/load-cmp.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
A llvm/test/Transforms/InstCombine/sext-and.ll
M llvm/test/Transforms/InstCombine/vec_shuffle.ll
M llvm/test/Transforms/InstSimplify/cmp-alloca-offsets.ll
M llvm/test/Transforms/LoopStrengthReduce/Power/incomplete-phi.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
A llvm/test/Transforms/LoopUnroll/preserve-branch-debuglocs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
A llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
A llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
A llvm/test/Transforms/LoopVectorize/RISCV/select-invariant-cond-cost.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
A llvm/test/Transforms/LoopVectorize/uitofp-preserve-nneg.ll
A llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
A llvm/test/Transforms/Reassociate/preserve-debugloc.ll
A llvm/test/Transforms/RewriteStatepointsForGC/base-atomicrmw.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
A llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
A llvm/test/Transforms/VectorCombine/X86/pr115575.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/05-dwarf-incorrect-lexical-scope-variable.test
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/Inputs/ThreadLocalStorage.ll
A llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
M llvm/test/tools/llvm-reduce/reduce-flags.ll
M llvm/test/tools/obj2yaml/ELF/verdef-section.yaml
M llvm/tools/lli/lli.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.h
M llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Instrumentation/MemProfUseTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/IR/DialectRegistry.h
M mlir/include/mlir/IR/Dominance.h
M mlir/include/mlir/Target/LLVMIR/ModuleImport.h
M mlir/include/mlir/Transforms/Passes.h
M mlir/lib/Bindings/Python/MainModule.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MemRefToLLVM/AllocLikeConversion.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Linalg/Transforms/DecomposeGenericByUnfoldingPermutation.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Mesh/IR/CMakeLists.txt
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/IR/Dialect.cpp
M mlir/lib/IR/Dominance.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/python/mlir/_mlir_libs/_mlir/__init__.pyi
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Analysis/test-dominance.mlir
A mlir/test/Conversion/MemRefToLLVM/invalid-uint.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
A mlir/test/Dialect/Linalg/decompose-generic-by-unfolding-projected-permutation.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/Dialect/MemRef/ops.mlir
M mlir/test/Dialect/Mesh/canonicalization.mlir
M mlir/test/Dialect/Mesh/invalid.mlir
M mlir/test/Dialect/Mesh/ops.mlir
M mlir/test/Dialect/Mesh/spmdization.mlir
M mlir/test/Dialect/Tensor/mesh-spmdization.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir
M mlir/test/IR/core-ops.mlir
R mlir/test/IR/memory-ops.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer.mlir
A mlir/test/Target/LLVMIR/Import/nneg.ll
M mlir/test/Target/LLVMIR/Import/nsw_nuw.ll
A mlir/test/Target/LLVMIR/nneg.mlir
M mlir/test/Target/LLVMIR/nsw_nuw.mlir
M mlir/test/Transforms/cse.mlir
M mlir/test/lib/IR/TestDominance.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/meinersbur/irbuilder-extract-refactor
Commit: b707c7e837022b5e0fafbdfe7294266f062ed04c
https://github.com/llvm/llvm-project/commit/b707c7e837022b5e0fafbdfe7294266f062ed04c
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2024-11-12 (Tue, 12 Nov 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/CodeExtractor.h
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/unittests/Transforms/Utils/CodeExtractorTest.cpp
Log Message:
-----------
SwitchCases -> ExtractedFuncRetVals
Compare: https://github.com/llvm/llvm-project/compare/db3c7f98ed26...b707c7e83702
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